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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+f -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck -check-prefix=RV32F %s4 5---6name: implicit_def_gpr7legalized: true8regBankSelected: true9body: |10 bb.0:11 ; RV32F-LABEL: name: implicit_def_gpr12 ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF13 ; RV32F-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[DEF]], [[DEF]]14 ; RV32F-NEXT: $x10 = COPY [[ADD]]15 %0:gprb(s32) = G_IMPLICIT_DEF16 %1:gprb(s32) = G_ADD %0, %017 $x10 = COPY %1(s32)18...19---20name: implicit_def_copy_gpr21legalized: true22regBankSelected: true23body: |24 bb.0:25 ; RV32F-LABEL: name: implicit_def_copy_gpr26 ; RV32F: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF27 ; RV32F-NEXT: $x10 = COPY [[DEF]]28 %0:gprb(s32) = G_IMPLICIT_DEF29 %1:gprb(s32) = COPY %0(s32)30 $x10 = COPY %1(s32)31...32 33---34name: implicit_def_fpr35legalized: true36regBankSelected: true37body: |38 bb.0:39 ; RV32F-LABEL: name: implicit_def_fpr40 ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF41 ; RV32F-NEXT: [[FADD_S:%[0-9]+]]:fpr32 = nofpexcept FADD_S [[DEF]], [[DEF]], 742 ; RV32F-NEXT: $f10_f = COPY [[FADD_S]]43 %0:fprb(s32) = G_IMPLICIT_DEF44 %1:fprb(s32) = G_FADD %0, %045 $f10_f = COPY %1(s32)46...47---48name: implicit_def_copy_fpr49legalized: true50regBankSelected: true51body: |52 bb.0:53 ; RV32F-LABEL: name: implicit_def_copy_fpr54 ; RV32F: [[DEF:%[0-9]+]]:fpr32 = IMPLICIT_DEF55 ; RV32F-NEXT: $f10_f = COPY [[DEF]]56 %0:fprb(s32) = G_IMPLICIT_DEF57 %1:fprb(s32) = COPY %0(s32)58 $f10_f = COPY %1(s32)59...60