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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=instruction-select \5# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s6 7---8name: rotl_i329legalized: true10regBankSelected: true11body: |12 bb.0:13 liveins: $x10, $x1114 15 ; CHECK-LABEL: name: rotl_i3216 ; CHECK: liveins: $x10, $x1117 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1019 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1120 ; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]]21 ; CHECK-NEXT: $x10 = COPY [[ROL]]22 ; CHECK-NEXT: PseudoRET implicit $x1023 %0:gprb(s32) = COPY $x1024 %1:gprb(s32) = COPY $x1125 %2:gprb(s32) = G_ROTL %0, %1(s32)26 $x10 = COPY %2(s32)27 PseudoRET implicit $x1028 29...30---31name: rotr_i3232legalized: true33regBankSelected: true34body: |35 bb.0:36 liveins: $x10, $x1137 38 ; CHECK-LABEL: name: rotr_i3239 ; CHECK: liveins: $x10, $x1140 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1042 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1143 ; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]]44 ; CHECK-NEXT: $x10 = COPY [[ROR]]45 ; CHECK-NEXT: PseudoRET implicit $x1046 %0:gprb(s32) = COPY $x1047 %1:gprb(s32) = COPY $x1148 %2:gprb(s32) = G_ROTR %0, %1(s32)49 $x10 = COPY %2(s32)50 PseudoRET implicit $x1051 52...53---54name: rotl_imm_i3255legalized: true56regBankSelected: true57body: |58 bb.0:59 liveins: $x1060 61 ; CHECK-LABEL: name: rotl_imm_i3262 ; CHECK: liveins: $x1063 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1065 ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 2766 ; CHECK-NEXT: $x10 = COPY [[RORI]]67 ; CHECK-NEXT: PseudoRET implicit $x1068 %0:gprb(s32) = COPY $x1069 %1:gprb(s32) = G_CONSTANT i32 570 %2:gprb(s32) = G_ROTL %0, %1(s32)71 $x10 = COPY %2(s32)72 PseudoRET implicit $x1073 74...75---76name: rotr_imm_i3277legalized: true78regBankSelected: true79body: |80 bb.0:81 liveins: $x1082 83 ; CHECK-LABEL: name: rotr_imm_i3284 ; CHECK: liveins: $x1085 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1087 ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 588 ; CHECK-NEXT: $x10 = COPY [[RORI]]89 ; CHECK-NEXT: PseudoRET implicit $x1090 %0:gprb(s32) = COPY $x1091 %1:gprb(s32) = G_CONSTANT i32 592 %2:gprb(s32) = G_ROTR %0, %1(s32)93 $x10 = COPY %2(s32)94 PseudoRET implicit $x1095 96...97