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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s3# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s4 5# Don't test i1 element types here since they have been widened to i8 in legalization6 7---8name: icmp_nxv1i89legalized: true10regBankSelected: true11tracksRegLiveness: true12body: |13 bb.0.entry:14 ; RV32I-LABEL: name: icmp_nxv1i815 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF16 ; RV32I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */17 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]]18 ; RV32I-NEXT: PseudoRET implicit $v819 ;20 ; RV64I-LABEL: name: icmp_nxv1i821 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF22 ; RV64I-NEXT: [[PseudoVMSLTU_VV_MF8_:%[0-9]+]]:vr = PseudoVMSLTU_VV_MF8 [[DEF]], [[DEF]], -1, 3 /* e8 */23 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_MF8_]]24 ; RV64I-NEXT: PseudoRET implicit $v825 %0:vrb(<vscale x 1 x s8>) = G_IMPLICIT_DEF26 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(ult), %0(<vscale x 1 x s8>), %027 $v8 = COPY %1(<vscale x 1 x s1>)28 PseudoRET implicit $v829 30...31---32name: icmp_nxv2i833legalized: true34regBankSelected: true35tracksRegLiveness: true36body: |37 bb.0.entry:38 ; RV32I-LABEL: name: icmp_nxv2i839 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF40 ; RV32I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */41 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]]42 ; RV32I-NEXT: PseudoRET implicit $v843 ;44 ; RV64I-LABEL: name: icmp_nxv2i845 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF46 ; RV64I-NEXT: [[PseudoVMSLT_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLT_VV_MF4 [[DEF]], [[DEF]], -1, 3 /* e8 */47 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLT_VV_MF4_]]48 ; RV64I-NEXT: PseudoRET implicit $v849 %0:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF50 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(slt), %0(<vscale x 2 x s8>), %051 $v8 = COPY %1(<vscale x 2 x s1>)52 PseudoRET implicit $v853 54...55---56name: icmp_nxv4i857legalized: true58regBankSelected: true59tracksRegLiveness: true60body: |61 bb.0.entry:62 ; RV32I-LABEL: name: icmp_nxv4i863 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF64 ; RV32I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */65 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]]66 ; RV32I-NEXT: PseudoRET implicit $v867 ;68 ; RV64I-LABEL: name: icmp_nxv4i869 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF70 ; RV64I-NEXT: [[PseudoVMSLEU_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLEU_VV_MF2 [[DEF]], [[DEF]], -1, 3 /* e8 */71 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLEU_VV_MF2_]]72 ; RV64I-NEXT: PseudoRET implicit $v873 %0:vrb(<vscale x 4 x s8>) = G_IMPLICIT_DEF74 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(uge), %0(<vscale x 4 x s8>), %075 $v8 = COPY %1(<vscale x 4 x s1>)76 PseudoRET implicit $v877 78...79---80name: icmp_nxv8i881legalized: true82regBankSelected: true83tracksRegLiveness: true84body: |85 bb.0.entry:86 ; RV32I-LABEL: name: icmp_nxv8i887 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF88 ; RV32I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */89 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]]90 ; RV32I-NEXT: PseudoRET implicit $v891 ;92 ; RV64I-LABEL: name: icmp_nxv8i893 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF94 ; RV64I-NEXT: [[PseudoVMSLE_VV_M1_:%[0-9]+]]:vr = PseudoVMSLE_VV_M1 [[DEF]], [[DEF]], -1, 3 /* e8 */95 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_M1_]]96 ; RV64I-NEXT: PseudoRET implicit $v897 %0:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF98 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(sge), %0(<vscale x 8 x s8>), %099 $v8 = COPY %1(<vscale x 8 x s1>)100 PseudoRET implicit $v8101 102...103---104name: icmp_nxv16i8105legalized: true106regBankSelected: true107tracksRegLiveness: true108body: |109 bb.0.entry:110 ; RV32I-LABEL: name: icmp_nxv16i8111 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF112 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */113 ; RV32I-NEXT: $v8 = COPY %1114 ; RV32I-NEXT: PseudoRET implicit $v8115 ;116 ; RV64I-LABEL: name: icmp_nxv16i8117 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF118 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 3 /* e8 */119 ; RV64I-NEXT: $v8 = COPY %1120 ; RV64I-NEXT: PseudoRET implicit $v8121 %0:vrb(<vscale x 16 x s8>) = G_IMPLICIT_DEF122 %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(ugt), %0(<vscale x 16 x s8>), %0123 $v8 = COPY %1(<vscale x 16 x s1>)124 PseudoRET implicit $v8125 126...127---128name: icmp_nxv32i8129legalized: true130regBankSelected: true131tracksRegLiveness: true132body: |133 bb.0.entry:134 ; RV32I-LABEL: name: icmp_nxv32i8135 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF136 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */137 ; RV32I-NEXT: $v8 = COPY %1138 ; RV32I-NEXT: PseudoRET implicit $v8139 ;140 ; RV64I-LABEL: name: icmp_nxv32i8141 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF142 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 3 /* e8 */143 ; RV64I-NEXT: $v8 = COPY %1144 ; RV64I-NEXT: PseudoRET implicit $v8145 %0:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF146 %1:vrb(<vscale x 32 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 32 x s8>), %0147 $v8 = COPY %1(<vscale x 32 x s1>)148 PseudoRET implicit $v8149 150...151---152name: icmp_nxv64i8153legalized: true154regBankSelected: true155tracksRegLiveness: true156body: |157 bb.0.entry:158 ; RV32I-LABEL: name: icmp_nxv64i8159 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF160 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */161 ; RV32I-NEXT: $v8 = COPY %1162 ; RV32I-NEXT: PseudoRET implicit $v8163 ;164 ; RV64I-LABEL: name: icmp_nxv64i8165 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF166 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 3 /* e8 */167 ; RV64I-NEXT: $v8 = COPY %1168 ; RV64I-NEXT: PseudoRET implicit $v8169 %0:vrb(<vscale x 64 x s8>) = G_IMPLICIT_DEF170 %1:vrb(<vscale x 64 x s1>) = G_ICMP intpred(ule), %0(<vscale x 64 x s8>), %0171 $v8 = COPY %1(<vscale x 64 x s1>)172 PseudoRET implicit $v8173 174...175---176name: icmp_nxv1i16177legalized: true178regBankSelected: true179tracksRegLiveness: true180body: |181 bb.0.entry:182 ; RV32I-LABEL: name: icmp_nxv1i16183 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF184 ; RV32I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */185 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]]186 ; RV32I-NEXT: PseudoRET implicit $v8187 ;188 ; RV64I-LABEL: name: icmp_nxv1i16189 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF190 ; RV64I-NEXT: [[PseudoVMSLE_VV_MF4_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF4 [[DEF]], [[DEF]], -1, 4 /* e16 */191 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF4_]]192 ; RV64I-NEXT: PseudoRET implicit $v8193 %0:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF194 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sle), %0(<vscale x 1 x s16>), %0195 $v8 = COPY %1(<vscale x 1 x s1>)196 PseudoRET implicit $v8197 198...199---200name: icmp_nxv2i16201legalized: true202regBankSelected: true203tracksRegLiveness: true204body: |205 bb.0.entry:206 ; RV32I-LABEL: name: icmp_nxv2i16207 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF208 ; RV32I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */209 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]]210 ; RV32I-NEXT: PseudoRET implicit $v8211 ;212 ; RV64I-LABEL: name: icmp_nxv2i16213 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF214 ; RV64I-NEXT: [[PseudoVMSNE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSNE_VV_MF2 [[DEF]], [[DEF]], -1, 4 /* e16 */215 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSNE_VV_MF2_]]216 ; RV64I-NEXT: PseudoRET implicit $v8217 %0:vrb(<vscale x 2 x s16>) = G_IMPLICIT_DEF218 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ne), %0(<vscale x 2 x s16>), %0219 $v8 = COPY %1(<vscale x 2 x s1>)220 PseudoRET implicit $v8221 222...223---224name: icmp_nxv4i16225legalized: true226regBankSelected: true227tracksRegLiveness: true228body: |229 bb.0.entry:230 ; RV32I-LABEL: name: icmp_nxv4i16231 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF232 ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */233 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]]234 ; RV32I-NEXT: PseudoRET implicit $v8235 ;236 ; RV64I-LABEL: name: icmp_nxv4i16237 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF238 ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 4 /* e16 */239 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]]240 ; RV64I-NEXT: PseudoRET implicit $v8241 %0:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF242 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(eq), %0(<vscale x 4 x s16>), %0243 $v8 = COPY %1(<vscale x 4 x s1>)244 PseudoRET implicit $v8245 246...247---248name: icmp_nxv8i16249legalized: true250regBankSelected: true251tracksRegLiveness: true252body: |253 bb.0.entry:254 ; RV32I-LABEL: name: icmp_nxv8i16255 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF256 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */257 ; RV32I-NEXT: $v8 = COPY %1258 ; RV32I-NEXT: PseudoRET implicit $v8259 ;260 ; RV64I-LABEL: name: icmp_nxv8i16261 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF262 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M2 [[DEF]], [[DEF]], -1, 4 /* e16 */263 ; RV64I-NEXT: $v8 = COPY %1264 ; RV64I-NEXT: PseudoRET implicit $v8265 %0:vrb(<vscale x 8 x s16>) = G_IMPLICIT_DEF266 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ult), %0(<vscale x 8 x s16>), %0267 $v8 = COPY %1(<vscale x 8 x s1>)268 PseudoRET implicit $v8269 270...271---272name: icmp_nxv16i16273legalized: true274regBankSelected: true275tracksRegLiveness: true276body: |277 bb.0.entry:278 ; RV32I-LABEL: name: icmp_nxv16i16279 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF280 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */281 ; RV32I-NEXT: $v8 = COPY %1282 ; RV32I-NEXT: PseudoRET implicit $v8283 ;284 ; RV64I-LABEL: name: icmp_nxv16i16285 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF286 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M4 [[DEF]], [[DEF]], -1, 4 /* e16 */287 ; RV64I-NEXT: $v8 = COPY %1288 ; RV64I-NEXT: PseudoRET implicit $v8289 %0:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF290 %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(slt), %0(<vscale x 16 x s16>), %0291 $v8 = COPY %1(<vscale x 16 x s1>)292 PseudoRET implicit $v8293 294...295---296name: icmp_nxv32i16297legalized: true298regBankSelected: true299tracksRegLiveness: true300body: |301 bb.0.entry:302 ; RV32I-LABEL: name: icmp_nxv32i16303 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF304 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */305 ; RV32I-NEXT: $v8 = COPY %1306 ; RV32I-NEXT: PseudoRET implicit $v8307 ;308 ; RV64I-LABEL: name: icmp_nxv32i16309 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF310 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M8 [[DEF]], [[DEF]], -1, 4 /* e16 */311 ; RV64I-NEXT: $v8 = COPY %1312 ; RV64I-NEXT: PseudoRET implicit $v8313 %0:vrb(<vscale x 32 x s16>) = G_IMPLICIT_DEF314 %1:vrb(<vscale x 32 x s1>) = G_ICMP intpred(uge), %0(<vscale x 32 x s16>), %0315 $v8 = COPY %1(<vscale x 32 x s1>)316 PseudoRET implicit $v8317 318...319---320name: icmp_nxv1i32321legalized: true322regBankSelected: true323tracksRegLiveness: true324body: |325 bb.0.entry:326 ; RV32I-LABEL: name: icmp_nxv1i32327 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF328 ; RV32I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */329 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]]330 ; RV32I-NEXT: PseudoRET implicit $v8331 ;332 ; RV64I-LABEL: name: icmp_nxv1i32333 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF334 ; RV64I-NEXT: [[PseudoVMSLE_VV_MF2_:%[0-9]+]]:vr = PseudoVMSLE_VV_MF2 [[DEF]], [[DEF]], -1, 5 /* e32 */335 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLE_VV_MF2_]]336 ; RV64I-NEXT: PseudoRET implicit $v8337 %0:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF338 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(sge), %0(<vscale x 1 x s32>), %0339 $v8 = COPY %1(<vscale x 1 x s1>)340 PseudoRET implicit $v8341 342...343---344name: icmp_nxv2i32345legalized: true346regBankSelected: true347tracksRegLiveness: true348body: |349 bb.0.entry:350 ; RV32I-LABEL: name: icmp_nxv2i32351 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF352 ; RV32I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */353 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]]354 ; RV32I-NEXT: PseudoRET implicit $v8355 ;356 ; RV64I-LABEL: name: icmp_nxv2i32357 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF358 ; RV64I-NEXT: [[PseudoVMSLTU_VV_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VV_M1 [[DEF]], [[DEF]], -1, 5 /* e32 */359 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSLTU_VV_M1_]]360 ; RV64I-NEXT: PseudoRET implicit $v8361 %0:vrb(<vscale x 2 x s32>) = G_IMPLICIT_DEF362 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ugt), %0(<vscale x 2 x s32>), %0363 $v8 = COPY %1(<vscale x 2 x s1>)364 PseudoRET implicit $v8365 366...367---368name: icmp_nxv4i32369legalized: true370regBankSelected: true371tracksRegLiveness: true372body: |373 bb.0.entry:374 ; RV32I-LABEL: name: icmp_nxv4i32375 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF376 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */377 ; RV32I-NEXT: $v8 = COPY %1378 ; RV32I-NEXT: PseudoRET implicit $v8379 ;380 ; RV64I-LABEL: name: icmp_nxv4i32381 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF382 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLT_VV_M2 [[DEF]], [[DEF]], -1, 5 /* e32 */383 ; RV64I-NEXT: $v8 = COPY %1384 ; RV64I-NEXT: PseudoRET implicit $v8385 %0:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF386 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(sgt), %0(<vscale x 4 x s32>), %0387 $v8 = COPY %1(<vscale x 4 x s1>)388 PseudoRET implicit $v8389 390...391---392name: icmp_nxv8i32393legalized: true394regBankSelected: true395tracksRegLiveness: true396body: |397 bb.0.entry:398 ; RV32I-LABEL: name: icmp_nxv8i32399 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF400 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */401 ; RV32I-NEXT: $v8 = COPY %1402 ; RV32I-NEXT: PseudoRET implicit $v8403 ;404 ; RV64I-LABEL: name: icmp_nxv8i32405 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF406 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLEU_VV_M4 [[DEF]], [[DEF]], -1, 5 /* e32 */407 ; RV64I-NEXT: $v8 = COPY %1408 ; RV64I-NEXT: PseudoRET implicit $v8409 %0:vrb(<vscale x 8 x s32>) = G_IMPLICIT_DEF410 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ule), %0(<vscale x 8 x s32>), %0411 $v8 = COPY %1(<vscale x 8 x s1>)412 PseudoRET implicit $v8413 414...415---416name: icmp_nxv16i32417legalized: true418regBankSelected: true419tracksRegLiveness: true420body: |421 bb.0.entry:422 ; RV32I-LABEL: name: icmp_nxv16i32423 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF424 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */425 ; RV32I-NEXT: $v8 = COPY %1426 ; RV32I-NEXT: PseudoRET implicit $v8427 ;428 ; RV64I-LABEL: name: icmp_nxv16i32429 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF430 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLE_VV_M8 [[DEF]], [[DEF]], -1, 5 /* e32 */431 ; RV64I-NEXT: $v8 = COPY %1432 ; RV64I-NEXT: PseudoRET implicit $v8433 %0:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF434 %1:vrb(<vscale x 16 x s1>) = G_ICMP intpred(sle), %0(<vscale x 16 x s32>), %0435 $v8 = COPY %1(<vscale x 16 x s1>)436 PseudoRET implicit $v8437 438...439---440name: icmp_nxv1i64441legalized: true442regBankSelected: true443tracksRegLiveness: true444body: |445 bb.0.entry:446 ; RV32I-LABEL: name: icmp_nxv1i64447 ; RV32I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF448 ; RV32I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */449 ; RV32I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]]450 ; RV32I-NEXT: PseudoRET implicit $v8451 ;452 ; RV64I-LABEL: name: icmp_nxv1i64453 ; RV64I: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF454 ; RV64I-NEXT: [[PseudoVMSEQ_VV_M1_:%[0-9]+]]:vr = PseudoVMSEQ_VV_M1 [[DEF]], [[DEF]], -1, 6 /* e64 */455 ; RV64I-NEXT: $v8 = COPY [[PseudoVMSEQ_VV_M1_]]456 ; RV64I-NEXT: PseudoRET implicit $v8457 %0:vrb(<vscale x 1 x s64>) = G_IMPLICIT_DEF458 %1:vrb(<vscale x 1 x s1>) = G_ICMP intpred(eq), %0(<vscale x 1 x s64>), %0459 $v8 = COPY %1(<vscale x 1 x s1>)460 PseudoRET implicit $v8461 462...463---464name: icmp_nxv2i64465legalized: true466regBankSelected: true467tracksRegLiveness: true468body: |469 bb.0.entry:470 ; RV32I-LABEL: name: icmp_nxv2i64471 ; RV32I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF472 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */473 ; RV32I-NEXT: $v8 = COPY %1474 ; RV32I-NEXT: PseudoRET implicit $v8475 ;476 ; RV64I-LABEL: name: icmp_nxv2i64477 ; RV64I: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF478 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSNE_VV_M2 [[DEF]], [[DEF]], -1, 6 /* e64 */479 ; RV64I-NEXT: $v8 = COPY %1480 ; RV64I-NEXT: PseudoRET implicit $v8481 %0:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF482 %1:vrb(<vscale x 2 x s1>) = G_ICMP intpred(ne), %0(<vscale x 2 x s64>), %0483 $v8 = COPY %1(<vscale x 2 x s1>)484 PseudoRET implicit $v8485 486...487---488name: icmp_nxv4i64489legalized: true490regBankSelected: true491tracksRegLiveness: true492body: |493 bb.0.entry:494 ; RV32I-LABEL: name: icmp_nxv4i64495 ; RV32I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF496 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */497 ; RV32I-NEXT: $v8 = COPY %1498 ; RV32I-NEXT: PseudoRET implicit $v8499 ;500 ; RV64I-LABEL: name: icmp_nxv4i64501 ; RV64I: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF502 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M4 [[DEF]], [[DEF]], -1, 6 /* e64 */503 ; RV64I-NEXT: $v8 = COPY %1504 ; RV64I-NEXT: PseudoRET implicit $v8505 %0:vrb(<vscale x 4 x s64>) = G_IMPLICIT_DEF506 %1:vrb(<vscale x 4 x s1>) = G_ICMP intpred(ult), %0(<vscale x 4 x s64>), %0507 $v8 = COPY %1(<vscale x 4 x s1>)508 PseudoRET implicit $v8509 510...511---512name: icmp_nxv8i64513legalized: true514regBankSelected: true515tracksRegLiveness: true516body: |517 bb.0.entry:518 ; RV32I-LABEL: name: icmp_nxv8i64519 ; RV32I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF520 ; RV32I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */521 ; RV32I-NEXT: $v8 = COPY %1522 ; RV32I-NEXT: PseudoRET implicit $v8523 ;524 ; RV64I-LABEL: name: icmp_nxv8i64525 ; RV64I: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF526 ; RV64I-NEXT: early-clobber %1:vr = PseudoVMSLTU_VV_M8 [[DEF]], [[DEF]], -1, 6 /* e64 */527 ; RV64I-NEXT: $v8 = COPY %1528 ; RV64I-NEXT: PseudoRET implicit $v8529 %0:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF530 %1:vrb(<vscale x 8 x s1>) = G_ICMP intpred(ult), %0(<vscale x 8 x s64>), %0531 $v8 = COPY %1(<vscale x 8 x s1>)532 PseudoRET implicit $v8533 534...535