77 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \3# RUN: -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: negative_vl7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.1:12 ; CHECK-LABEL: name: negative_vl13 ; CHECK: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, -214 ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[ADDI]], 0 /* e8 */15 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]16 ; CHECK-NEXT: PseudoRET implicit $v017 %0:gprb(s32) = G_CONSTANT i32 -218 %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)19 $v0 = COPY %1(<vscale x 1 x s1>)20 PseudoRET implicit $v021...22---23name: nonconst_vl24legalized: true25regBankSelected: true26tracksRegLiveness: true27body: |28 bb.1:29 liveins: $x1030 ; CHECK-LABEL: name: nonconst_vl31 ; CHECK: liveins: $x1032 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x1034 ; CHECK-NEXT: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 [[COPY]], 0 /* e8 */35 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]36 ; CHECK-NEXT: PseudoRET implicit $v037 %0:gprb(s32) = COPY $x1038 %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)39 $v0 = COPY %1(<vscale x 1 x s1>)40 PseudoRET implicit $v041...42 43---44name: nonzero_vl45legalized: true46regBankSelected: true47tracksRegLiveness: true48body: |49 bb.1:50 ; CHECK-LABEL: name: nonzero_vl51 ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 1, 0 /* e8 */52 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]53 ; CHECK-NEXT: PseudoRET implicit $v054 %0:gprb(s32) = G_CONSTANT i32 155 %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)56 $v0 = COPY %1(<vscale x 1 x s1>)57 PseudoRET implicit $v058...59 60---61name: zero_vl62legalized: true63regBankSelected: true64tracksRegLiveness: true65body: |66 bb.1:67 ; CHECK-LABEL: name: zero_vl68 ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 0, 0 /* e8 */69 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]70 ; CHECK-NEXT: PseudoRET implicit $v071 %0:gprb(s32) = G_CONSTANT i32 072 %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)73 $v0 = COPY %1(<vscale x 1 x s1>)74 PseudoRET implicit $v075...76 77