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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s3# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s4 5---6name: select_nxv1i87legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 ; RV32I-LABEL: name: select_nxv1i813 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF14 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF15 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF16 ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */17 ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]18 ; RV32I-NEXT: PseudoRET implicit $v819 ;20 ; RV64I-LABEL: name: select_nxv1i821 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF22 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF23 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF24 ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */25 ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]26 ; RV64I-NEXT: PseudoRET implicit $v827 %0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF28 %1:vrb(<vscale x 2 x s8>) = G_IMPLICIT_DEF29 %2:vrb(<vscale x 2 x s8>) = G_SELECT %0(<vscale x 2 x s1>), %1, %130 $v8 = COPY %2(<vscale x 2 x s8>)31 PseudoRET implicit $v832 33...34---35name: select_nxv4i836legalized: true37regBankSelected: true38tracksRegLiveness: true39body: |40 bb.0.entry:41 ; RV32I-LABEL: name: select_nxv4i842 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF43 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF44 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF45 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */46 ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]47 ; RV32I-NEXT: PseudoRET implicit $v848 ;49 ; RV64I-LABEL: name: select_nxv4i850 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF51 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF52 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF53 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */54 ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]55 ; RV64I-NEXT: PseudoRET implicit $v856 %0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF57 %1:vrb(<vscale x 8 x s8>) = G_IMPLICIT_DEF58 %2:vrb(<vscale x 8 x s8>) = G_SELECT %0(<vscale x 8 x s1>), %1, %159 $v8 = COPY %2(<vscale x 8 x s8>)60 PseudoRET implicit $v861 62...63---64name: select_nxv16i865legalized: true66regBankSelected: true67tracksRegLiveness: true68body: |69 bb.0.entry:70 ; RV32I-LABEL: name: select_nxv16i871 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF72 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF73 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF74 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */75 ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]76 ; RV32I-NEXT: PseudoRET implicit $v8m477 ;78 ; RV64I-LABEL: name: select_nxv16i879 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF80 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF81 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF82 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 3 /* e8 */83 ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]84 ; RV64I-NEXT: PseudoRET implicit $v8m485 %0:vrb(<vscale x 32 x s1>) = G_IMPLICIT_DEF86 %1:vrb(<vscale x 32 x s8>) = G_IMPLICIT_DEF87 %2:vrb(<vscale x 32 x s8>) = G_SELECT %0(<vscale x 32 x s1>), %1, %188 $v8m4 = COPY %2(<vscale x 32 x s8>)89 PseudoRET implicit $v8m490 91...92---93name: select_nxv64i894legalized: true95regBankSelected: true96tracksRegLiveness: true97body: |98 bb.0.entry:99 ; RV32I-LABEL: name: select_nxv64i8100 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF101 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF102 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF103 ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */104 ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]105 ; RV32I-NEXT: PseudoRET implicit $v8106 ;107 ; RV64I-LABEL: name: select_nxv64i8108 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF109 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF110 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF111 ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF4_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */112 ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF4_]]113 ; RV64I-NEXT: PseudoRET implicit $v8114 %0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF115 %1:vrb(<vscale x 1 x s16>) = G_IMPLICIT_DEF116 %2:vrb(<vscale x 1 x s16>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1117 $v8 = COPY %2(<vscale x 1 x s16>)118 PseudoRET implicit $v8119 120...121---122name: select_nxv2i16123legalized: true124regBankSelected: true125tracksRegLiveness: true126body: |127 bb.0.entry:128 ; RV32I-LABEL: name: select_nxv2i16129 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF130 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF131 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF132 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */133 ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]134 ; RV32I-NEXT: PseudoRET implicit $v8135 ;136 ; RV64I-LABEL: name: select_nxv2i16137 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF138 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF139 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF140 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M1_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_M1 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */141 ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_M1_]]142 ; RV64I-NEXT: PseudoRET implicit $v8143 %0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF144 %1:vrb(<vscale x 4 x s16>) = G_IMPLICIT_DEF145 %2:vrb(<vscale x 4 x s16>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1146 $v8 = COPY %2(<vscale x 4 x s16>)147 PseudoRET implicit $v8148 149...150---151name: select_nxv8i16152legalized: true153regBankSelected: true154tracksRegLiveness: true155body: |156 bb.0.entry:157 ; RV32I-LABEL: name: select_nxv8i16158 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF159 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF160 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF161 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */162 ; RV32I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]163 ; RV32I-NEXT: PseudoRET implicit $v8m4164 ;165 ; RV64I-LABEL: name: select_nxv8i16166 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF167 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm4 = IMPLICIT_DEF168 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm4nov0 = IMPLICIT_DEF169 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M4_:%[0-9]+]]:vrm4nov0 = PseudoVMERGE_VVM_M4 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 4 /* e16 */170 ; RV64I-NEXT: $v8m4 = COPY [[PseudoVMERGE_VVM_M4_]]171 ; RV64I-NEXT: PseudoRET implicit $v8m4172 %0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF173 %1:vrb(<vscale x 16 x s16>) = G_IMPLICIT_DEF174 %2:vrb(<vscale x 16 x s16>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1175 $v8m4 = COPY %2(<vscale x 16 x s16>)176 PseudoRET implicit $v8m4177 178...179---180name: select_nxv32i16181legalized: true182regBankSelected: true183tracksRegLiveness: true184body: |185 bb.0.entry:186 ; RV32I-LABEL: name: select_nxv32i16187 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF188 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF189 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF190 ; RV32I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */191 ; RV32I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]192 ; RV32I-NEXT: PseudoRET implicit $v8193 ;194 ; RV64I-LABEL: name: select_nxv32i16195 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF196 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF197 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrnov0 = IMPLICIT_DEF198 ; RV64I-NEXT: [[PseudoVMERGE_VVM_MF2_:%[0-9]+]]:vrnov0 = PseudoVMERGE_VVM_MF2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */199 ; RV64I-NEXT: $v8 = COPY [[PseudoVMERGE_VVM_MF2_]]200 ; RV64I-NEXT: PseudoRET implicit $v8201 %0:vrb(<vscale x 1 x s1>) = G_IMPLICIT_DEF202 %1:vrb(<vscale x 1 x s32>) = G_IMPLICIT_DEF203 %2:vrb(<vscale x 1 x s32>) = G_SELECT %0(<vscale x 1 x s1>), %1, %1204 $v8 = COPY %2(<vscale x 1 x s32>)205 PseudoRET implicit $v8206 207...208---209name: select_nxv2i32210legalized: true211regBankSelected: true212tracksRegLiveness: true213body: |214 bb.0.entry:215 ; RV32I-LABEL: name: select_nxv2i32216 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF217 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF218 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF219 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */220 ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]221 ; RV32I-NEXT: PseudoRET implicit $v8m2222 ;223 ; RV64I-LABEL: name: select_nxv2i32224 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF225 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF226 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF227 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */228 ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]229 ; RV64I-NEXT: PseudoRET implicit $v8m2230 %0:vrb(<vscale x 4 x s1>) = G_IMPLICIT_DEF231 %1:vrb(<vscale x 4 x s32>) = G_IMPLICIT_DEF232 %2:vrb(<vscale x 4 x s32>) = G_SELECT %0(<vscale x 4 x s1>), %1, %1233 $v8m2 = COPY %2(<vscale x 4 x s32>)234 PseudoRET implicit $v8m2235 236...237---238name: select_nxv8i32239legalized: true240regBankSelected: true241tracksRegLiveness: true242body: |243 bb.0.entry:244 ; RV32I-LABEL: name: select_nxv8i32245 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF246 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF247 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF248 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */249 ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]250 ; RV32I-NEXT: PseudoRET implicit $v8m8251 ;252 ; RV64I-LABEL: name: select_nxv8i32253 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF254 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF255 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF256 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 5 /* e32 */257 ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]258 ; RV64I-NEXT: PseudoRET implicit $v8m8259 %0:vrb(<vscale x 16 x s1>) = G_IMPLICIT_DEF260 %1:vrb(<vscale x 16 x s32>) = G_IMPLICIT_DEF261 %2:vrb(<vscale x 16 x s32>) = G_SELECT %0(<vscale x 16 x s1>), %1, %1262 $v8m8 = COPY %2(<vscale x 16 x s32>)263 PseudoRET implicit $v8m8264 265...266---267name: select_nxv1i64268legalized: true269regBankSelected: true270tracksRegLiveness: true271body: |272 bb.0.entry:273 ; RV32I-LABEL: name: select_nxv1i64274 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF275 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF276 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF277 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */278 ; RV32I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]279 ; RV32I-NEXT: PseudoRET implicit $v8m2280 ;281 ; RV64I-LABEL: name: select_nxv1i64282 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF283 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm2 = IMPLICIT_DEF284 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm2nov0 = IMPLICIT_DEF285 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M2_:%[0-9]+]]:vrm2nov0 = PseudoVMERGE_VVM_M2 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */286 ; RV64I-NEXT: $v8m2 = COPY [[PseudoVMERGE_VVM_M2_]]287 ; RV64I-NEXT: PseudoRET implicit $v8m2288 %0:vrb(<vscale x 2 x s1>) = G_IMPLICIT_DEF289 %1:vrb(<vscale x 2 x s64>) = G_IMPLICIT_DEF290 %2:vrb(<vscale x 2 x s64>) = G_SELECT %0(<vscale x 2 x s1>), %1, %1291 $v8m2 = COPY %2(<vscale x 2 x s64>)292 PseudoRET implicit $v8m2293 294...295---296name: select_nxv4i64297legalized: true298regBankSelected: true299tracksRegLiveness: true300body: |301 bb.0.entry:302 ; RV32I-LABEL: name: select_nxv4i64303 ; RV32I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF304 ; RV32I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF305 ; RV32I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF306 ; RV32I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */307 ; RV32I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]308 ; RV32I-NEXT: PseudoRET implicit $v8m8309 ;310 ; RV64I-LABEL: name: select_nxv4i64311 ; RV64I: [[DEF:%[0-9]+]]:vmv0 = IMPLICIT_DEF312 ; RV64I-NEXT: [[DEF1:%[0-9]+]]:vrm8 = IMPLICIT_DEF313 ; RV64I-NEXT: [[DEF2:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF314 ; RV64I-NEXT: [[PseudoVMERGE_VVM_M8_:%[0-9]+]]:vrm8nov0 = PseudoVMERGE_VVM_M8 [[DEF2]], [[DEF1]], [[DEF1]], [[DEF]], -1, 6 /* e64 */315 ; RV64I-NEXT: $v8m8 = COPY [[PseudoVMERGE_VVM_M8_]]316 ; RV64I-NEXT: PseudoRET implicit $v8m8317 %0:vrb(<vscale x 8 x s1>) = G_IMPLICIT_DEF318 %1:vrb(<vscale x 8 x s64>) = G_IMPLICIT_DEF319 %2:vrb(<vscale x 8 x s64>) = G_SELECT %0(<vscale x 8 x s1>), %1, %1320 $v8m8 = COPY %2(<vscale x 8 x s64>)321 PseudoRET implicit $v8m8322 323...324