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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s3# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s4---5name: test_nxv1i86legalized: true7regBankSelected: true8tracksRegLiveness: true9body: |10 bb.0.entry:11 liveins: $v8, $v912 13 ; RV32I-LABEL: name: test_nxv1i814 ; RV32I: liveins: $v8, $v915 ; RV32I-NEXT: {{ $}}16 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v817 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v918 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF19 ; RV32I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */20 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF8_]]21 ; RV32I-NEXT: PseudoRET implicit $v822 ;23 ; RV64I-LABEL: name: test_nxv1i824 ; RV64I: liveins: $v8, $v925 ; RV64I-NEXT: {{ $}}26 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v827 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v928 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF29 ; RV64I-NEXT: [[PseudoVSUB_VV_MF8_:%[0-9]+]]:vr = PseudoVSUB_VV_MF8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */30 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF8_]]31 ; RV64I-NEXT: PseudoRET implicit $v832 %0:vrb(<vscale x 1 x s8>) = COPY $v833 %1:vrb(<vscale x 1 x s8>) = COPY $v934 %2:vrb(<vscale x 1 x s8>) = G_SUB %0, %135 $v8 = COPY %2(<vscale x 1 x s8>)36 PseudoRET implicit $v837 38...39---40name: test_nxv2i841legalized: true42regBankSelected: true43tracksRegLiveness: true44body: |45 bb.0.entry:46 liveins: $v8, $v947 48 ; RV32I-LABEL: name: test_nxv2i849 ; RV32I: liveins: $v8, $v950 ; RV32I-NEXT: {{ $}}51 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v852 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v953 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF54 ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */55 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]]56 ; RV32I-NEXT: PseudoRET implicit $v857 ;58 ; RV64I-LABEL: name: test_nxv2i859 ; RV64I: liveins: $v8, $v960 ; RV64I-NEXT: {{ $}}61 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v862 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v963 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF64 ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */65 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]]66 ; RV64I-NEXT: PseudoRET implicit $v867 %0:vrb(<vscale x 2 x s8>) = COPY $v868 %1:vrb(<vscale x 2 x s8>) = COPY $v969 %2:vrb(<vscale x 2 x s8>) = G_SUB %0, %170 $v8 = COPY %2(<vscale x 2 x s8>)71 PseudoRET implicit $v872 73...74---75name: test_nxv4i876legalized: true77regBankSelected: true78tracksRegLiveness: true79body: |80 bb.0.entry:81 liveins: $v8, $v982 83 ; RV32I-LABEL: name: test_nxv4i884 ; RV32I: liveins: $v8, $v985 ; RV32I-NEXT: {{ $}}86 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v887 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v988 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF89 ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */90 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]]91 ; RV32I-NEXT: PseudoRET implicit $v892 ;93 ; RV64I-LABEL: name: test_nxv4i894 ; RV64I: liveins: $v8, $v995 ; RV64I-NEXT: {{ $}}96 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v897 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v998 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF99 ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */100 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]]101 ; RV64I-NEXT: PseudoRET implicit $v8102 %0:vrb(<vscale x 4 x s8>) = COPY $v8103 %1:vrb(<vscale x 4 x s8>) = COPY $v9104 %2:vrb(<vscale x 4 x s8>) = G_SUB %0, %1105 $v8 = COPY %2(<vscale x 4 x s8>)106 PseudoRET implicit $v8107 108...109---110name: test_nxv8i8111legalized: true112regBankSelected: true113tracksRegLiveness: true114body: |115 bb.0.entry:116 liveins: $v8, $v9117 118 ; RV32I-LABEL: name: test_nxv8i8119 ; RV32I: liveins: $v8, $v9120 ; RV32I-NEXT: {{ $}}121 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8122 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9123 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF124 ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */125 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]126 ; RV32I-NEXT: PseudoRET implicit $v8127 ;128 ; RV64I-LABEL: name: test_nxv8i8129 ; RV64I: liveins: $v8, $v9130 ; RV64I-NEXT: {{ $}}131 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8132 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9133 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF134 ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */135 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]136 ; RV64I-NEXT: PseudoRET implicit $v8137 %0:vrb(<vscale x 8 x s8>) = COPY $v8138 %1:vrb(<vscale x 8 x s8>) = COPY $v9139 %2:vrb(<vscale x 8 x s8>) = G_SUB %0, %1140 $v8 = COPY %2(<vscale x 8 x s8>)141 PseudoRET implicit $v8142 143...144---145name: test_nxv16i8146legalized: true147regBankSelected: true148tracksRegLiveness: true149body: |150 bb.0.entry:151 liveins: $v8m2, $v10m2152 153 ; RV32I-LABEL: name: test_nxv16i8154 ; RV32I: liveins: $v8m2, $v10m2155 ; RV32I-NEXT: {{ $}}156 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2157 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2158 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF159 ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */160 ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]161 ; RV32I-NEXT: PseudoRET implicit $v8m2162 ;163 ; RV64I-LABEL: name: test_nxv16i8164 ; RV64I: liveins: $v8m2, $v10m2165 ; RV64I-NEXT: {{ $}}166 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2167 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2168 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF169 ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */170 ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]171 ; RV64I-NEXT: PseudoRET implicit $v8m2172 %0:vrb(<vscale x 16 x s8>) = COPY $v8m2173 %1:vrb(<vscale x 16 x s8>) = COPY $v10m2174 %2:vrb(<vscale x 16 x s8>) = G_SUB %0, %1175 $v8m2 = COPY %2(<vscale x 16 x s8>)176 PseudoRET implicit $v8m2177 178...179---180name: test_nxv32i8181legalized: true182regBankSelected: true183tracksRegLiveness: true184body: |185 bb.0.entry:186 liveins: $v8m4, $v12m4187 188 ; RV32I-LABEL: name: test_nxv32i8189 ; RV32I: liveins: $v8m4, $v12m4190 ; RV32I-NEXT: {{ $}}191 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4192 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4193 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF194 ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */195 ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]196 ; RV32I-NEXT: PseudoRET implicit $v8m4197 ;198 ; RV64I-LABEL: name: test_nxv32i8199 ; RV64I: liveins: $v8m4, $v12m4200 ; RV64I-NEXT: {{ $}}201 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4202 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4203 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF204 ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */205 ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]206 ; RV64I-NEXT: PseudoRET implicit $v8m4207 %0:vrb(<vscale x 32 x s8>) = COPY $v8m4208 %1:vrb(<vscale x 32 x s8>) = COPY $v12m4209 %2:vrb(<vscale x 32 x s8>) = G_SUB %0, %1210 $v8m4 = COPY %2(<vscale x 32 x s8>)211 PseudoRET implicit $v8m4212 213...214---215name: test_nxv64i8216legalized: true217regBankSelected: true218tracksRegLiveness: true219body: |220 bb.0.entry:221 liveins: $v8m8, $v16m8222 223 ; RV32I-LABEL: name: test_nxv64i8224 ; RV32I: liveins: $v8m8, $v16m8225 ; RV32I-NEXT: {{ $}}226 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8227 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8228 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF229 ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */230 ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]231 ; RV32I-NEXT: PseudoRET implicit $v8m8232 ;233 ; RV64I-LABEL: name: test_nxv64i8234 ; RV64I: liveins: $v8m8, $v16m8235 ; RV64I-NEXT: {{ $}}236 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8237 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8238 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF239 ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 3 /* e8 */, 3 /* ta, ma */240 ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]241 ; RV64I-NEXT: PseudoRET implicit $v8m8242 %0:vrb(<vscale x 64 x s8>) = COPY $v8m8243 %1:vrb(<vscale x 64 x s8>) = COPY $v16m8244 %2:vrb(<vscale x 64 x s8>) = G_SUB %0, %1245 $v8m8 = COPY %2(<vscale x 64 x s8>)246 PseudoRET implicit $v8m8247 248...249---250name: test_nxv1i16251legalized: true252regBankSelected: true253tracksRegLiveness: true254body: |255 bb.0.entry:256 liveins: $v8, $v9257 258 ; RV32I-LABEL: name: test_nxv1i16259 ; RV32I: liveins: $v8, $v9260 ; RV32I-NEXT: {{ $}}261 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8262 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9263 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF264 ; RV32I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */265 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]]266 ; RV32I-NEXT: PseudoRET implicit $v8267 ;268 ; RV64I-LABEL: name: test_nxv1i16269 ; RV64I: liveins: $v8, $v9270 ; RV64I-NEXT: {{ $}}271 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8272 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9273 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF274 ; RV64I-NEXT: [[PseudoVSUB_VV_MF4_:%[0-9]+]]:vr = PseudoVSUB_VV_MF4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */275 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF4_]]276 ; RV64I-NEXT: PseudoRET implicit $v8277 %0:vrb(<vscale x 1 x s16>) = COPY $v8278 %1:vrb(<vscale x 1 x s16>) = COPY $v9279 %2:vrb(<vscale x 1 x s16>) = G_SUB %0, %1280 $v8 = COPY %2(<vscale x 1 x s16>)281 PseudoRET implicit $v8282 283...284---285name: test_nxv2i16286legalized: true287regBankSelected: true288tracksRegLiveness: true289body: |290 bb.0.entry:291 liveins: $v8, $v9292 293 ; RV32I-LABEL: name: test_nxv2i16294 ; RV32I: liveins: $v8, $v9295 ; RV32I-NEXT: {{ $}}296 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8297 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9298 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF299 ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */300 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]]301 ; RV32I-NEXT: PseudoRET implicit $v8302 ;303 ; RV64I-LABEL: name: test_nxv2i16304 ; RV64I: liveins: $v8, $v9305 ; RV64I-NEXT: {{ $}}306 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8307 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9308 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF309 ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */310 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]]311 ; RV64I-NEXT: PseudoRET implicit $v8312 %0:vrb(<vscale x 2 x s16>) = COPY $v8313 %1:vrb(<vscale x 2 x s16>) = COPY $v9314 %2:vrb(<vscale x 2 x s16>) = G_SUB %0, %1315 $v8 = COPY %2(<vscale x 2 x s16>)316 PseudoRET implicit $v8317 318...319---320name: test_nxv4i16321legalized: true322regBankSelected: true323tracksRegLiveness: true324body: |325 bb.0.entry:326 liveins: $v8, $v9327 328 ; RV32I-LABEL: name: test_nxv4i16329 ; RV32I: liveins: $v8, $v9330 ; RV32I-NEXT: {{ $}}331 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8332 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9333 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF334 ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */335 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]336 ; RV32I-NEXT: PseudoRET implicit $v8337 ;338 ; RV64I-LABEL: name: test_nxv4i16339 ; RV64I: liveins: $v8, $v9340 ; RV64I-NEXT: {{ $}}341 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8342 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9343 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF344 ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */345 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]346 ; RV64I-NEXT: PseudoRET implicit $v8347 %0:vrb(<vscale x 4 x s16>) = COPY $v8348 %1:vrb(<vscale x 4 x s16>) = COPY $v9349 %2:vrb(<vscale x 4 x s16>) = G_SUB %0, %1350 $v8 = COPY %2(<vscale x 4 x s16>)351 PseudoRET implicit $v8352 353...354---355name: test_nxv8i16356legalized: true357regBankSelected: true358tracksRegLiveness: true359body: |360 bb.0.entry:361 liveins: $v8m2, $v10m2362 363 ; RV32I-LABEL: name: test_nxv8i16364 ; RV32I: liveins: $v8m2, $v10m2365 ; RV32I-NEXT: {{ $}}366 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2367 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2368 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF369 ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */370 ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]371 ; RV32I-NEXT: PseudoRET implicit $v8m2372 ;373 ; RV64I-LABEL: name: test_nxv8i16374 ; RV64I: liveins: $v8m2, $v10m2375 ; RV64I-NEXT: {{ $}}376 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2377 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2378 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF379 ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */380 ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]381 ; RV64I-NEXT: PseudoRET implicit $v8m2382 %0:vrb(<vscale x 8 x s16>) = COPY $v8m2383 %1:vrb(<vscale x 8 x s16>) = COPY $v10m2384 %2:vrb(<vscale x 8 x s16>) = G_SUB %0, %1385 $v8m2 = COPY %2(<vscale x 8 x s16>)386 PseudoRET implicit $v8m2387 388...389---390name: test_nxv16i16391legalized: true392regBankSelected: true393tracksRegLiveness: true394body: |395 bb.0.entry:396 liveins: $v8m4, $v12m4397 398 ; RV32I-LABEL: name: test_nxv16i16399 ; RV32I: liveins: $v8m4, $v12m4400 ; RV32I-NEXT: {{ $}}401 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4402 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4403 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF404 ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */405 ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]406 ; RV32I-NEXT: PseudoRET implicit $v8m4407 ;408 ; RV64I-LABEL: name: test_nxv16i16409 ; RV64I: liveins: $v8m4, $v12m4410 ; RV64I-NEXT: {{ $}}411 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4412 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4413 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF414 ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */415 ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]416 ; RV64I-NEXT: PseudoRET implicit $v8m4417 %0:vrb(<vscale x 16 x s16>) = COPY $v8m4418 %1:vrb(<vscale x 16 x s16>) = COPY $v12m4419 %2:vrb(<vscale x 16 x s16>) = G_SUB %0, %1420 $v8m4 = COPY %2(<vscale x 16 x s16>)421 PseudoRET implicit $v8m4422 423...424---425name: test_nxv32i16426legalized: true427regBankSelected: true428tracksRegLiveness: true429body: |430 bb.0.entry:431 liveins: $v8m8, $v16m8432 433 ; RV32I-LABEL: name: test_nxv32i16434 ; RV32I: liveins: $v8m8, $v16m8435 ; RV32I-NEXT: {{ $}}436 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8437 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8438 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF439 ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */440 ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]441 ; RV32I-NEXT: PseudoRET implicit $v8m8442 ;443 ; RV64I-LABEL: name: test_nxv32i16444 ; RV64I: liveins: $v8m8, $v16m8445 ; RV64I-NEXT: {{ $}}446 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8447 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8448 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF449 ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 4 /* e16 */, 3 /* ta, ma */450 ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]451 ; RV64I-NEXT: PseudoRET implicit $v8m8452 %0:vrb(<vscale x 32 x s16>) = COPY $v8m8453 %1:vrb(<vscale x 32 x s16>) = COPY $v16m8454 %2:vrb(<vscale x 32 x s16>) = G_SUB %0, %1455 $v8m8 = COPY %2(<vscale x 32 x s16>)456 PseudoRET implicit $v8m8457 458...459---460name: test_nxv1i32461legalized: true462regBankSelected: true463tracksRegLiveness: true464body: |465 bb.0.entry:466 liveins: $v8, $v9467 468 ; RV32I-LABEL: name: test_nxv1i32469 ; RV32I: liveins: $v8, $v9470 ; RV32I-NEXT: {{ $}}471 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8472 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9473 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF474 ; RV32I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */475 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]]476 ; RV32I-NEXT: PseudoRET implicit $v8477 ;478 ; RV64I-LABEL: name: test_nxv1i32479 ; RV64I: liveins: $v8, $v9480 ; RV64I-NEXT: {{ $}}481 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8482 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9483 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF484 ; RV64I-NEXT: [[PseudoVSUB_VV_MF2_:%[0-9]+]]:vr = PseudoVSUB_VV_MF2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */485 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_MF2_]]486 ; RV64I-NEXT: PseudoRET implicit $v8487 %0:vrb(<vscale x 1 x s32>) = COPY $v8488 %1:vrb(<vscale x 1 x s32>) = COPY $v9489 %2:vrb(<vscale x 1 x s32>) = G_SUB %0, %1490 $v8 = COPY %2(<vscale x 1 x s32>)491 PseudoRET implicit $v8492 493...494---495name: test_nxv2i32496legalized: true497regBankSelected: true498tracksRegLiveness: true499body: |500 bb.0.entry:501 liveins: $v8, $v9502 503 ; RV32I-LABEL: name: test_nxv2i32504 ; RV32I: liveins: $v8, $v9505 ; RV32I-NEXT: {{ $}}506 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8507 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9508 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF509 ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */510 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]511 ; RV32I-NEXT: PseudoRET implicit $v8512 ;513 ; RV64I-LABEL: name: test_nxv2i32514 ; RV64I: liveins: $v8, $v9515 ; RV64I-NEXT: {{ $}}516 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8517 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9518 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF519 ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */520 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]521 ; RV64I-NEXT: PseudoRET implicit $v8522 %0:vrb(<vscale x 2 x s32>) = COPY $v8523 %1:vrb(<vscale x 2 x s32>) = COPY $v9524 %2:vrb(<vscale x 2 x s32>) = G_SUB %0, %1525 $v8 = COPY %2(<vscale x 2 x s32>)526 PseudoRET implicit $v8527 528...529---530name: test_nxv4i32531legalized: true532regBankSelected: true533tracksRegLiveness: true534body: |535 bb.0.entry:536 liveins: $v8m2, $v10m2537 538 ; RV32I-LABEL: name: test_nxv4i32539 ; RV32I: liveins: $v8m2, $v10m2540 ; RV32I-NEXT: {{ $}}541 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2542 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2543 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF544 ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */545 ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]546 ; RV32I-NEXT: PseudoRET implicit $v8m2547 ;548 ; RV64I-LABEL: name: test_nxv4i32549 ; RV64I: liveins: $v8m2, $v10m2550 ; RV64I-NEXT: {{ $}}551 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2552 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2553 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF554 ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */555 ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]556 ; RV64I-NEXT: PseudoRET implicit $v8m2557 %0:vrb(<vscale x 4 x s32>) = COPY $v8m2558 %1:vrb(<vscale x 4 x s32>) = COPY $v10m2559 %2:vrb(<vscale x 4 x s32>) = G_SUB %0, %1560 $v8m2 = COPY %2(<vscale x 4 x s32>)561 PseudoRET implicit $v8m2562 563...564---565name: test_nxv8i32566legalized: true567regBankSelected: true568tracksRegLiveness: true569body: |570 bb.0.entry:571 liveins: $v8m4, $v12m4572 573 ; RV32I-LABEL: name: test_nxv8i32574 ; RV32I: liveins: $v8m4, $v12m4575 ; RV32I-NEXT: {{ $}}576 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4577 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4578 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF579 ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */580 ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]581 ; RV32I-NEXT: PseudoRET implicit $v8m4582 ;583 ; RV64I-LABEL: name: test_nxv8i32584 ; RV64I: liveins: $v8m4, $v12m4585 ; RV64I-NEXT: {{ $}}586 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4587 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4588 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF589 ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */590 ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]591 ; RV64I-NEXT: PseudoRET implicit $v8m4592 %0:vrb(<vscale x 8 x s32>) = COPY $v8m4593 %1:vrb(<vscale x 8 x s32>) = COPY $v12m4594 %2:vrb(<vscale x 8 x s32>) = G_SUB %0, %1595 $v8m4 = COPY %2(<vscale x 8 x s32>)596 PseudoRET implicit $v8m4597 598...599---600name: test_nxv16i32601legalized: true602regBankSelected: true603tracksRegLiveness: true604body: |605 bb.0.entry:606 liveins: $v8m8, $v16m8607 608 ; RV32I-LABEL: name: test_nxv16i32609 ; RV32I: liveins: $v8m8, $v16m8610 ; RV32I-NEXT: {{ $}}611 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8612 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8613 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF614 ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */615 ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]616 ; RV32I-NEXT: PseudoRET implicit $v8m8617 ;618 ; RV64I-LABEL: name: test_nxv16i32619 ; RV64I: liveins: $v8m8, $v16m8620 ; RV64I-NEXT: {{ $}}621 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8622 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8623 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF624 ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 5 /* e32 */, 3 /* ta, ma */625 ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]626 ; RV64I-NEXT: PseudoRET implicit $v8m8627 %0:vrb(<vscale x 16 x s32>) = COPY $v8m8628 %1:vrb(<vscale x 16 x s32>) = COPY $v16m8629 %2:vrb(<vscale x 16 x s32>) = G_SUB %0, %1630 $v8m8 = COPY %2(<vscale x 16 x s32>)631 PseudoRET implicit $v8m8632 633...634---635name: test_nxv1i64636legalized: true637regBankSelected: true638tracksRegLiveness: true639body: |640 bb.0.entry:641 liveins: $v8, $v9642 643 ; RV32I-LABEL: name: test_nxv1i64644 ; RV32I: liveins: $v8, $v9645 ; RV32I-NEXT: {{ $}}646 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8647 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9648 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF649 ; RV32I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */650 ; RV32I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]651 ; RV32I-NEXT: PseudoRET implicit $v8652 ;653 ; RV64I-LABEL: name: test_nxv1i64654 ; RV64I: liveins: $v8, $v9655 ; RV64I-NEXT: {{ $}}656 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8657 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9658 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF659 ; RV64I-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */660 ; RV64I-NEXT: $v8 = COPY [[PseudoVSUB_VV_M1_]]661 ; RV64I-NEXT: PseudoRET implicit $v8662 %0:vrb(<vscale x 1 x s64>) = COPY $v8663 %1:vrb(<vscale x 1 x s64>) = COPY $v9664 %2:vrb(<vscale x 1 x s64>) = G_SUB %0, %1665 $v8 = COPY %2(<vscale x 1 x s64>)666 PseudoRET implicit $v8667 668...669---670name: test_nxv2i64671legalized: true672regBankSelected: true673tracksRegLiveness: true674body: |675 bb.0.entry:676 liveins: $v8m2, $v10m2677 678 ; RV32I-LABEL: name: test_nxv2i64679 ; RV32I: liveins: $v8m2, $v10m2680 ; RV32I-NEXT: {{ $}}681 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2682 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2683 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF684 ; RV32I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */685 ; RV32I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]686 ; RV32I-NEXT: PseudoRET implicit $v8m2687 ;688 ; RV64I-LABEL: name: test_nxv2i64689 ; RV64I: liveins: $v8m2, $v10m2690 ; RV64I-NEXT: {{ $}}691 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2692 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm2 = COPY $v10m2693 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF694 ; RV64I-NEXT: [[PseudoVSUB_VV_M2_:%[0-9]+]]:vrm2 = PseudoVSUB_VV_M2 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */695 ; RV64I-NEXT: $v8m2 = COPY [[PseudoVSUB_VV_M2_]]696 ; RV64I-NEXT: PseudoRET implicit $v8m2697 %0:vrb(<vscale x 2 x s64>) = COPY $v8m2698 %1:vrb(<vscale x 2 x s64>) = COPY $v10m2699 %2:vrb(<vscale x 2 x s64>) = G_SUB %0, %1700 $v8m2 = COPY %2(<vscale x 2 x s64>)701 PseudoRET implicit $v8m2702 703...704---705name: test_nxv4i64706legalized: true707regBankSelected: true708tracksRegLiveness: true709body: |710 bb.0.entry:711 liveins: $v8m4, $v12m4712 713 ; RV32I-LABEL: name: test_nxv4i64714 ; RV32I: liveins: $v8m4, $v12m4715 ; RV32I-NEXT: {{ $}}716 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4717 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4718 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF719 ; RV32I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */720 ; RV32I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]721 ; RV32I-NEXT: PseudoRET implicit $v8m4722 ;723 ; RV64I-LABEL: name: test_nxv4i64724 ; RV64I: liveins: $v8m4, $v12m4725 ; RV64I-NEXT: {{ $}}726 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4727 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm4 = COPY $v12m4728 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF729 ; RV64I-NEXT: [[PseudoVSUB_VV_M4_:%[0-9]+]]:vrm4 = PseudoVSUB_VV_M4 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */730 ; RV64I-NEXT: $v8m4 = COPY [[PseudoVSUB_VV_M4_]]731 ; RV64I-NEXT: PseudoRET implicit $v8m4732 %0:vrb(<vscale x 4 x s64>) = COPY $v8m4733 %1:vrb(<vscale x 4 x s64>) = COPY $v12m4734 %2:vrb(<vscale x 4 x s64>) = G_SUB %0, %1735 $v8m4 = COPY %2(<vscale x 4 x s64>)736 PseudoRET implicit $v8m4737 738...739---740name: test_nxv8i64741legalized: true742regBankSelected: true743tracksRegLiveness: true744body: |745 bb.0.entry:746 liveins: $v8m8, $v16m8747 748 ; RV32I-LABEL: name: test_nxv8i64749 ; RV32I: liveins: $v8m8, $v16m8750 ; RV32I-NEXT: {{ $}}751 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8752 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8753 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF754 ; RV32I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */755 ; RV32I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]756 ; RV32I-NEXT: PseudoRET implicit $v8m8757 ;758 ; RV64I-LABEL: name: test_nxv8i64759 ; RV64I: liveins: $v8m8, $v16m8760 ; RV64I-NEXT: {{ $}}761 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8762 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:vrm8 = COPY $v16m8763 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF764 ; RV64I-NEXT: [[PseudoVSUB_VV_M8_:%[0-9]+]]:vrm8 = PseudoVSUB_VV_M8 [[DEF]], [[COPY]], [[COPY1]], -1, 6 /* e64 */, 3 /* ta, ma */765 ; RV64I-NEXT: $v8m8 = COPY [[PseudoVSUB_VV_M8_]]766 ; RV64I-NEXT: PseudoRET implicit $v8m8767 %0:vrb(<vscale x 8 x s64>) = COPY $v8m8768 %1:vrb(<vscale x 8 x s64>) = COPY $v16m8769 %2:vrb(<vscale x 8 x s64>) = G_SUB %0, %1770 $v8m8 = COPY %2(<vscale x 8 x s64>)771 PseudoRET implicit $v8m8772 773...774 775