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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: splat_zero_nxv1i17legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.1:12 ; CHECK-LABEL: name: splat_zero_nxv1i113 ; CHECK: [[PseudoVMCLR_M_B64_:%[0-9]+]]:vr = PseudoVMCLR_M_B64 -1, 0 /* e8 */14 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B64_]]15 ; CHECK-NEXT: PseudoRET implicit $v016 %0:gprb(s64) = G_CONSTANT i64 -117 %1:vrb(<vscale x 1 x s1>) = G_VMCLR_VL %0(s64)18 $v0 = COPY %1(<vscale x 1 x s1>)19 PseudoRET implicit $v020 21...22---23name: splat_zero_nxv2i124legalized: true25regBankSelected: true26tracksRegLiveness: true27body: |28 bb.1:29 ; CHECK-LABEL: name: splat_zero_nxv2i130 ; CHECK: [[PseudoVMCLR_M_B32_:%[0-9]+]]:vr = PseudoVMCLR_M_B32 -1, 0 /* e8 */31 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B32_]]32 ; CHECK-NEXT: PseudoRET implicit $v033 %0:gprb(s64) = G_CONSTANT i64 -134 %1:vrb(<vscale x 2 x s1>) = G_VMCLR_VL %0(s64)35 $v0 = COPY %1(<vscale x 2 x s1>)36 PseudoRET implicit $v037 38...39---40name: splat_zero_nxv4i141legalized: true42regBankSelected: true43tracksRegLiveness: true44body: |45 bb.1:46 ; CHECK-LABEL: name: splat_zero_nxv4i147 ; CHECK: [[PseudoVMCLR_M_B16_:%[0-9]+]]:vr = PseudoVMCLR_M_B16 -1, 0 /* e8 */48 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B16_]]49 ; CHECK-NEXT: PseudoRET implicit $v050 %0:gprb(s64) = G_CONSTANT i64 -151 %1:vrb(<vscale x 4 x s1>) = G_VMCLR_VL %0(s64)52 $v0 = COPY %1(<vscale x 4 x s1>)53 PseudoRET implicit $v054 55...56---57name: splat_zero_nxv8i158legalized: true59regBankSelected: true60tracksRegLiveness: true61body: |62 bb.1:63 ; CHECK-LABEL: name: splat_zero_nxv8i164 ; CHECK: [[PseudoVMCLR_M_B8_:%[0-9]+]]:vr = PseudoVMCLR_M_B8 -1, 0 /* e8 */65 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B8_]]66 ; CHECK-NEXT: PseudoRET implicit $v067 %0:gprb(s64) = G_CONSTANT i64 -168 %1:vrb(<vscale x 8 x s1>) = G_VMCLR_VL %0(s64)69 $v0 = COPY %1(<vscale x 8 x s1>)70 PseudoRET implicit $v071 72...73---74name: splat_zero_nxv16i175legalized: true76regBankSelected: true77tracksRegLiveness: true78body: |79 bb.1:80 ; CHECK-LABEL: name: splat_zero_nxv16i181 ; CHECK: [[PseudoVMCLR_M_B4_:%[0-9]+]]:vr = PseudoVMCLR_M_B4 -1, 0 /* e8 */82 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B4_]]83 ; CHECK-NEXT: PseudoRET implicit $v084 %0:gprb(s64) = G_CONSTANT i64 -185 %1:vrb(<vscale x 16 x s1>) = G_VMCLR_VL %0(s64)86 $v0 = COPY %1(<vscale x 16 x s1>)87 PseudoRET implicit $v088 89...90---91name: splat_zero_nxv32i192legalized: true93regBankSelected: true94tracksRegLiveness: true95body: |96 bb.1:97 ; CHECK-LABEL: name: splat_zero_nxv32i198 ; CHECK: [[PseudoVMCLR_M_B2_:%[0-9]+]]:vr = PseudoVMCLR_M_B2 -1, 0 /* e8 */99 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B2_]]100 ; CHECK-NEXT: PseudoRET implicit $v0101 %0:gprb(s64) = G_CONSTANT i64 -1102 %1:vrb(<vscale x 32 x s1>) = G_VMCLR_VL %0(s64)103 $v0 = COPY %1(<vscale x 32 x s1>)104 PseudoRET implicit $v0105 106...107---108name: splat_zero_nxv64i1109legalized: true110regBankSelected: true111tracksRegLiveness: true112body: |113 bb.1:114 ; CHECK-LABEL: name: splat_zero_nxv64i1115 ; CHECK: [[PseudoVMCLR_M_B1_:%[0-9]+]]:vr = PseudoVMCLR_M_B1 -1, 0 /* e8 */116 ; CHECK-NEXT: $v0 = COPY [[PseudoVMCLR_M_B1_]]117 ; CHECK-NEXT: PseudoRET implicit $v0118 %0:gprb(s64) = G_CONSTANT i64 -1119 %1:vrb(<vscale x 64 x s1>) = G_VMCLR_VL %0(s64)120 $v0 = COPY %1(<vscale x 64 x s1>)121 PseudoRET implicit $v0122 123...124 125