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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v,+m -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: test_1_s327legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 ; CHECK-LABEL: name: test_1_s3213 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB14 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 315 ; CHECK-NEXT: $x10 = COPY [[SRLI]]16 ; CHECK-NEXT: PseudoRET implicit $x1017 %1:gprb(s32) = G_READ_VLENB18 %2:gprb(s32) = G_CONSTANT i32 319 %0:gprb(s32) = G_LSHR %1, %2(s32)20 $x10 = COPY %0(s32)21 PseudoRET implicit $x1022 23...24---25name: test_2_s3226legalized: true27regBankSelected: true28tracksRegLiveness: true29body: |30 bb.0.entry:31 ; CHECK-LABEL: name: test_2_s3232 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB33 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 234 ; CHECK-NEXT: $x10 = COPY [[SRLI]]35 ; CHECK-NEXT: PseudoRET implicit $x1036 %1:gprb(s32) = G_READ_VLENB37 %2:gprb(s32) = G_CONSTANT i32 238 %0:gprb(s32) = G_LSHR %1, %2(s32)39 $x10 = COPY %0(s32)40 PseudoRET implicit $x1041 42...43---44name: test_3_s3245legalized: true46regBankSelected: true47tracksRegLiveness: true48body: |49 bb.0.entry:50 ; CHECK-LABEL: name: test_3_s3251 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB52 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 353 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 354 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]55 ; CHECK-NEXT: $x10 = COPY [[MUL]]56 ; CHECK-NEXT: PseudoRET implicit $x1057 %1:gprb(s32) = G_READ_VLENB58 %2:gprb(s32) = G_CONSTANT i32 359 %3:gprb(s32) = G_LSHR %1, %2(s32)60 %4:gprb(s32) = G_CONSTANT i32 361 %0:gprb(s32) = G_MUL %3, %462 $x10 = COPY %0(s32)63 PseudoRET implicit $x1064 65...66---67name: test_4_s3268legalized: true69regBankSelected: true70tracksRegLiveness: true71body: |72 bb.0.entry:73 ; CHECK-LABEL: name: test_4_s3274 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB75 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 176 ; CHECK-NEXT: $x10 = COPY [[SRLI]]77 ; CHECK-NEXT: PseudoRET implicit $x1078 %1:gprb(s32) = G_READ_VLENB79 %2:gprb(s32) = G_CONSTANT i32 180 %0:gprb(s32) = G_LSHR %1, %2(s32)81 $x10 = COPY %0(s32)82 PseudoRET implicit $x1083 84...85---86name: test_8_s3287legalized: true88regBankSelected: true89tracksRegLiveness: true90body: |91 bb.0.entry:92 ; CHECK-LABEL: name: test_8_s3293 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB94 ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]95 ; CHECK-NEXT: PseudoRET implicit $x1096 %0:gprb(s32) = G_READ_VLENB97 $x10 = COPY %0(s32)98 PseudoRET implicit $x1099 100...101---102name: test_16_s32103legalized: true104regBankSelected: true105tracksRegLiveness: true106body: |107 bb.0.entry:108 ; CHECK-LABEL: name: test_16_s32109 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB110 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1111 ; CHECK-NEXT: $x10 = COPY [[SLLI]]112 ; CHECK-NEXT: PseudoRET implicit $x10113 %1:gprb(s32) = G_READ_VLENB114 %2:gprb(s32) = G_CONSTANT i32 1115 %0:gprb(s32) = G_SHL %1, %2(s32)116 $x10 = COPY %0(s32)117 PseudoRET implicit $x10118 119...120---121name: test_40_s32122legalized: true123regBankSelected: true124tracksRegLiveness: true125body: |126 bb.0.entry:127 ; CHECK-LABEL: name: test_40_s32128 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB129 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5130 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]]131 ; CHECK-NEXT: $x10 = COPY [[MUL]]132 ; CHECK-NEXT: PseudoRET implicit $x10133 %1:gprb(s32) = G_READ_VLENB134 %2:gprb(s32) = G_CONSTANT i32 5135 %0:gprb(s32) = G_MUL %1, %2136 $x10 = COPY %0(s32)137 PseudoRET implicit $x10138 139...140---141name: test_1_s64142legalized: true143regBankSelected: true144tracksRegLiveness: true145body: |146 bb.0.entry:147 ; CHECK-LABEL: name: test_1_s64148 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB149 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3150 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1151 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]152 ; CHECK-NEXT: $x10 = COPY [[MUL]]153 ; CHECK-NEXT: PseudoRET implicit $x10154 %17:gprb(s32) = G_READ_VLENB155 %18:gprb(s32) = G_CONSTANT i32 3156 %2:gprb(s32) = G_LSHR %17, %18(s32)157 %15:gprb(s32) = G_CONSTANT i32 1158 %9:gprb(s32) = G_MUL %2, %15159 $x10 = COPY %9(s32)160 PseudoRET implicit $x10161 162...163---164name: test_2_s64165legalized: true166regBankSelected: true167tracksRegLiveness: true168body: |169 bb.0.entry:170 ; CHECK-LABEL: name: test_2_s64171 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB172 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3173 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 2174 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]175 ; CHECK-NEXT: $x10 = COPY [[MUL]]176 ; CHECK-NEXT: PseudoRET implicit $x10177 %17:gprb(s32) = G_READ_VLENB178 %18:gprb(s32) = G_CONSTANT i32 3179 %2:gprb(s32) = G_LSHR %17, %18(s32)180 %15:gprb(s32) = G_CONSTANT i32 2181 %9:gprb(s32) = G_MUL %2, %15182 $x10 = COPY %9(s32)183 PseudoRET implicit $x10184 185...186---187name: test_3_s64188legalized: true189regBankSelected: true190tracksRegLiveness: true191body: |192 bb.0.entry:193 ; CHECK-LABEL: name: test_3_s64194 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB195 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3196 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 3197 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]198 ; CHECK-NEXT: $x10 = COPY [[MUL]]199 ; CHECK-NEXT: PseudoRET implicit $x10200 %17:gprb(s32) = G_READ_VLENB201 %18:gprb(s32) = G_CONSTANT i32 3202 %2:gprb(s32) = G_LSHR %17, %18(s32)203 %15:gprb(s32) = G_CONSTANT i32 3204 %9:gprb(s32) = G_MUL %2, %15205 $x10 = COPY %9(s32)206 PseudoRET implicit $x10207 208...209---210name: test_4_s64211legalized: true212regBankSelected: true213tracksRegLiveness: true214body: |215 bb.0.entry:216 ; CHECK-LABEL: name: test_4_s64217 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB218 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3219 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 4220 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]221 ; CHECK-NEXT: $x10 = COPY [[MUL]]222 ; CHECK-NEXT: PseudoRET implicit $x10223 %17:gprb(s32) = G_READ_VLENB224 %18:gprb(s32) = G_CONSTANT i32 3225 %2:gprb(s32) = G_LSHR %17, %18(s32)226 %15:gprb(s32) = G_CONSTANT i32 4227 %9:gprb(s32) = G_MUL %2, %15228 $x10 = COPY %9(s32)229 PseudoRET implicit $x10230 231...232---233name: test_8_s64234legalized: true235regBankSelected: true236tracksRegLiveness: true237body: |238 bb.0.entry:239 ; CHECK-LABEL: name: test_8_s64240 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB241 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3242 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8243 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]244 ; CHECK-NEXT: $x10 = COPY [[MUL]]245 ; CHECK-NEXT: PseudoRET implicit $x10246 %17:gprb(s32) = G_READ_VLENB247 %18:gprb(s32) = G_CONSTANT i32 3248 %2:gprb(s32) = G_LSHR %17, %18(s32)249 %15:gprb(s32) = G_CONSTANT i32 8250 %9:gprb(s32) = G_MUL %2, %15251 $x10 = COPY %9(s32)252 PseudoRET implicit $x10253 254...255---256name: test_16_s64257legalized: true258regBankSelected: true259tracksRegLiveness: true260body: |261 bb.0.entry:262 ; CHECK-LABEL: name: test_16_s64263 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB264 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3265 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 16266 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]267 ; CHECK-NEXT: $x10 = COPY [[MUL]]268 ; CHECK-NEXT: PseudoRET implicit $x10269 %17:gprb(s32) = G_READ_VLENB270 %18:gprb(s32) = G_CONSTANT i32 3271 %2:gprb(s32) = G_LSHR %17, %18(s32)272 %15:gprb(s32) = G_CONSTANT i32 16273 %9:gprb(s32) = G_MUL %2, %15274 $x10 = COPY %9(s32)275 PseudoRET implicit $x10276 277...278---279name: test_40_s64280legalized: true281regBankSelected: true282tracksRegLiveness: true283body: |284 bb.0.entry:285 ; CHECK-LABEL: name: test_40_s64286 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB287 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3288 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 40289 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]290 ; CHECK-NEXT: $x10 = COPY [[MUL]]291 ; CHECK-NEXT: PseudoRET implicit $x10292 %17:gprb(s32) = G_READ_VLENB293 %18:gprb(s32) = G_CONSTANT i32 3294 %2:gprb(s32) = G_LSHR %17, %18(s32)295 %15:gprb(s32) = G_CONSTANT i32 40296 %9:gprb(s32) = G_MUL %2, %15297 $x10 = COPY %9(s32)298 PseudoRET implicit $x10299 300...301