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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv64 -mattr=+v,+m -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: test_17legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 ; CHECK-LABEL: name: test_113 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB14 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 315 ; CHECK-NEXT: $x10 = COPY [[SRLI]]16 ; CHECK-NEXT: PseudoRET implicit $x1017 %0:gprb(s64) = G_READ_VLENB18 %1:gprb(s64) = G_CONSTANT i64 319 %2:gprb(s64) = G_LSHR %0, %1(s64)20 $x10 = COPY %2(s64)21 PseudoRET implicit $x1022 23...24---25name: test_226legalized: true27regBankSelected: true28tracksRegLiveness: true29body: |30 bb.0.entry:31 ; CHECK-LABEL: name: test_232 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB33 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 234 ; CHECK-NEXT: $x10 = COPY [[SRLI]]35 ; CHECK-NEXT: PseudoRET implicit $x1036 %0:gprb(s64) = G_READ_VLENB37 %1:gprb(s64) = G_CONSTANT i64 238 %2:gprb(s64) = G_LSHR %0, %1(s64)39 $x10 = COPY %2(s64)40 PseudoRET implicit $x1041 42...43---44name: test_345legalized: true46regBankSelected: true47tracksRegLiveness: true48body: |49 bb.0.entry:50 ; CHECK-LABEL: name: test_351 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB52 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 353 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 354 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[SRLI]], [[ADDI]]55 ; CHECK-NEXT: $x10 = COPY [[MUL]]56 ; CHECK-NEXT: PseudoRET implicit $x1057 %0:gprb(s64) = G_READ_VLENB58 %1:gprb(s64) = G_CONSTANT i64 359 %2:gprb(s64) = G_LSHR %0, %1(s64)60 %3:gprb(s64) = G_CONSTANT i64 361 %4:gprb(s64) = G_MUL %2, %362 $x10 = COPY %4(s64)63 PseudoRET implicit $x1064 65...66---67name: test_468legalized: true69regBankSelected: true70tracksRegLiveness: true71body: |72 bb.0.entry:73 ; CHECK-LABEL: name: test_474 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB75 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 176 ; CHECK-NEXT: $x10 = COPY [[SRLI]]77 ; CHECK-NEXT: PseudoRET implicit $x1078 %0:gprb(s64) = G_READ_VLENB79 %1:gprb(s64) = G_CONSTANT i64 180 %2:gprb(s64) = G_LSHR %0, %1(s64)81 $x10 = COPY %2(s64)82 PseudoRET implicit $x1083 84...85---86name: test_887legalized: true88regBankSelected: true89tracksRegLiveness: true90body: |91 bb.0.entry:92 ; CHECK-LABEL: name: test_893 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB94 ; CHECK-NEXT: $x10 = COPY [[PseudoReadVLENB]]95 ; CHECK-NEXT: PseudoRET implicit $x1096 %0:gprb(s64) = G_READ_VLENB97 $x10 = COPY %0(s64)98 PseudoRET implicit $x1099 100...101---102name: test_16103legalized: true104regBankSelected: true105tracksRegLiveness: true106body: |107 bb.0.entry:108 ; CHECK-LABEL: name: test_16109 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB110 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[PseudoReadVLENB]], 1111 ; CHECK-NEXT: $x10 = COPY [[SLLI]]112 ; CHECK-NEXT: PseudoRET implicit $x10113 %0:gprb(s64) = G_READ_VLENB114 %1:gprb(s64) = G_CONSTANT i64 1115 %2:gprb(s64) = G_SHL %0, %1(s64)116 $x10 = COPY %2(s64)117 PseudoRET implicit $x10118 119...120---121name: test_40122legalized: true123regBankSelected: true124tracksRegLiveness: true125body: |126 bb.0.entry:127 ; CHECK-LABEL: name: test_40128 ; CHECK: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB129 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 5130 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PseudoReadVLENB]], [[ADDI]]131 ; CHECK-NEXT: $x10 = COPY [[MUL]]132 ; CHECK-NEXT: PseudoRET implicit $x10133 %0:gprb(s64) = G_READ_VLENB134 %1:gprb(s64) = G_CONSTANT i64 5135 %2:gprb(s64) = G_MUL %0, %1136 $x10 = COPY %2(s64)137 PseudoRET implicit $x10138 139...140