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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV32I %s3# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - | FileCheck -check-prefix=RV64I %s4 5---6name: zext_nxv1i16_nxv1i87legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 liveins: $v813 14 ; RV32I-LABEL: name: zext_nxv1i16_nxv1i815 ; RV32I: liveins: $v816 ; RV32I-NEXT: {{ $}}17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v818 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF19 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */20 ; RV32I-NEXT: $v8 = COPY %121 ; RV32I-NEXT: PseudoRET implicit $v822 ;23 ; RV64I-LABEL: name: zext_nxv1i16_nxv1i824 ; RV64I: liveins: $v825 ; RV64I-NEXT: {{ $}}26 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v827 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF28 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */29 ; RV64I-NEXT: $v8 = COPY %130 ; RV64I-NEXT: PseudoRET implicit $v831 %0:vrb(<vscale x 1 x s8>) = COPY $v832 %1:vrb(<vscale x 1 x s16>) = G_ZEXT %0(<vscale x 1 x s8>)33 $v8 = COPY %1(<vscale x 1 x s16>)34 PseudoRET implicit $v835 36...37---38name: zext_nxv1i32_nxv1i839legalized: true40regBankSelected: true41tracksRegLiveness: true42body: |43 bb.0.entry:44 liveins: $v845 46 ; RV32I-LABEL: name: zext_nxv1i32_nxv1i847 ; RV32I: liveins: $v848 ; RV32I-NEXT: {{ $}}49 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v850 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF51 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */52 ; RV32I-NEXT: $v8 = COPY %153 ; RV32I-NEXT: PseudoRET implicit $v854 ;55 ; RV64I-LABEL: name: zext_nxv1i32_nxv1i856 ; RV64I: liveins: $v857 ; RV64I-NEXT: {{ $}}58 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v859 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF60 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */61 ; RV64I-NEXT: $v8 = COPY %162 ; RV64I-NEXT: PseudoRET implicit $v863 %0:vrb(<vscale x 1 x s8>) = COPY $v864 %1:vrb(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s8>)65 $v8 = COPY %1(<vscale x 1 x s32>)66 PseudoRET implicit $v867 68...69---70name: zext_nxv1i64_nxv1i871legalized: true72regBankSelected: true73tracksRegLiveness: true74body: |75 bb.0.entry:76 liveins: $v877 78 ; RV32I-LABEL: name: zext_nxv1i64_nxv1i879 ; RV32I: liveins: $v880 ; RV32I-NEXT: {{ $}}81 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v882 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF83 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */84 ; RV32I-NEXT: $v8 = COPY %185 ; RV32I-NEXT: PseudoRET implicit $v886 ;87 ; RV64I-LABEL: name: zext_nxv1i64_nxv1i888 ; RV64I: liveins: $v889 ; RV64I-NEXT: {{ $}}90 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v891 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF92 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF8_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */93 ; RV64I-NEXT: $v8 = COPY %194 ; RV64I-NEXT: PseudoRET implicit $v895 %0:vrb(<vscale x 1 x s8>) = COPY $v896 %1:vrb(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s8>)97 $v8 = COPY %1(<vscale x 1 x s64>)98 PseudoRET implicit $v899 100...101---102name: zext_nxv2i16_nxv2i8103legalized: true104regBankSelected: true105tracksRegLiveness: true106body: |107 bb.0.entry:108 liveins: $v8109 110 ; RV32I-LABEL: name: zext_nxv2i16_nxv2i8111 ; RV32I: liveins: $v8112 ; RV32I-NEXT: {{ $}}113 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8114 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF115 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */116 ; RV32I-NEXT: $v8 = COPY %1117 ; RV32I-NEXT: PseudoRET implicit $v8118 ;119 ; RV64I-LABEL: name: zext_nxv2i16_nxv2i8120 ; RV64I: liveins: $v8121 ; RV64I-NEXT: {{ $}}122 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8123 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF124 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */125 ; RV64I-NEXT: $v8 = COPY %1126 ; RV64I-NEXT: PseudoRET implicit $v8127 %0:vrb(<vscale x 2 x s8>) = COPY $v8128 %1:vrb(<vscale x 2 x s16>) = G_ZEXT %0(<vscale x 2 x s8>)129 $v8 = COPY %1(<vscale x 2 x s16>)130 PseudoRET implicit $v8131 132...133---134name: zext_nxv2i32_nxv2i8135legalized: true136regBankSelected: true137tracksRegLiveness: true138body: |139 bb.0.entry:140 liveins: $v8141 142 ; RV32I-LABEL: name: zext_nxv2i32_nxv2i8143 ; RV32I: liveins: $v8144 ; RV32I-NEXT: {{ $}}145 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8146 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF147 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */148 ; RV32I-NEXT: $v8 = COPY %1149 ; RV32I-NEXT: PseudoRET implicit $v8150 ;151 ; RV64I-LABEL: name: zext_nxv2i32_nxv2i8152 ; RV64I: liveins: $v8153 ; RV64I-NEXT: {{ $}}154 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8155 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF156 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */157 ; RV64I-NEXT: $v8 = COPY %1158 ; RV64I-NEXT: PseudoRET implicit $v8159 %0:vrb(<vscale x 2 x s8>) = COPY $v8160 %1:vrb(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s8>)161 $v8 = COPY %1(<vscale x 2 x s32>)162 PseudoRET implicit $v8163 164...165---166name: zext_nxv2i64_nxv2i8167legalized: true168regBankSelected: true169tracksRegLiveness: true170body: |171 bb.0.entry:172 liveins: $v8173 174 ; RV32I-LABEL: name: zext_nxv2i64_nxv2i8175 ; RV32I: liveins: $v8176 ; RV32I-NEXT: {{ $}}177 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8178 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF179 ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */180 ; RV32I-NEXT: $v8m2 = COPY %1181 ; RV32I-NEXT: PseudoRET implicit $v8m2182 ;183 ; RV64I-LABEL: name: zext_nxv2i64_nxv2i8184 ; RV64I: liveins: $v8185 ; RV64I-NEXT: {{ $}}186 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8187 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF188 ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF8_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */189 ; RV64I-NEXT: $v8m2 = COPY %1190 ; RV64I-NEXT: PseudoRET implicit $v8m2191 %0:vrb(<vscale x 2 x s8>) = COPY $v8192 %1:vrb(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s8>)193 $v8m2 = COPY %1(<vscale x 2 x s64>)194 PseudoRET implicit $v8m2195 196...197---198name: zext_nxv4i16_nxv4i8199legalized: true200regBankSelected: true201tracksRegLiveness: true202body: |203 bb.0.entry:204 liveins: $v8205 206 ; RV32I-LABEL: name: zext_nxv4i16_nxv4i8207 ; RV32I: liveins: $v8208 ; RV32I-NEXT: {{ $}}209 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8210 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF211 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */212 ; RV32I-NEXT: $v8 = COPY %1213 ; RV32I-NEXT: PseudoRET implicit $v8214 ;215 ; RV64I-LABEL: name: zext_nxv4i16_nxv4i8216 ; RV64I: liveins: $v8217 ; RV64I-NEXT: {{ $}}218 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8219 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF220 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */221 ; RV64I-NEXT: $v8 = COPY %1222 ; RV64I-NEXT: PseudoRET implicit $v8223 %0:vrb(<vscale x 4 x s8>) = COPY $v8224 %1:vrb(<vscale x 4 x s16>) = G_ZEXT %0(<vscale x 4 x s8>)225 $v8 = COPY %1(<vscale x 4 x s16>)226 PseudoRET implicit $v8227 228...229---230name: zext_nxv4i32_nxv4i8231legalized: true232regBankSelected: true233tracksRegLiveness: true234body: |235 bb.0.entry:236 liveins: $v8237 238 ; RV32I-LABEL: name: zext_nxv4i32_nxv4i8239 ; RV32I: liveins: $v8240 ; RV32I-NEXT: {{ $}}241 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8242 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF243 ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */244 ; RV32I-NEXT: $v8m2 = COPY %1245 ; RV32I-NEXT: PseudoRET implicit $v8m2246 ;247 ; RV64I-LABEL: name: zext_nxv4i32_nxv4i8248 ; RV64I: liveins: $v8249 ; RV64I-NEXT: {{ $}}250 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8251 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF252 ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */253 ; RV64I-NEXT: $v8m2 = COPY %1254 ; RV64I-NEXT: PseudoRET implicit $v8m2255 %0:vrb(<vscale x 4 x s8>) = COPY $v8256 %1:vrb(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s8>)257 $v8m2 = COPY %1(<vscale x 4 x s32>)258 PseudoRET implicit $v8m2259 260...261---262name: zext_nxv4i64_nxv4i8263legalized: true264regBankSelected: true265tracksRegLiveness: true266body: |267 bb.0.entry:268 liveins: $v8269 270 ; RV32I-LABEL: name: zext_nxv4i64_nxv4i8271 ; RV32I: liveins: $v8272 ; RV32I-NEXT: {{ $}}273 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8274 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF275 ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */276 ; RV32I-NEXT: $v8m4 = COPY %1277 ; RV32I-NEXT: PseudoRET implicit $v8m4278 ;279 ; RV64I-LABEL: name: zext_nxv4i64_nxv4i8280 ; RV64I: liveins: $v8281 ; RV64I-NEXT: {{ $}}282 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8283 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF284 ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF8_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */285 ; RV64I-NEXT: $v8m4 = COPY %1286 ; RV64I-NEXT: PseudoRET implicit $v8m4287 %0:vrb(<vscale x 4 x s8>) = COPY $v8288 %1:vrb(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s8>)289 $v8m4 = COPY %1(<vscale x 4 x s64>)290 PseudoRET implicit $v8m4291 292...293---294name: zext_nxv8i16_nxv8i8295legalized: true296regBankSelected: true297tracksRegLiveness: true298body: |299 bb.0.entry:300 liveins: $v8301 302 ; RV32I-LABEL: name: zext_nxv8i16_nxv8i8303 ; RV32I: liveins: $v8304 ; RV32I-NEXT: {{ $}}305 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8306 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF307 ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */308 ; RV32I-NEXT: $v8m2 = COPY %1309 ; RV32I-NEXT: PseudoRET implicit $v8m2310 ;311 ; RV64I-LABEL: name: zext_nxv8i16_nxv8i8312 ; RV64I: liveins: $v8313 ; RV64I-NEXT: {{ $}}314 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8315 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF316 ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */317 ; RV64I-NEXT: $v8m2 = COPY %1318 ; RV64I-NEXT: PseudoRET implicit $v8m2319 %0:vrb(<vscale x 8 x s8>) = COPY $v8320 %1:vrb(<vscale x 8 x s16>) = G_ZEXT %0(<vscale x 8 x s8>)321 $v8m2 = COPY %1(<vscale x 8 x s16>)322 PseudoRET implicit $v8m2323 324...325---326name: zext_nxv8i32_nxv8i8327legalized: true328regBankSelected: true329tracksRegLiveness: true330body: |331 bb.0.entry:332 liveins: $v8333 334 ; RV32I-LABEL: name: zext_nxv8i32_nxv8i8335 ; RV32I: liveins: $v8336 ; RV32I-NEXT: {{ $}}337 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8338 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF339 ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */340 ; RV32I-NEXT: $v8m4 = COPY %1341 ; RV32I-NEXT: PseudoRET implicit $v8m4342 ;343 ; RV64I-LABEL: name: zext_nxv8i32_nxv8i8344 ; RV64I: liveins: $v8345 ; RV64I-NEXT: {{ $}}346 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8347 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF348 ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */349 ; RV64I-NEXT: $v8m4 = COPY %1350 ; RV64I-NEXT: PseudoRET implicit $v8m4351 %0:vrb(<vscale x 8 x s8>) = COPY $v8352 %1:vrb(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s8>)353 $v8m4 = COPY %1(<vscale x 8 x s32>)354 PseudoRET implicit $v8m4355 356...357---358name: zext_nxv8i64_nxv8i8359legalized: true360regBankSelected: true361tracksRegLiveness: true362body: |363 bb.0.entry:364 liveins: $v8365 366 ; RV32I-LABEL: name: zext_nxv8i64_nxv8i8367 ; RV32I: liveins: $v8368 ; RV32I-NEXT: {{ $}}369 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8370 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF371 ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */372 ; RV32I-NEXT: $v8m8 = COPY %1373 ; RV32I-NEXT: PseudoRET implicit $v8m8374 ;375 ; RV64I-LABEL: name: zext_nxv8i64_nxv8i8376 ; RV64I: liveins: $v8377 ; RV64I-NEXT: {{ $}}378 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8379 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF380 ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF8_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */381 ; RV64I-NEXT: $v8m8 = COPY %1382 ; RV64I-NEXT: PseudoRET implicit $v8m8383 %0:vrb(<vscale x 8 x s8>) = COPY $v8384 %1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s8>)385 $v8m8 = COPY %1(<vscale x 8 x s64>)386 PseudoRET implicit $v8m8387 388...389---390name: zext_nxv16i16_nxv16i8391legalized: true392regBankSelected: true393tracksRegLiveness: true394body: |395 bb.0.entry:396 liveins: $v8m2397 398 ; RV32I-LABEL: name: zext_nxv16i16_nxv16i8399 ; RV32I: liveins: $v8m2400 ; RV32I-NEXT: {{ $}}401 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2402 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF403 ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */404 ; RV32I-NEXT: $v8m4 = COPY %1405 ; RV32I-NEXT: PseudoRET implicit $v8m4406 ;407 ; RV64I-LABEL: name: zext_nxv16i16_nxv16i8408 ; RV64I: liveins: $v8m2409 ; RV64I-NEXT: {{ $}}410 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2411 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF412 ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */413 ; RV64I-NEXT: $v8m4 = COPY %1414 ; RV64I-NEXT: PseudoRET implicit $v8m4415 %0:vrb(<vscale x 16 x s8>) = COPY $v8m2416 %1:vrb(<vscale x 16 x s16>) = G_ZEXT %0(<vscale x 16 x s8>)417 $v8m4 = COPY %1(<vscale x 16 x s16>)418 PseudoRET implicit $v8m4419 420...421---422name: zext_nxv16i32_nxv16i8423legalized: true424regBankSelected: true425tracksRegLiveness: true426body: |427 bb.0.entry:428 liveins: $v8m2429 430 ; RV32I-LABEL: name: zext_nxv16i32_nxv16i8431 ; RV32I: liveins: $v8m2432 ; RV32I-NEXT: {{ $}}433 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2434 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF435 ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */436 ; RV32I-NEXT: $v8m8 = COPY %1437 ; RV32I-NEXT: PseudoRET implicit $v8m8438 ;439 ; RV64I-LABEL: name: zext_nxv16i32_nxv16i8440 ; RV64I: liveins: $v8m2441 ; RV64I-NEXT: {{ $}}442 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2443 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF444 ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */445 ; RV64I-NEXT: $v8m8 = COPY %1446 ; RV64I-NEXT: PseudoRET implicit $v8m8447 %0:vrb(<vscale x 16 x s8>) = COPY $v8m2448 %1:vrb(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s8>)449 $v8m8 = COPY %1(<vscale x 16 x s32>)450 PseudoRET implicit $v8m8451 452...453---454name: zext_nxv32i16_nxv32i8455legalized: true456regBankSelected: true457tracksRegLiveness: true458body: |459 bb.0.entry:460 liveins: $v8m4461 462 ; RV32I-LABEL: name: zext_nxv32i16_nxv32i8463 ; RV32I: liveins: $v8m4464 ; RV32I-NEXT: {{ $}}465 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4466 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF467 ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */468 ; RV32I-NEXT: $v8m8 = COPY %1469 ; RV32I-NEXT: PseudoRET implicit $v8m8470 ;471 ; RV64I-LABEL: name: zext_nxv32i16_nxv32i8472 ; RV64I: liveins: $v8m4473 ; RV64I-NEXT: {{ $}}474 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4475 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF476 ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 4 /* e16 */, 3 /* ta, ma */477 ; RV64I-NEXT: $v8m8 = COPY %1478 ; RV64I-NEXT: PseudoRET implicit $v8m8479 %0:vrb(<vscale x 32 x s8>) = COPY $v8m4480 %1:vrb(<vscale x 32 x s16>) = G_ZEXT %0(<vscale x 32 x s8>)481 $v8m8 = COPY %1(<vscale x 32 x s16>)482 PseudoRET implicit $v8m8483 484...485---486name: zext_nxv1i32_nxv1i16487legalized: true488regBankSelected: true489tracksRegLiveness: true490body: |491 bb.0.entry:492 liveins: $v8493 494 ; RV32I-LABEL: name: zext_nxv1i32_nxv1i16495 ; RV32I: liveins: $v8496 ; RV32I-NEXT: {{ $}}497 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8498 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF499 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */500 ; RV32I-NEXT: $v8 = COPY %1501 ; RV32I-NEXT: PseudoRET implicit $v8502 ;503 ; RV64I-LABEL: name: zext_nxv1i32_nxv1i16504 ; RV64I: liveins: $v8505 ; RV64I-NEXT: {{ $}}506 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8507 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF508 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_MF2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */509 ; RV64I-NEXT: $v8 = COPY %1510 ; RV64I-NEXT: PseudoRET implicit $v8511 %0:vrb(<vscale x 1 x s16>) = COPY $v8512 %1:vrb(<vscale x 1 x s32>) = G_ZEXT %0(<vscale x 1 x s16>)513 $v8 = COPY %1(<vscale x 1 x s32>)514 PseudoRET implicit $v8515 516...517---518name: zext_nxv1i64_nxv1i16519legalized: true520regBankSelected: true521tracksRegLiveness: true522body: |523 bb.0.entry:524 liveins: $v8525 526 ; RV32I-LABEL: name: zext_nxv1i64_nxv1i16527 ; RV32I: liveins: $v8528 ; RV32I-NEXT: {{ $}}529 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8530 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF531 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */532 ; RV32I-NEXT: $v8 = COPY %1533 ; RV32I-NEXT: PseudoRET implicit $v8534 ;535 ; RV64I-LABEL: name: zext_nxv1i64_nxv1i16536 ; RV64I: liveins: $v8537 ; RV64I-NEXT: {{ $}}538 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8539 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF540 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF4_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */541 ; RV64I-NEXT: $v8 = COPY %1542 ; RV64I-NEXT: PseudoRET implicit $v8543 %0:vrb(<vscale x 1 x s16>) = COPY $v8544 %1:vrb(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s16>)545 $v8 = COPY %1(<vscale x 1 x s64>)546 PseudoRET implicit $v8547 548...549---550name: zext_nxv2i32_nxv2i16551legalized: true552regBankSelected: true553tracksRegLiveness: true554body: |555 bb.0.entry:556 liveins: $v8557 558 ; RV32I-LABEL: name: zext_nxv2i32_nxv2i16559 ; RV32I: liveins: $v8560 ; RV32I-NEXT: {{ $}}561 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8562 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF563 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */564 ; RV32I-NEXT: $v8 = COPY %1565 ; RV32I-NEXT: PseudoRET implicit $v8566 ;567 ; RV64I-LABEL: name: zext_nxv2i32_nxv2i16568 ; RV64I: liveins: $v8569 ; RV64I-NEXT: {{ $}}570 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8571 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF572 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */573 ; RV64I-NEXT: $v8 = COPY %1574 ; RV64I-NEXT: PseudoRET implicit $v8575 %0:vrb(<vscale x 2 x s16>) = COPY $v8576 %1:vrb(<vscale x 2 x s32>) = G_ZEXT %0(<vscale x 2 x s16>)577 $v8 = COPY %1(<vscale x 2 x s32>)578 PseudoRET implicit $v8579 580...581---582name: zext_nxv2i64_nxv2i16583legalized: true584regBankSelected: true585tracksRegLiveness: true586body: |587 bb.0.entry:588 liveins: $v8589 590 ; RV32I-LABEL: name: zext_nxv2i64_nxv2i16591 ; RV32I: liveins: $v8592 ; RV32I-NEXT: {{ $}}593 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8594 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF595 ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */596 ; RV32I-NEXT: $v8m2 = COPY %1597 ; RV32I-NEXT: PseudoRET implicit $v8m2598 ;599 ; RV64I-LABEL: name: zext_nxv2i64_nxv2i16600 ; RV64I: liveins: $v8601 ; RV64I-NEXT: {{ $}}602 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8603 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF604 ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF4_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */605 ; RV64I-NEXT: $v8m2 = COPY %1606 ; RV64I-NEXT: PseudoRET implicit $v8m2607 %0:vrb(<vscale x 2 x s16>) = COPY $v8608 %1:vrb(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s16>)609 $v8m2 = COPY %1(<vscale x 2 x s64>)610 PseudoRET implicit $v8m2611 612...613---614name: zext_nxv4i32_nxv4i16615legalized: true616regBankSelected: true617tracksRegLiveness: true618body: |619 bb.0.entry:620 liveins: $v8621 622 ; RV32I-LABEL: name: zext_nxv4i32_nxv4i16623 ; RV32I: liveins: $v8624 ; RV32I-NEXT: {{ $}}625 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8626 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF627 ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */628 ; RV32I-NEXT: $v8m2 = COPY %1629 ; RV32I-NEXT: PseudoRET implicit $v8m2630 ;631 ; RV64I-LABEL: name: zext_nxv4i32_nxv4i16632 ; RV64I: liveins: $v8633 ; RV64I-NEXT: {{ $}}634 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8635 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF636 ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */637 ; RV64I-NEXT: $v8m2 = COPY %1638 ; RV64I-NEXT: PseudoRET implicit $v8m2639 %0:vrb(<vscale x 4 x s16>) = COPY $v8640 %1:vrb(<vscale x 4 x s32>) = G_ZEXT %0(<vscale x 4 x s16>)641 $v8m2 = COPY %1(<vscale x 4 x s32>)642 PseudoRET implicit $v8m2643 644...645---646name: zext_nxv4i64_nxv4i16647legalized: true648regBankSelected: true649tracksRegLiveness: true650body: |651 bb.0.entry:652 liveins: $v8653 654 ; RV32I-LABEL: name: zext_nxv4i64_nxv4i16655 ; RV32I: liveins: $v8656 ; RV32I-NEXT: {{ $}}657 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8658 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF659 ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */660 ; RV32I-NEXT: $v8m4 = COPY %1661 ; RV32I-NEXT: PseudoRET implicit $v8m4662 ;663 ; RV64I-LABEL: name: zext_nxv4i64_nxv4i16664 ; RV64I: liveins: $v8665 ; RV64I-NEXT: {{ $}}666 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8667 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF668 ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF4_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */669 ; RV64I-NEXT: $v8m4 = COPY %1670 ; RV64I-NEXT: PseudoRET implicit $v8m4671 %0:vrb(<vscale x 4 x s16>) = COPY $v8672 %1:vrb(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s16>)673 $v8m4 = COPY %1(<vscale x 4 x s64>)674 PseudoRET implicit $v8m4675 676...677---678name: zext_nxv8i32_nxv8i16679legalized: true680regBankSelected: true681tracksRegLiveness: true682body: |683 bb.0.entry:684 liveins: $v8m2685 686 ; RV32I-LABEL: name: zext_nxv8i32_nxv8i16687 ; RV32I: liveins: $v8m2688 ; RV32I-NEXT: {{ $}}689 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2690 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF691 ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */692 ; RV32I-NEXT: $v8m4 = COPY %1693 ; RV32I-NEXT: PseudoRET implicit $v8m4694 ;695 ; RV64I-LABEL: name: zext_nxv8i32_nxv8i16696 ; RV64I: liveins: $v8m2697 ; RV64I-NEXT: {{ $}}698 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2699 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF700 ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */701 ; RV64I-NEXT: $v8m4 = COPY %1702 ; RV64I-NEXT: PseudoRET implicit $v8m4703 %0:vrb(<vscale x 8 x s16>) = COPY $v8m2704 %1:vrb(<vscale x 8 x s32>) = G_ZEXT %0(<vscale x 8 x s16>)705 $v8m4 = COPY %1(<vscale x 8 x s32>)706 PseudoRET implicit $v8m4707 708...709---710name: zext_nxv8i64_nxv8i16711legalized: true712regBankSelected: true713tracksRegLiveness: true714body: |715 bb.0.entry:716 liveins: $v8m2717 718 ; RV32I-LABEL: name: zext_nxv8i64_nxv8i16719 ; RV32I: liveins: $v8m2720 ; RV32I-NEXT: {{ $}}721 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2722 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF723 ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */724 ; RV32I-NEXT: $v8m8 = COPY %1725 ; RV32I-NEXT: PseudoRET implicit $v8m8726 ;727 ; RV64I-LABEL: name: zext_nxv8i64_nxv8i16728 ; RV64I: liveins: $v8m2729 ; RV64I-NEXT: {{ $}}730 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2731 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF732 ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF4_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */733 ; RV64I-NEXT: $v8m8 = COPY %1734 ; RV64I-NEXT: PseudoRET implicit $v8m8735 %0:vrb(<vscale x 8 x s16>) = COPY $v8m2736 %1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s16>)737 $v8m8 = COPY %1(<vscale x 8 x s64>)738 PseudoRET implicit $v8m8739 740...741---742name: zext_nxv16i32_nxv16i16743legalized: true744regBankSelected: true745tracksRegLiveness: true746body: |747 bb.0.entry:748 liveins: $v8m4749 750 ; RV32I-LABEL: name: zext_nxv16i32_nxv16i16751 ; RV32I: liveins: $v8m4752 ; RV32I-NEXT: {{ $}}753 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4754 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF755 ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */756 ; RV32I-NEXT: $v8m8 = COPY %1757 ; RV32I-NEXT: PseudoRET implicit $v8m8758 ;759 ; RV64I-LABEL: name: zext_nxv16i32_nxv16i16760 ; RV64I: liveins: $v8m4761 ; RV64I-NEXT: {{ $}}762 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4763 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF764 ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 5 /* e32 */, 3 /* ta, ma */765 ; RV64I-NEXT: $v8m8 = COPY %1766 ; RV64I-NEXT: PseudoRET implicit $v8m8767 %0:vrb(<vscale x 16 x s16>) = COPY $v8m4768 %1:vrb(<vscale x 16 x s32>) = G_ZEXT %0(<vscale x 16 x s16>)769 $v8m8 = COPY %1(<vscale x 16 x s32>)770 PseudoRET implicit $v8m8771 772...773---774name: zext_nxv1i64_nxv1i32775legalized: true776regBankSelected: true777tracksRegLiveness: true778body: |779 bb.0.entry:780 liveins: $v8781 782 ; RV32I-LABEL: name: zext_nxv1i64_nxv1i32783 ; RV32I: liveins: $v8784 ; RV32I-NEXT: {{ $}}785 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8786 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF787 ; RV32I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */788 ; RV32I-NEXT: $v8 = COPY %1789 ; RV32I-NEXT: PseudoRET implicit $v8790 ;791 ; RV64I-LABEL: name: zext_nxv1i64_nxv1i32792 ; RV64I: liveins: $v8793 ; RV64I-NEXT: {{ $}}794 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8795 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF796 ; RV64I-NEXT: early-clobber %1:vr = PseudoVZEXT_VF2_M1 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */797 ; RV64I-NEXT: $v8 = COPY %1798 ; RV64I-NEXT: PseudoRET implicit $v8799 %0:vrb(<vscale x 1 x s32>) = COPY $v8800 %1:vrb(<vscale x 1 x s64>) = G_ZEXT %0(<vscale x 1 x s32>)801 $v8 = COPY %1(<vscale x 1 x s64>)802 PseudoRET implicit $v8803 804...805---806name: zext_nxv2i64_nxv2i32807legalized: true808regBankSelected: true809tracksRegLiveness: true810body: |811 bb.0.entry:812 liveins: $v8813 814 ; RV32I-LABEL: name: zext_nxv2i64_nxv2i32815 ; RV32I: liveins: $v8816 ; RV32I-NEXT: {{ $}}817 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8818 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF819 ; RV32I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */820 ; RV32I-NEXT: $v8m2 = COPY %1821 ; RV32I-NEXT: PseudoRET implicit $v8m2822 ;823 ; RV64I-LABEL: name: zext_nxv2i64_nxv2i32824 ; RV64I: liveins: $v8825 ; RV64I-NEXT: {{ $}}826 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8827 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm2 = IMPLICIT_DEF828 ; RV64I-NEXT: early-clobber %1:vrm2 = PseudoVZEXT_VF2_M2 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */829 ; RV64I-NEXT: $v8m2 = COPY %1830 ; RV64I-NEXT: PseudoRET implicit $v8m2831 %0:vrb(<vscale x 2 x s32>) = COPY $v8832 %1:vrb(<vscale x 2 x s64>) = G_ZEXT %0(<vscale x 2 x s32>)833 $v8m2 = COPY %1(<vscale x 2 x s64>)834 PseudoRET implicit $v8m2835 836...837---838name: zext_nxv4i64_nxv4i32839legalized: true840regBankSelected: true841tracksRegLiveness: true842body: |843 bb.0.entry:844 liveins: $v8m2845 846 ; RV32I-LABEL: name: zext_nxv4i64_nxv4i32847 ; RV32I: liveins: $v8m2848 ; RV32I-NEXT: {{ $}}849 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2850 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF851 ; RV32I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */852 ; RV32I-NEXT: $v8m4 = COPY %1853 ; RV32I-NEXT: PseudoRET implicit $v8m4854 ;855 ; RV64I-LABEL: name: zext_nxv4i64_nxv4i32856 ; RV64I: liveins: $v8m2857 ; RV64I-NEXT: {{ $}}858 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm2 = COPY $v8m2859 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF860 ; RV64I-NEXT: early-clobber %1:vrm4 = PseudoVZEXT_VF2_M4 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */861 ; RV64I-NEXT: $v8m4 = COPY %1862 ; RV64I-NEXT: PseudoRET implicit $v8m4863 %0:vrb(<vscale x 4 x s32>) = COPY $v8m2864 %1:vrb(<vscale x 4 x s64>) = G_ZEXT %0(<vscale x 4 x s32>)865 $v8m4 = COPY %1(<vscale x 4 x s64>)866 PseudoRET implicit $v8m4867 868...869---870name: zext_nxv8i64_nxv8i32871legalized: true872regBankSelected: true873tracksRegLiveness: true874body: |875 bb.0.entry:876 liveins: $v8m4877 878 ; RV32I-LABEL: name: zext_nxv8i64_nxv8i32879 ; RV32I: liveins: $v8m4880 ; RV32I-NEXT: {{ $}}881 ; RV32I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4882 ; RV32I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF883 ; RV32I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */884 ; RV32I-NEXT: $v8m8 = COPY %1885 ; RV32I-NEXT: PseudoRET implicit $v8m8886 ;887 ; RV64I-LABEL: name: zext_nxv8i64_nxv8i32888 ; RV64I: liveins: $v8m4889 ; RV64I-NEXT: {{ $}}890 ; RV64I-NEXT: [[COPY:%[0-9]+]]:vrm4 = COPY $v8m4891 ; RV64I-NEXT: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF892 ; RV64I-NEXT: early-clobber %1:vrm8 = PseudoVZEXT_VF2_M8 [[DEF]], [[COPY]], -1, 6 /* e64 */, 3 /* ta, ma */893 ; RV64I-NEXT: $v8m8 = COPY %1894 ; RV64I-NEXT: PseudoRET implicit $v8m8895 %0:vrb(<vscale x 8 x s32>) = COPY $v8m4896 %1:vrb(<vscale x 8 x s64>) = G_ZEXT %0(<vscale x 8 x s32>)897 $v8m8 = COPY %1(<vscale x 8 x s64>)898 PseudoRET implicit $v8m8899 900...901