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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -mtriple=riscv32 -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4 5# This 32-bit version doesn't have tests for zext, because there is no legal type to zext from.6---7name: shl8legalized: true9regBankSelected: true10tracksRegLiveness: true11body: |12 bb.0:13 liveins: $x10, $x1114 15 ; CHECK-LABEL: name: shl16 ; CHECK: liveins: $x10, $x1117 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1019 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1120 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]21 ; CHECK-NEXT: $x10 = COPY [[SLL]]22 ; CHECK-NEXT: PseudoRET implicit $x1023 %0:gprb(s32) = COPY $x1024 %1:gprb(s32) = COPY $x1125 %3:gprb(s32) = G_SHL %0, %126 $x10 = COPY %3(s32)27 PseudoRET implicit $x1028...29 30---31name: shl_and32legalized: true33regBankSelected: true34tracksRegLiveness: true35body: |36 bb.0:37 liveins: $x10, $x1138 39 ; CHECK-LABEL: name: shl_and40 ; CHECK: liveins: $x10, $x1141 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1043 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1144 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]45 ; CHECK-NEXT: $x10 = COPY [[SLL]]46 ; CHECK-NEXT: PseudoRET implicit $x1047 %0:gprb(s32) = COPY $x1048 %1:gprb(s32) = COPY $x1149 %2:gprb(s32) = G_CONSTANT i32 3150 %3:gprb(s32) = G_AND %1, %251 %4:gprb(s32) = G_SHL %0, %3(s32)52 $x10 = COPY %4(s32)53 PseudoRET implicit $x1054...55 56---57name: shl_and_with_simplified_mask58legalized: true59regBankSelected: true60tracksRegLiveness: true61body: |62 bb.0:63 liveins: $x10, $x1164 65 ; CHECK-LABEL: name: shl_and_with_simplified_mask66 ; CHECK: liveins: $x10, $x1167 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1069 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1170 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 3171 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ANDI]]72 ; CHECK-NEXT: $x10 = COPY [[SLL]]73 ; CHECK-NEXT: PseudoRET implicit $x1074 %0:gprb(s32) = COPY $x1075 %1:gprb(s32) = COPY $x1176 %2:gprb(s32) = G_CONSTANT i32 3177 %3:gprb(s32) = G_AND %1, %278 %4:gprb(s32) = G_CONSTANT i32 3179 %5:gprb(s32) = G_AND %3, %480 %6:gprb(s32) = G_SHL %0, %5(s32)81 $x10 = COPY %6(s32)82 PseudoRET implicit $x1083...84 85---86name: shl_add87legalized: true88regBankSelected: true89tracksRegLiveness: true90body: |91 bb.0:92 liveins: $x10, $x1193 94 ; CHECK-LABEL: name: shl_add95 ; CHECK: liveins: $x10, $x1196 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1098 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1199 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]100 ; CHECK-NEXT: $x10 = COPY [[SLL]]101 ; CHECK-NEXT: PseudoRET implicit $x10102 %0:gprb(s32) = COPY $x10103 %1:gprb(s32) = COPY $x11104 %2:gprb(s32) = G_CONSTANT i32 32105 %3:gprb(s32) = G_ADD %1, %2106 %4:gprb(s32) = G_SHL %0, %3(s32)107 $x10 = COPY %4(s32)108 PseudoRET implicit $x10109...110 111---112name: shl_sub113legalized: true114regBankSelected: true115tracksRegLiveness: true116body: |117 bb.0:118 liveins: $x10, $x11119 120 ; CHECK-LABEL: name: shl_sub121 ; CHECK: liveins: $x10, $x11122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10124 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11125 ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB $x0, [[COPY1]]126 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[SUB]]127 ; CHECK-NEXT: $x10 = COPY [[SLL]]128 ; CHECK-NEXT: PseudoRET implicit $x10129 %0:gprb(s32) = COPY $x10130 %1:gprb(s32) = COPY $x11131 %2:gprb(s32) = G_CONSTANT i32 32132 %3:gprb(s32) = G_SUB %2, %1133 %4:gprb(s32) = G_SHL %0, %3(s32)134 $x10 = COPY %4(s32)135 PseudoRET implicit $x10136...137 138---139name: shl_bitwise_not140legalized: true141regBankSelected: true142tracksRegLiveness: true143body: |144 bb.0:145 liveins: $x10, $x11146 147 ; CHECK-LABEL: name: shl_bitwise_not148 ; CHECK: liveins: $x10, $x11149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10151 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11152 ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1153 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]154 ; CHECK-NEXT: $x10 = COPY [[SLL]]155 ; CHECK-NEXT: PseudoRET implicit $x10156 %0:gprb(s32) = COPY $x10157 %1:gprb(s32) = COPY $x11158 %2:gprb(s32) = G_CONSTANT i32 -1159 %3:gprb(s32) = G_SUB %2, %1160 %4:gprb(s32) = G_SHL %0, %3(s32)161 $x10 = COPY %4(s32)162 PseudoRET implicit $x10163...164 165---166name: shl_bitwise_not_2167legalized: true168regBankSelected: true169tracksRegLiveness: true170body: |171 bb.0:172 liveins: $x10, $x11173 174 ; CHECK-LABEL: name: shl_bitwise_not_2175 ; CHECK: liveins: $x10, $x11176 ; CHECK-NEXT: {{ $}}177 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10178 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11179 ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1180 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]181 ; CHECK-NEXT: $x10 = COPY [[SLL]]182 ; CHECK-NEXT: PseudoRET implicit $x10183 %0:gprb(s32) = COPY $x10184 %1:gprb(s32) = COPY $x11185 %2:gprb(s32) = G_CONSTANT i32 31186 %3:gprb(s32) = G_SUB %2, %1187 %4:gprb(s32) = G_SHL %0, %3(s32)188 $x10 = COPY %4(s32)189 PseudoRET implicit $x10190...191 192---193name: srl_and_needed194legalized: true195regBankSelected: true196tracksRegLiveness: true197body: |198 bb.1.entry:199 liveins: $x10, $x11200 201 ; CHECK-LABEL: name: srl_and_needed202 ; CHECK: liveins: $x10, $x11203 ; CHECK-NEXT: {{ $}}204 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10205 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11206 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15207 ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]208 ; CHECK-NEXT: $x10 = COPY [[SRL]]209 ; CHECK-NEXT: PseudoRET implicit $x10210 %0:gprb(s32) = COPY $x10211 %1:gprb(s32) = COPY $x11212 %2:gprb(s32) = G_CONSTANT i32 15213 %3:gprb(s32) = G_AND %0, %2214 %4:gprb(s32) = G_LSHR %1, %3(s32)215 $x10 = COPY %4(s32)216 PseudoRET implicit $x10217...218 219---220name: srl_and_eliminated221legalized: true222regBankSelected: true223tracksRegLiveness: true224body: |225 bb.1.entry:226 liveins: $x10, $x11227 228 ; CHECK-LABEL: name: srl_and_eliminated229 ; CHECK: liveins: $x10, $x11230 ; CHECK-NEXT: {{ $}}231 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10232 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11233 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 47234 ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]235 ; CHECK-NEXT: $x10 = COPY [[SRL]]236 ; CHECK-NEXT: PseudoRET implicit $x10237 %0:gprb(s32) = COPY $x10238 %1:gprb(s32) = COPY $x11239 %2:gprb(s32) = G_CONSTANT i32 15240 %3:gprb(s32) = G_CONSTANT i32 47241 %4:gprb(s32) = G_AND %0, %3242 %5:gprb(s32) = G_AND %4, %2243 %6:gprb(s32) = G_LSHR %1, %5(s32)244 $x10 = COPY %6(s32)245 PseudoRET implicit $x10246...247