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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42# RUN: llc -mtriple=riscv64 -run-pass=instruction-select \3# RUN: -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s4 5---6name: shl7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0:12 liveins: $x10, $x1113 14 ; CHECK-LABEL: name: shl15 ; CHECK: liveins: $x10, $x1116 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1018 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1119 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]20 ; CHECK-NEXT: $x10 = COPY [[SLL]]21 ; CHECK-NEXT: PseudoRET implicit $x1022 %0:gprb(s64) = COPY $x1023 %1:gprb(s64) = COPY $x1124 %3:gprb(s64) = G_SHL %0, %125 $x10 = COPY %3(s64)26 PseudoRET implicit $x1027...28 29---30name: shl_and31legalized: true32regBankSelected: true33tracksRegLiveness: true34body: |35 bb.0:36 liveins: $x10, $x1137 38 ; CHECK-LABEL: name: shl_and39 ; CHECK: liveins: $x10, $x1140 ; CHECK-NEXT: {{ $}}41 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1042 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1143 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]44 ; CHECK-NEXT: $x10 = COPY [[SLL]]45 ; CHECK-NEXT: PseudoRET implicit $x1046 %0:gprb(s64) = COPY $x1047 %1:gprb(s64) = COPY $x1148 %2:gprb(s64) = G_CONSTANT i64 6349 %3:gprb(s64) = G_AND %1, %250 %4:gprb(s64) = G_SHL %0, %3(s64)51 $x10 = COPY %4(s64)52 PseudoRET implicit $x1053...54 55---56name: shl_and_with_simplified_mask57legalized: true58regBankSelected: true59tracksRegLiveness: true60body: |61 bb.0:62 liveins: $x10, $x1163 64 ; CHECK-LABEL: name: shl_and_with_simplified_mask65 ; CHECK: liveins: $x10, $x1166 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1068 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1169 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 6270 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ANDI]]71 ; CHECK-NEXT: $x10 = COPY [[SLL]]72 ; CHECK-NEXT: PseudoRET implicit $x1073 %0:gprb(s64) = COPY $x1074 %1:gprb(s64) = COPY $x1175 %2:gprb(s64) = G_CONSTANT i64 6276 %3:gprb(s64) = G_AND %1, %277 %4:gprb(s64) = G_CONSTANT i64 6278 %5:gprb(s64) = G_AND %3, %479 %6:gprb(s64) = G_SHL %0, %5(s64)80 $x10 = COPY %6(s64)81 PseudoRET implicit $x1082...83 84---85name: shl_add86legalized: true87regBankSelected: true88tracksRegLiveness: true89body: |90 bb.0:91 liveins: $x10, $x1192 93 ; CHECK-LABEL: name: shl_add94 ; CHECK: liveins: $x10, $x1195 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1097 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1198 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]99 ; CHECK-NEXT: $x10 = COPY [[SLL]]100 ; CHECK-NEXT: PseudoRET implicit $x10101 %0:gprb(s64) = COPY $x10102 %1:gprb(s64) = COPY $x11103 %2:gprb(s64) = G_CONSTANT i64 64104 %3:gprb(s64) = G_ADD %1, %2105 %4:gprb(s64) = G_SHL %0, %3(s64)106 $x10 = COPY %4(s64)107 PseudoRET implicit $x10108...109 110---111name: shl_sub112legalized: true113regBankSelected: true114tracksRegLiveness: true115body: |116 bb.0:117 liveins: $x10, $x11118 119 ; CHECK-LABEL: name: shl_sub120 ; CHECK: liveins: $x10, $x11121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10123 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11124 ; CHECK-NEXT: [[SUBW:%[0-9]+]]:gpr = SUBW $x0, [[COPY1]]125 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[SUBW]]126 ; CHECK-NEXT: $x10 = COPY [[SLL]]127 ; CHECK-NEXT: PseudoRET implicit $x10128 %0:gprb(s64) = COPY $x10129 %1:gprb(s64) = COPY $x11130 %2:gprb(s64) = G_CONSTANT i64 64131 %3:gprb(s64) = G_SUB %2, %1132 %4:gprb(s64) = G_SHL %0, %3(s64)133 $x10 = COPY %4(s64)134 PseudoRET implicit $x10135...136 137---138name: shl_bitwise_not139legalized: true140regBankSelected: true141tracksRegLiveness: true142body: |143 bb.0:144 liveins: $x10, $x11145 146 ; CHECK-LABEL: name: shl_bitwise_not147 ; CHECK: liveins: $x10, $x11148 ; CHECK-NEXT: {{ $}}149 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10150 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11151 ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1152 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]153 ; CHECK-NEXT: $x10 = COPY [[SLL]]154 ; CHECK-NEXT: PseudoRET implicit $x10155 %0:gprb(s64) = COPY $x10156 %1:gprb(s64) = COPY $x11157 %2:gprb(s64) = G_CONSTANT i64 -1158 %3:gprb(s64) = G_SUB %2, %1159 %4:gprb(s64) = G_SHL %0, %3(s64)160 $x10 = COPY %4(s64)161 PseudoRET implicit $x10162...163 164---165name: shl_bitwise_not_2166legalized: true167regBankSelected: true168tracksRegLiveness: true169body: |170 bb.0:171 liveins: $x10, $x11172 173 ; CHECK-LABEL: name: shl_bitwise_not_2174 ; CHECK: liveins: $x10, $x11175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10177 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11178 ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1179 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]180 ; CHECK-NEXT: $x10 = COPY [[SLL]]181 ; CHECK-NEXT: PseudoRET implicit $x10182 %0:gprb(s64) = COPY $x10183 %1:gprb(s64) = COPY $x11184 %2:gprb(s64) = G_CONSTANT i64 63185 %3:gprb(s64) = G_SUB %2, %1186 %4:gprb(s64) = G_SHL %0, %3(s64)187 $x10 = COPY %4(s64)188 PseudoRET implicit $x10189...190 191---192name: shl_and_zext193legalized: true194regBankSelected: true195tracksRegLiveness: true196body: |197 bb.0:198 liveins: $x10, $x11199 200 ; CHECK-LABEL: name: shl_and_zext201 ; CHECK: liveins: $x10, $x11202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11205 ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY1]], 0 :: (load (s32))206 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[LW]]207 ; CHECK-NEXT: $x10 = COPY [[SLL]]208 ; CHECK-NEXT: PseudoRET implicit $x10209 %0:gprb(s64) = COPY $x10210 %1:gprb(p0) = COPY $x11211 %2:gprb(s64) = G_LOAD %1(p0) :: (load (s32))212 %3:gprb(s64) = G_CONSTANT i64 63213 %4:gprb(s64) = G_AND %2, %3214 %5:gprb(s64) = G_SHL %0, %4(s64)215 $x10 = COPY %5(s64)216 PseudoRET implicit $x10217...218 219---220name: srl_and_needed221legalized: true222regBankSelected: true223tracksRegLiveness: true224body: |225 bb.1.entry:226 liveins: $x10, $x11227 228 ; CHECK-LABEL: name: srl_and_needed229 ; CHECK: liveins: $x10, $x11230 ; CHECK-NEXT: {{ $}}231 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10232 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11233 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15234 ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]235 ; CHECK-NEXT: $x10 = COPY [[SRL]]236 ; CHECK-NEXT: PseudoRET implicit $x10237 %0:gprb(s64) = COPY $x10238 %1:gprb(s64) = COPY $x11239 %2:gprb(s64) = G_CONSTANT i64 15240 %3:gprb(s64) = G_AND %0, %2241 %4:gprb(s64) = G_LSHR %1, %3(s64)242 $x10 = COPY %4(s64)243 PseudoRET implicit $x10244...245 246---247name: srl_and_eliminated248legalized: true249regBankSelected: true250tracksRegLiveness: true251body: |252 bb.1.entry:253 liveins: $x10, $x11254 255 ; CHECK-LABEL: name: srl_and_eliminated256 ; CHECK: liveins: $x10, $x11257 ; CHECK-NEXT: {{ $}}258 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10259 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11260 ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 79261 ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]262 ; CHECK-NEXT: $x10 = COPY [[SRL]]263 ; CHECK-NEXT: PseudoRET implicit $x10264 %0:gprb(s64) = COPY $x10265 %1:gprb(s64) = COPY $x11266 %2:gprb(s64) = G_CONSTANT i64 15267 %6:gprb(s64) = G_CONSTANT i64 79268 %7:gprb(s64) = G_AND %0, %6269 %3:gprb(s64) = G_AND %7, %2270 %5:gprb(s64) = G_LSHR %1, %3(s64)271 $x10 = COPY %5(s64)272 PseudoRET implicit $x10273...274