153 lines · plain
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=riscv32 -mattr='+zba' -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \3# RUN: | FileCheck %s4 5---6name: sh1add7legalized: true8regBankSelected: true9tracksRegLiveness: true10body: |11 bb.0.entry:12 liveins: $x10, $x1113 14 ; CHECK-LABEL: name: sh1add15 ; CHECK: liveins: $x10, $x1116 ; CHECK-NEXT: {{ $}}17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1018 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1119 ; CHECK-NEXT: [[SH1ADD:%[0-9]+]]:gpr = SH1ADD [[COPY]], [[COPY1]]20 ; CHECK-NEXT: $x10 = COPY [[SH1ADD]]21 %0:gprb(s32) = COPY $x1022 %1:gprb(s32) = COPY $x1123 %2:gprb(s32) = G_CONSTANT i32 124 %3:gprb(s32) = G_SHL %0, %225 %4:gprb(s32) = G_ADD %3, %126 $x10 = COPY %4(s32)27...28---29name: sh2add30legalized: true31regBankSelected: true32tracksRegLiveness: true33body: |34 bb.0.entry:35 liveins: $x10, $x1136 37 ; CHECK-LABEL: name: sh2add38 ; CHECK: liveins: $x10, $x1139 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1041 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1142 ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[COPY]], [[COPY1]]43 ; CHECK-NEXT: $x10 = COPY [[SH2ADD]]44 %0:gprb(s32) = COPY $x1045 %1:gprb(s32) = COPY $x1146 %2:gprb(s32) = G_CONSTANT i32 247 %3:gprb(s32) = G_SHL %0, %248 %4:gprb(s32) = G_ADD %3, %149 $x10 = COPY %4(s32)50...51---52name: sh3add53legalized: true54regBankSelected: true55tracksRegLiveness: true56body: |57 bb.0.entry:58 liveins: $x10, $x1159 60 ; CHECK-LABEL: name: sh3add61 ; CHECK: liveins: $x10, $x1162 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1064 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x1165 ; CHECK-NEXT: [[SH3ADD:%[0-9]+]]:gpr = SH3ADD [[COPY]], [[COPY1]]66 ; CHECK-NEXT: $x10 = COPY [[SH3ADD]]67 %0:gprb(s32) = COPY $x1068 %1:gprb(s32) = COPY $x1169 %2:gprb(s32) = G_CONSTANT i32 370 %3:gprb(s32) = G_SHL %0, %271 %4:gprb(s32) = G_ADD %3, %172 $x10 = COPY %4(s32)73...74---75name: no_sh1add76legalized: true77regBankSelected: true78tracksRegLiveness: true79body: |80 bb.0.entry:81 liveins: $x10, $x1182 83 ; CHECK-LABEL: name: no_sh1add84 ; CHECK: liveins: $x10, $x1185 ; CHECK-NEXT: {{ $}}86 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x1087 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 188 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[SLLI]], 3789 ; CHECK-NEXT: $x10 = COPY [[ADDI]]90 %0:gprb(s32) = COPY $x1091 %1:gprb(s32) = G_CONSTANT i32 3792 %2:gprb(s32) = G_CONSTANT i32 193 %3:gprb(s32) = G_SHL %0, %294 %4:gprb(s32) = G_ADD %3, %195 $x10 = COPY %4(s32)96...97---98name: shXadd_complex_shl_and99legalized: true100regBankSelected: true101tracksRegLiveness: true102body: |103 bb.0.entry:104 liveins: $x10, $x11105 106 ; CHECK-LABEL: name: shXadd_complex_shl_and107 ; CHECK: liveins: $x10, $x11108 ; CHECK-NEXT: {{ $}}109 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11111 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 1112 ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[SRLI]], [[COPY1]]113 ; CHECK-NEXT: $x10 = COPY [[SH2ADD]]114 %0:gprb(s32) = COPY $x10115 %1:gprb(s32) = COPY $x11116 117 %2:gprb(s32) = G_CONSTANT i32 1118 %3:gprb(s32) = G_SHL %0, %2119 %4:gprb(s32) = G_CONSTANT i32 4294967292120 %5:gprb(s32) = G_AND %3, %4121 122 %6:gprb(s32) = G_ADD %5, %1123 $x10 = COPY %6(s32)124...125---126name: shXadd_complex_lshr_and127legalized: true128regBankSelected: true129tracksRegLiveness: true130body: |131 bb.0.entry:132 liveins: $x10, $x11133 134 ; CHECK-LABEL: name: shXadd_complex_lshr_and135 ; CHECK: liveins: $x10, $x11136 ; CHECK-NEXT: {{ $}}137 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10138 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11139 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 29140 ; CHECK-NEXT: [[SH2ADD:%[0-9]+]]:gpr = SH2ADD [[SRLI]], [[COPY1]]141 ; CHECK-NEXT: $x10 = COPY [[SH2ADD]]142 %0:gprb(s32) = COPY $x10143 %1:gprb(s32) = COPY $x11144 145 %2:gprb(s32) = G_CONSTANT i32 27146 %3:gprb(s32) = G_LSHR %0, %2147 %4:gprb(s32) = G_CONSTANT i32 60148 %5:gprb(s32) = G_AND %3, %4149 150 %6:gprb(s32) = G_ADD %5, %1151 $x10 = COPY %6(s32)152...153