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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \3; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \4; RUN: | FileCheck -check-prefix=RV32-ILP32D %s5 6; This file contains tests that will have differing output for the ilp32/ilp32f7; and ilp32d ABIs.8 9define i32 @callee_double_in_fpr(i32 %a, double %b) nounwind {10 ; RV32-ILP32D-LABEL: name: callee_double_in_fpr11 ; RV32-ILP32D: bb.1 (%ir-block.0):12 ; RV32-ILP32D-NEXT: liveins: $x10, $f10_d13 ; RV32-ILP32D-NEXT: {{ $}}14 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1015 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d16 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY1]](s64)17 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[FPTOSI]]18 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)19 ; RV32-ILP32D-NEXT: PseudoRET implicit $x1020 %b_fptosi = fptosi double %b to i3221 %1 = add i32 %a, %b_fptosi22 ret i32 %123}24 25define i32 @caller_double_in_fpr() nounwind {26 ; RV32-ILP32D-LABEL: name: caller_double_in_fpr27 ; RV32-ILP32D: bb.1 (%ir-block.0):28 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 129 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+0030 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x231 ; RV32-ILP32D-NEXT: $x10 = COPY [[C]](s32)32 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64)33 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x1034 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x235 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1036 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)37 ; RV32-ILP32D-NEXT: PseudoRET implicit $x1038 %1 = call i32 @callee_double_in_fpr(i32 1, double 2.0)39 ret i32 %140}41 42; Must keep define on a single line due to an update_llc_test_checks.py limitation43define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind {44 ; RV32-ILP32D-LABEL: name: callee_double_in_fpr_exhausted_gprs45 ; RV32-ILP32D: bb.1 (%ir-block.0):46 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_d47 ; RV32-ILP32D-NEXT: {{ $}}48 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1049 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1150 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)51 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x1252 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x1353 ; RV32-ILP32D-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)54 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x1455 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x1556 ; RV32-ILP32D-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)57 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x1658 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x1759 ; RV32-ILP32D-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)60 ; RV32-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.061 ; RV32-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)62 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $f10_d63 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY8]](s64)64 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[FPTOSI]]65 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)66 ; RV32-ILP32D-NEXT: PseudoRET implicit $x1067 %f_fptosi = fptosi double %f to i3268 %1 = add i32 %e, %f_fptosi69 ret i32 %170}71 72define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {73 ; RV32-ILP32D-LABEL: name: caller_double_in_fpr_exhausted_gprs74 ; RV32-ILP32D: bb.1 (%ir-block.0):75 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 176 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 277 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 378 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 479 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 580 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+0081 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x282 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)83 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)84 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)85 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)86 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x287 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 088 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32)89 ; RV32-ILP32D-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)90 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)91 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)92 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)93 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)94 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)95 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)96 ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32)97 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32)98 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C5]](s64)99 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10100 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2101 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10102 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)103 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10104 %1 = call i32 @callee_double_in_fpr_exhausted_gprs(105 i64 1, i64 2, i64 3, i64 4, i32 5, double 6.0)106 ret i32 %1107}108 109; Must keep define on a single line due to an update_llc_test_checks.py limitation110define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind {111 ; RV32-ILP32D-LABEL: name: callee_double_in_gpr_exhausted_fprs112 ; RV32-ILP32D: bb.1 (%ir-block.0):113 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $f10_d, $f11_d, $f12_d, $f13_d, $f14_d, $f15_d, $f16_d, $f17_d114 ; RV32-ILP32D-NEXT: {{ $}}115 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d116 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d117 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f12_d118 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $f13_d119 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $f14_d120 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $f15_d121 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $f16_d122 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $f17_d123 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10124 ; RV32-ILP32D-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x11125 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)126 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY7]](s64)127 ; RV32-ILP32D-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[MV]](s64)128 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOSI]], [[FPTOSI1]]129 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)130 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10131 %h_fptosi = fptosi double %h to i32132 %i_fptosi = fptosi double %i to i32133 %1 = add i32 %h_fptosi, %i_fptosi134 ret i32 %1135}136 137define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {138 ; RV32-ILP32D-LABEL: name: caller_double_in_gpr_exhausted_fprs139 ; RV32-ILP32D: bb.1 (%ir-block.0):140 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00141 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00142 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 3.000000e+00143 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00144 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e+00145 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+00146 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s64) = G_FCONSTANT double 7.000000e+00147 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00148 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 9.000000e+00149 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2150 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C8]](s64)151 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C]](s64)152 ; RV32-ILP32D-NEXT: $f11_d = COPY [[C1]](s64)153 ; RV32-ILP32D-NEXT: $f12_d = COPY [[C2]](s64)154 ; RV32-ILP32D-NEXT: $f13_d = COPY [[C3]](s64)155 ; RV32-ILP32D-NEXT: $f14_d = COPY [[C4]](s64)156 ; RV32-ILP32D-NEXT: $f15_d = COPY [[C5]](s64)157 ; RV32-ILP32D-NEXT: $f16_d = COPY [[C6]](s64)158 ; RV32-ILP32D-NEXT: $f17_d = COPY [[C7]](s64)159 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)160 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)161 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit $x11, implicit-def $x10162 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2163 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10164 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)165 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10166 %1 = call i32 @callee_double_in_gpr_exhausted_fprs(167 double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,168 double 7.0, double 8.0, double 9.0)169 ret i32 %1170}171 172; Must keep define on a single line due to an update_llc_test_checks.py limitation173define i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i32 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {174 ; RV32-ILP32D-LABEL: name: callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs175 ; RV32-ILP32D: bb.1 (%ir-block.0):176 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_d, $f11_d, $f12_d, $f13_d, $f14_d, $f15_d, $f16_d, $f17_d177 ; RV32-ILP32D-NEXT: {{ $}}178 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10179 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11180 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)181 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f10_d182 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x12183 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x13184 ; RV32-ILP32D-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)185 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $f11_d186 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x14187 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x15188 ; RV32-ILP32D-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)189 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $f12_d190 ; RV32-ILP32D-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x16191 ; RV32-ILP32D-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $f13_d192 ; RV32-ILP32D-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $f14_d193 ; RV32-ILP32D-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $f15_d194 ; RV32-ILP32D-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $f16_d195 ; RV32-ILP32D-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $f17_d196 ; RV32-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0197 ; RV32-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)198 ; RV32-ILP32D-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x17199 ; RV32-ILP32D-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY15]](s32), [[LOAD]](s32)200 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[MV3]](s64)201 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY9]], [[FPTOSI]]202 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)203 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10204 %m_fptosi = fptosi double %m to i32205 %1 = add i32 %g, %m_fptosi206 ret i32 %1207}208 209define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind {210 ; RV32-ILP32D-LABEL: name: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs211 ; RV32-ILP32D: bb.1 (%ir-block.0):212 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1213 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00214 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3215 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00216 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5217 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+00218 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7219 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00220 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 9.000000e+00221 ; RV32-ILP32D-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+01222 ; RV32-ILP32D-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.100000e+01223 ; RV32-ILP32D-NEXT: [[C11:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.200000e+01224 ; RV32-ILP32D-NEXT: [[C12:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.300000e+01225 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 4, 0, implicit-def $x2, implicit $x2226 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)227 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)228 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)229 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C12]](s64)230 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2231 ; RV32-ILP32D-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0232 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32)233 ; RV32-ILP32D-NEXT: G_STORE [[UV7]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)234 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)235 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)236 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64)237 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)238 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)239 ; RV32-ILP32D-NEXT: $f11_d = COPY [[C3]](s64)240 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)241 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)242 ; RV32-ILP32D-NEXT: $f12_d = COPY [[C5]](s64)243 ; RV32-ILP32D-NEXT: $x16 = COPY [[C6]](s32)244 ; RV32-ILP32D-NEXT: $f13_d = COPY [[C7]](s64)245 ; RV32-ILP32D-NEXT: $f14_d = COPY [[C8]](s64)246 ; RV32-ILP32D-NEXT: $f15_d = COPY [[C9]](s64)247 ; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64)248 ; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64)249 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV6]](s32)250 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x17, implicit-def $x10251 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $x2, implicit $x2252 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10253 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)254 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10255 %1 = call i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(256 i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i32 7, double 8.0,257 double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)258 ret i32 %1259}260 261 262; Must keep define on a single line due to an update_llc_test_checks.py limitation263define i32 @callee_double_on_stack_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i64 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {264 ; RV32-ILP32D-LABEL: name: callee_double_on_stack_exhausted_gprs_fprs265 ; RV32-ILP32D: bb.1 (%ir-block.0):266 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_d, $f11_d, $f12_d, $f13_d, $f14_d, $f15_d, $f16_d, $f17_d267 ; RV32-ILP32D-NEXT: {{ $}}268 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10269 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11270 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)271 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f10_d272 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x12273 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x13274 ; RV32-ILP32D-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)275 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $f11_d276 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x14277 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x15278 ; RV32-ILP32D-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)279 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $f12_d280 ; RV32-ILP32D-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x16281 ; RV32-ILP32D-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x17282 ; RV32-ILP32D-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32)283 ; RV32-ILP32D-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $f13_d284 ; RV32-ILP32D-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $f14_d285 ; RV32-ILP32D-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $f15_d286 ; RV32-ILP32D-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $f16_d287 ; RV32-ILP32D-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $f17_d288 ; RV32-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0289 ; RV32-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0, align 16)290 ; RV32-ILP32D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s64)291 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[LOAD]](s64)292 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[FPTOSI]]293 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)294 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10295 %g_trunc = trunc i64 %g to i32296 %m_fptosi = fptosi double %m to i32297 %1 = add i32 %g_trunc, %m_fptosi298 ret i32 %1299}300 301define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {302 ; RV32-ILP32D-LABEL: name: caller_double_on_stack_exhausted_gprs_fprs303 ; RV32-ILP32D: bb.1 (%ir-block.0):304 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1305 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00306 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3307 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00308 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5309 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+00310 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7311 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00312 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 9.000000e+00313 ; RV32-ILP32D-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+01314 ; RV32-ILP32D-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.100000e+01315 ; RV32-ILP32D-NEXT: [[C11:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.200000e+01316 ; RV32-ILP32D-NEXT: [[C12:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.300000e+01317 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 8, 0, implicit-def $x2, implicit $x2318 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)319 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)320 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)321 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)322 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2323 ; RV32-ILP32D-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0324 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32)325 ; RV32-ILP32D-NEXT: G_STORE [[C12]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)326 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)327 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)328 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64)329 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)330 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)331 ; RV32-ILP32D-NEXT: $f11_d = COPY [[C3]](s64)332 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)333 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)334 ; RV32-ILP32D-NEXT: $f12_d = COPY [[C5]](s64)335 ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32)336 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32)337 ; RV32-ILP32D-NEXT: $f13_d = COPY [[C7]](s64)338 ; RV32-ILP32D-NEXT: $f14_d = COPY [[C8]](s64)339 ; RV32-ILP32D-NEXT: $f15_d = COPY [[C9]](s64)340 ; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64)341 ; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64)342 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10343 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $x2, implicit $x2344 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10345 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)346 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10347 %1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs(348 i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0,349 double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)350 ret i32 %1351}352 353define double @callee_double_ret() nounwind {354 ; RV32-ILP32D-LABEL: name: callee_double_ret355 ; RV32-ILP32D: bb.1 (%ir-block.0):356 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00357 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C]](s64)358 ; RV32-ILP32D-NEXT: PseudoRET implicit $f10_d359 ret double 1.0360}361 362define i32 @caller_double_ret() nounwind {363 ; RV32-ILP32D-LABEL: name: caller_double_ret364 ; RV32-ILP32D: bb.1 (%ir-block.0):365 ; RV32-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2366 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, csr_ilp32d_lp64d, implicit-def $x1, implicit-def $f10_d367 ; RV32-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2368 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d369 ; RV32-ILP32D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)370 ; RV32-ILP32D-NEXT: $x10 = COPY [[TRUNC]](s32)371 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10372 %1 = call double @callee_double_ret()373 %2 = bitcast double %1 to i64374 %3 = trunc i64 %2 to i32375 ret i32 %3376}377