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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator \3; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator \5; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s6 7define <vscale x 1 x i1> @insertelement_nxv1i1_0() {8  ; RV32-LABEL: name: insertelement_nxv1i1_09  ; RV32: bb.1 (%ir-block.0):10  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF11  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false12  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 013  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)14  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 1 x s1>)15  ; RV32-NEXT:   PseudoRET implicit $v016  ;17  ; RV64-LABEL: name: insertelement_nxv1i1_018  ; RV64: bb.1 (%ir-block.0):19  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF20  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false21  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 022  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)23  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 1 x s1>)24  ; RV64-NEXT:   PseudoRET implicit $v025  %a = insertelement <vscale x 1 x i1> poison, i1 0, i32 026  ret <vscale x 1 x i1> %a27}28 29define <vscale x 1 x i1> @insertelement_nxv1i1_1() {30  ; RV32-LABEL: name: insertelement_nxv1i1_131  ; RV32: bb.1 (%ir-block.0):32  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF33  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true34  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 035  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)36  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 1 x s1>)37  ; RV32-NEXT:   PseudoRET implicit $v038  ;39  ; RV64-LABEL: name: insertelement_nxv1i1_140  ; RV64: bb.1 (%ir-block.0):41  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF42  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true43  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 044  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)45  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 1 x s1>)46  ; RV64-NEXT:   PseudoRET implicit $v047  %a = insertelement <vscale x 1 x i1> poison, i1 -1, i32 048  ret <vscale x 1 x i1> %a49}50 51define <vscale x 1 x i1> @insertelement_nxv1i1_2(i1 %x, i32 %idx) {52  ; RV32-LABEL: name: insertelement_nxv1i1_253  ; RV32: bb.1 (%ir-block.0):54  ; RV32-NEXT:   liveins: $x10, $x1155  ; RV32-NEXT: {{  $}}56  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x1057  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)58  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x1159  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF60  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)61  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 1 x s1>)62  ; RV32-NEXT:   PseudoRET implicit $v063  ;64  ; RV64-LABEL: name: insertelement_nxv1i1_265  ; RV64: bb.1 (%ir-block.0):66  ; RV64-NEXT:   liveins: $x10, $x1167  ; RV64-NEXT: {{  $}}68  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x1069  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)70  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x1171  ; RV64-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)72  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF73  ; RV64-NEXT:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32)74  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64)75  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 1 x s1>)76  ; RV64-NEXT:   PseudoRET implicit $v077  %a = insertelement <vscale x 1 x i1> poison, i1 %x, i32 %idx78  ret <vscale x 1 x i1> %a79}80 81define <vscale x 2 x i1> @insertelement_nxv2i1_0() {82  ; RV32-LABEL: name: insertelement_nxv2i1_083  ; RV32: bb.1 (%ir-block.0):84  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF85  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false86  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 187  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)88  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 2 x s1>)89  ; RV32-NEXT:   PseudoRET implicit $v090  ;91  ; RV64-LABEL: name: insertelement_nxv2i1_092  ; RV64: bb.1 (%ir-block.0):93  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF94  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false95  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 196  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)97  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 2 x s1>)98  ; RV64-NEXT:   PseudoRET implicit $v099  %a = insertelement <vscale x 2 x i1> poison, i1 0, i32 1100  ret <vscale x 2 x i1> %a101}102 103define <vscale x 2 x i1> @insertelement_nxv2i1_1() {104  ; RV32-LABEL: name: insertelement_nxv2i1_1105  ; RV32: bb.1 (%ir-block.0):106  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF107  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true108  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0109  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)110  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 2 x s1>)111  ; RV32-NEXT:   PseudoRET implicit $v0112  ;113  ; RV64-LABEL: name: insertelement_nxv2i1_1114  ; RV64: bb.1 (%ir-block.0):115  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF116  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true117  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0118  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)119  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 2 x s1>)120  ; RV64-NEXT:   PseudoRET implicit $v0121  %a = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0122  ret <vscale x 2 x i1> %a123}124 125define <vscale x 2 x i1> @insertelement_nxv2i1_2(i1 %x, i32 %idx) {126  ; RV32-LABEL: name: insertelement_nxv2i1_2127  ; RV32: bb.1 (%ir-block.0):128  ; RV32-NEXT:   liveins: $x10, $x11129  ; RV32-NEXT: {{  $}}130  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10131  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)132  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11133  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF134  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)135  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 2 x s1>)136  ; RV32-NEXT:   PseudoRET implicit $v0137  ;138  ; RV64-LABEL: name: insertelement_nxv2i1_2139  ; RV64: bb.1 (%ir-block.0):140  ; RV64-NEXT:   liveins: $x10, $x11141  ; RV64-NEXT: {{  $}}142  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10143  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)144  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11145  ; RV64-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)146  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF147  ; RV64-NEXT:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32)148  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64)149  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 2 x s1>)150  ; RV64-NEXT:   PseudoRET implicit $v0151  %a = insertelement <vscale x 2 x i1> poison, i1 %x, i32 %idx152  ret <vscale x 2 x i1> %a153}154 155define <vscale x 4 x i1> @insertelement_nxv4i1_0() {156  ; RV32-LABEL: name: insertelement_nxv4i1_0157  ; RV32: bb.1 (%ir-block.0):158  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF159  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false160  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2161  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)162  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)163  ; RV32-NEXT:   PseudoRET implicit $v0164  ;165  ; RV64-LABEL: name: insertelement_nxv4i1_0166  ; RV64: bb.1 (%ir-block.0):167  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF168  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false169  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2170  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)171  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)172  ; RV64-NEXT:   PseudoRET implicit $v0173  %a = insertelement <vscale x 4 x i1> poison, i1 0, i32 2174  ret <vscale x 4 x i1> %a175}176 177define <vscale x 4 x i1> @insertelement_nxv4i1_1() {178  ; RV32-LABEL: name: insertelement_nxv4i1_1179  ; RV32: bb.1 (%ir-block.0):180  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF181  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true182  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0183  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)184  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)185  ; RV32-NEXT:   PseudoRET implicit $v0186  ;187  ; RV64-LABEL: name: insertelement_nxv4i1_1188  ; RV64: bb.1 (%ir-block.0):189  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF190  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true191  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0192  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)193  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)194  ; RV64-NEXT:   PseudoRET implicit $v0195  %a = insertelement <vscale x 4 x i1> poison, i1 -1, i32 0196  ret <vscale x 4 x i1> %a197}198 199define <vscale x 4 x i1> @insertelement_nxv4i1_2(i1 %x) {200  ; RV32-LABEL: name: insertelement_nxv4i1_2201  ; RV32: bb.1 (%ir-block.0):202  ; RV32-NEXT:   liveins: $x10203  ; RV32-NEXT: {{  $}}204  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10205  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)206  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF207  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0208  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s32)209  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)210  ; RV32-NEXT:   PseudoRET implicit $v0211  ;212  ; RV64-LABEL: name: insertelement_nxv4i1_2213  ; RV64: bb.1 (%ir-block.0):214  ; RV64-NEXT:   liveins: $x10215  ; RV64-NEXT: {{  $}}216  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10217  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)218  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF219  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0220  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[C]](s64)221  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)222  ; RV64-NEXT:   PseudoRET implicit $v0223  %a = insertelement <vscale x 4 x i1> poison, i1 %x, i32 0224  ret <vscale x 4 x i1> %a225}226 227define <vscale x 8 x i1> @insertelement_nxv8i1_0() {228  ; RV32-LABEL: name: insertelement_nxv8i1_0229  ; RV32: bb.1 (%ir-block.0):230  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF231  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false232  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0233  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)234  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 8 x s1>)235  ; RV32-NEXT:   PseudoRET implicit $v0236  ;237  ; RV64-LABEL: name: insertelement_nxv8i1_0238  ; RV64: bb.1 (%ir-block.0):239  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF240  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false241  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0242  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)243  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 8 x s1>)244  ; RV64-NEXT:   PseudoRET implicit $v0245  %a = insertelement <vscale x 8 x i1> poison, i1 0, i32 0246  ret <vscale x 8 x i1> %a247}248 249define <vscale x 8 x i1> @insertelement_nxv8i1_1() {250  ; RV32-LABEL: name: insertelement_nxv8i1_1251  ; RV32: bb.1 (%ir-block.0):252  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF253  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true254  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0255  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)256  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 8 x s1>)257  ; RV32-NEXT:   PseudoRET implicit $v0258  ;259  ; RV64-LABEL: name: insertelement_nxv8i1_1260  ; RV64: bb.1 (%ir-block.0):261  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF262  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true263  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0264  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)265  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 8 x s1>)266  ; RV64-NEXT:   PseudoRET implicit $v0267  %a = insertelement <vscale x 8 x i1> poison, i1 -1, i32 0268  ret <vscale x 8 x i1> %a269}270 271define <vscale x 8 x i1> @insertelement_nxv8i1_2(i1 %x, i32 %idx) {272  ; RV32-LABEL: name: insertelement_nxv8i1_2273  ; RV32: bb.1 (%ir-block.0):274  ; RV32-NEXT:   liveins: $x10, $x11275  ; RV32-NEXT: {{  $}}276  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10277  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)278  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11279  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF280  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)281  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 8 x s1>)282  ; RV32-NEXT:   PseudoRET implicit $v0283  ;284  ; RV64-LABEL: name: insertelement_nxv8i1_2285  ; RV64: bb.1 (%ir-block.0):286  ; RV64-NEXT:   liveins: $x10, $x11287  ; RV64-NEXT: {{  $}}288  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10289  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)290  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11291  ; RV64-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)292  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF293  ; RV64-NEXT:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32)294  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64)295  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 8 x s1>)296  ; RV64-NEXT:   PseudoRET implicit $v0297  %a = insertelement <vscale x 8 x i1> poison, i1 %x, i32 %idx298  ret <vscale x 8 x i1> %a299}300 301define <vscale x 16 x i1> @insertelement_nxv16i1_0() {302  ; RV32-LABEL: name: insertelement_nxv16i1_0303  ; RV32: bb.1 (%ir-block.0):304  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF305  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false306  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15307  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)308  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 16 x s1>)309  ; RV32-NEXT:   PseudoRET implicit $v0310  ;311  ; RV64-LABEL: name: insertelement_nxv16i1_0312  ; RV64: bb.1 (%ir-block.0):313  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF314  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false315  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 15316  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)317  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 16 x s1>)318  ; RV64-NEXT:   PseudoRET implicit $v0319  %a = insertelement <vscale x 16 x i1> poison, i1 0, i32 15320  ret <vscale x 16 x i1> %a321}322 323define <vscale x 16 x i1> @insertelement_nxv16i1_1() {324  ; RV32-LABEL: name: insertelement_nxv16i1_1325  ; RV32: bb.1 (%ir-block.0):326  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF327  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true328  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0329  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s32)330  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 16 x s1>)331  ; RV32-NEXT:   PseudoRET implicit $v0332  ;333  ; RV64-LABEL: name: insertelement_nxv16i1_1334  ; RV64: bb.1 (%ir-block.0):335  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF336  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 true337  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0338  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s1), [[C1]](s64)339  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 16 x s1>)340  ; RV64-NEXT:   PseudoRET implicit $v0341  %a = insertelement <vscale x 16 x i1> poison, i1 -1, i32 0342  ret <vscale x 16 x i1> %a343}344 345define <vscale x 16 x i1> @insertelement_nxv16i1_2(i1 %x, i32 %idx) {346  ; RV32-LABEL: name: insertelement_nxv16i1_2347  ; RV32: bb.1 (%ir-block.0):348  ; RV32-NEXT:   liveins: $x10, $x11349  ; RV32-NEXT: {{  $}}350  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10351  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)352  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11353  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF354  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[COPY1]](s32)355  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 16 x s1>)356  ; RV32-NEXT:   PseudoRET implicit $v0357  ;358  ; RV64-LABEL: name: insertelement_nxv16i1_2359  ; RV64: bb.1 (%ir-block.0):360  ; RV64-NEXT:   liveins: $x10, $x11361  ; RV64-NEXT: {{  $}}362  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10363  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)364  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11365  ; RV64-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)366  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF367  ; RV64-NEXT:   [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[TRUNC1]](s32)368  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s1>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s1), [[ZEXT]](s64)369  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 16 x s1>)370  ; RV64-NEXT:   PseudoRET implicit $v0371  %a = insertelement <vscale x 16 x i1> poison, i1 %x, i32 %idx372  ret <vscale x 16 x i1> %a373}374 375define <vscale x 4 x i1> @insertelement_nxv4i1_3(<vscale x 4 x i1> %v, i1 %x) {376  ; RV32-LABEL: name: insertelement_nxv4i1_3377  ; RV32: bb.1 (%ir-block.0):378  ; RV32-NEXT:   liveins: $v0, $x10379  ; RV32-NEXT: {{  $}}380  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0381  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x10382  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s32)383  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0384  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s32)385  ; RV32-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)386  ; RV32-NEXT:   PseudoRET implicit $v0387  ;388  ; RV64-LABEL: name: insertelement_nxv4i1_3389  ; RV64: bb.1 (%ir-block.0):390  ; RV64-NEXT:   liveins: $v0, $x10391  ; RV64-NEXT: {{  $}}392  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0393  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x10394  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY1]](s64)395  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0396  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s1), [[C]](s64)397  ; RV64-NEXT:   $v0 = COPY [[IVEC]](<vscale x 4 x s1>)398  ; RV64-NEXT:   PseudoRET implicit $v0399  %a = insertelement <vscale x 4 x i1> %v, i1 %x, i32 0400  ret <vscale x 4 x i1> %a401}402 403define <vscale x 1 x i8> @insertelement_nxv1i8_0() {404  ; RV32-LABEL: name: insertelement_nxv1i8_0405  ; RV32: bb.1 (%ir-block.0):406  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF407  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0408  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0409  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)410  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s8>)411  ; RV32-NEXT:   PseudoRET implicit $v8412  ;413  ; RV64-LABEL: name: insertelement_nxv1i8_0414  ; RV64: bb.1 (%ir-block.0):415  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF416  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0417  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0418  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)419  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s8>)420  ; RV64-NEXT:   PseudoRET implicit $v8421  %a = insertelement <vscale x 1 x i8> poison, i8 0, i32 0422  ret <vscale x 1 x i8> %a423}424 425define <vscale x 1 x i8> @insertelement_nxv1i8_1() {426  ; RV32-LABEL: name: insertelement_nxv1i8_1427  ; RV32: bb.1 (%ir-block.0):428  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF429  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1430  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0431  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)432  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s8>)433  ; RV32-NEXT:   PseudoRET implicit $v8434  ;435  ; RV64-LABEL: name: insertelement_nxv1i8_1436  ; RV64: bb.1 (%ir-block.0):437  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF438  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1439  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0440  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)441  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s8>)442  ; RV64-NEXT:   PseudoRET implicit $v8443  %a = insertelement <vscale x 1 x i8> poison, i8 -1, i32 0444  ret <vscale x 1 x i8> %a445}446 447define <vscale x 1 x i8> @insertelement_nxv1i8_2(i8 %x) {448  ; RV32-LABEL: name: insertelement_nxv1i8_2449  ; RV32: bb.1 (%ir-block.0):450  ; RV32-NEXT:   liveins: $x10451  ; RV32-NEXT: {{  $}}452  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10453  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)454  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF455  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0456  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)457  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s8>)458  ; RV32-NEXT:   PseudoRET implicit $v8459  ;460  ; RV64-LABEL: name: insertelement_nxv1i8_2461  ; RV64: bb.1 (%ir-block.0):462  ; RV64-NEXT:   liveins: $x10463  ; RV64-NEXT: {{  $}}464  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10465  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)466  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF467  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0468  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)469  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s8>)470  ; RV64-NEXT:   PseudoRET implicit $v8471  %a = insertelement <vscale x 1 x i8> poison, i8 %x, i32 0472  ret <vscale x 1 x i8> %a473}474 475define <vscale x 2 x i8> @insertelement_nxv2i8_0() {476  ; RV32-LABEL: name: insertelement_nxv2i8_0477  ; RV32: bb.1 (%ir-block.0):478  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF479  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0480  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0481  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)482  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s8>)483  ; RV32-NEXT:   PseudoRET implicit $v8484  ;485  ; RV64-LABEL: name: insertelement_nxv2i8_0486  ; RV64: bb.1 (%ir-block.0):487  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF488  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0489  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0490  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)491  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s8>)492  ; RV64-NEXT:   PseudoRET implicit $v8493  %a = insertelement <vscale x 2 x i8> poison, i8 0, i32 0494  ret <vscale x 2 x i8> %a495}496 497define <vscale x 2 x i8> @insertelement_nxv2i8_1() {498  ; RV32-LABEL: name: insertelement_nxv2i8_1499  ; RV32: bb.1 (%ir-block.0):500  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF501  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1502  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0503  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)504  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s8>)505  ; RV32-NEXT:   PseudoRET implicit $v8506  ;507  ; RV64-LABEL: name: insertelement_nxv2i8_1508  ; RV64: bb.1 (%ir-block.0):509  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF510  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1511  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0512  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)513  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s8>)514  ; RV64-NEXT:   PseudoRET implicit $v8515  %a = insertelement <vscale x 2 x i8> poison, i8 -1, i32 0516  ret <vscale x 2 x i8> %a517}518 519define <vscale x 2 x i8> @insertelement_nxv2i8_2(i8 %x) {520  ; RV32-LABEL: name: insertelement_nxv2i8_2521  ; RV32: bb.1 (%ir-block.0):522  ; RV32-NEXT:   liveins: $x10523  ; RV32-NEXT: {{  $}}524  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10525  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)526  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF527  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0528  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)529  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s8>)530  ; RV32-NEXT:   PseudoRET implicit $v8531  ;532  ; RV64-LABEL: name: insertelement_nxv2i8_2533  ; RV64: bb.1 (%ir-block.0):534  ; RV64-NEXT:   liveins: $x10535  ; RV64-NEXT: {{  $}}536  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10537  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)538  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF539  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0540  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)541  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s8>)542  ; RV64-NEXT:   PseudoRET implicit $v8543  %a = insertelement <vscale x 2 x i8> poison, i8 %x, i32 0544  ret <vscale x 2 x i8> %a545}546 547define <vscale x 4 x i8> @insertelement_nxv4i8_0() {548  ; RV32-LABEL: name: insertelement_nxv4i8_0549  ; RV32: bb.1 (%ir-block.0):550  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF551  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0552  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0553  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)554  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)555  ; RV32-NEXT:   PseudoRET implicit $v8556  ;557  ; RV64-LABEL: name: insertelement_nxv4i8_0558  ; RV64: bb.1 (%ir-block.0):559  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF560  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0561  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0562  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)563  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)564  ; RV64-NEXT:   PseudoRET implicit $v8565  %a = insertelement <vscale x 4 x i8> poison, i8 0, i32 0566  ret <vscale x 4 x i8> %a567}568 569define <vscale x 4 x i8> @insertelement_nxv4i8_1() {570  ; RV32-LABEL: name: insertelement_nxv4i8_1571  ; RV32: bb.1 (%ir-block.0):572  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF573  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1574  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0575  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)576  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)577  ; RV32-NEXT:   PseudoRET implicit $v8578  ;579  ; RV64-LABEL: name: insertelement_nxv4i8_1580  ; RV64: bb.1 (%ir-block.0):581  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF582  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1583  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0584  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)585  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)586  ; RV64-NEXT:   PseudoRET implicit $v8587  %a = insertelement <vscale x 4 x i8> poison, i8 -1, i32 0588  ret <vscale x 4 x i8> %a589}590 591define <vscale x 4 x i8> @insertelement_nxv4i8_2(i8 %x) {592  ; RV32-LABEL: name: insertelement_nxv4i8_2593  ; RV32: bb.1 (%ir-block.0):594  ; RV32-NEXT:   liveins: $x10595  ; RV32-NEXT: {{  $}}596  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10597  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)598  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF599  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0600  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)601  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)602  ; RV32-NEXT:   PseudoRET implicit $v8603  ;604  ; RV64-LABEL: name: insertelement_nxv4i8_2605  ; RV64: bb.1 (%ir-block.0):606  ; RV64-NEXT:   liveins: $x10607  ; RV64-NEXT: {{  $}}608  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10609  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)610  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF611  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0612  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)613  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)614  ; RV64-NEXT:   PseudoRET implicit $v8615  %a = insertelement <vscale x 4 x i8> poison, i8 %x, i32 0616  ret <vscale x 4 x i8> %a617}618 619define <vscale x 8 x i8> @insertelement_nxv8i8_0() {620  ; RV32-LABEL: name: insertelement_nxv8i8_0621  ; RV32: bb.1 (%ir-block.0):622  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF623  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0624  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0625  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)626  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 8 x s8>)627  ; RV32-NEXT:   PseudoRET implicit $v8628  ;629  ; RV64-LABEL: name: insertelement_nxv8i8_0630  ; RV64: bb.1 (%ir-block.0):631  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF632  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0633  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0634  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)635  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 8 x s8>)636  ; RV64-NEXT:   PseudoRET implicit $v8637  %a = insertelement <vscale x 8 x i8> poison, i8 0, i32 0638  ret <vscale x 8 x i8> %a639}640 641define <vscale x 8 x i8> @insertelement_nxv8i8_1() {642  ; RV32-LABEL: name: insertelement_nxv8i8_1643  ; RV32: bb.1 (%ir-block.0):644  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF645  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1646  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0647  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)648  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 8 x s8>)649  ; RV32-NEXT:   PseudoRET implicit $v8650  ;651  ; RV64-LABEL: name: insertelement_nxv8i8_1652  ; RV64: bb.1 (%ir-block.0):653  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF654  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1655  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0656  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)657  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 8 x s8>)658  ; RV64-NEXT:   PseudoRET implicit $v8659  %a = insertelement <vscale x 8 x i8> poison, i8 -1, i32 0660  ret <vscale x 8 x i8> %a661}662 663define <vscale x 8 x i8> @insertelement_nxv8i8_2(i8 %x) {664  ; RV32-LABEL: name: insertelement_nxv8i8_2665  ; RV32: bb.1 (%ir-block.0):666  ; RV32-NEXT:   liveins: $x10667  ; RV32-NEXT: {{  $}}668  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10669  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)670  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF671  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0672  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s32)673  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 8 x s8>)674  ; RV32-NEXT:   PseudoRET implicit $v8675  ;676  ; RV64-LABEL: name: insertelement_nxv8i8_2677  ; RV64: bb.1 (%ir-block.0):678  ; RV64-NEXT:   liveins: $x10679  ; RV64-NEXT: {{  $}}680  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10681  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)682  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF683  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0684  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[C]](s64)685  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 8 x s8>)686  ; RV64-NEXT:   PseudoRET implicit $v8687  %a = insertelement <vscale x 8 x i8> poison, i8 %x, i32 0688  ret <vscale x 8 x i8> %a689}690 691define <vscale x 16 x i8> @insertelement_nxv16i8_0() {692  ; RV32-LABEL: name: insertelement_nxv16i8_0693  ; RV32: bb.1 (%ir-block.0):694  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF695  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0696  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0697  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)698  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)699  ; RV32-NEXT:   PseudoRET implicit $v8m2700  ;701  ; RV64-LABEL: name: insertelement_nxv16i8_0702  ; RV64: bb.1 (%ir-block.0):703  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF704  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0705  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0706  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)707  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)708  ; RV64-NEXT:   PseudoRET implicit $v8m2709  %a = insertelement <vscale x 16 x i8> poison, i8 0, i64 0710  ret <vscale x 16 x i8> %a711}712 713define <vscale x 16 x i8> @insertelement_nxv16i8_1() {714  ; RV32-LABEL: name: insertelement_nxv16i8_1715  ; RV32: bb.1 (%ir-block.0):716  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF717  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1718  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0719  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s32)720  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)721  ; RV32-NEXT:   PseudoRET implicit $v8m2722  ;723  ; RV64-LABEL: name: insertelement_nxv16i8_1724  ; RV64: bb.1 (%ir-block.0):725  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF726  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1727  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0728  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s8), [[C1]](s64)729  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)730  ; RV64-NEXT:   PseudoRET implicit $v8m2731  %a = insertelement <vscale x 16 x i8> poison, i8 -1, i32 0732  ret <vscale x 16 x i8> %a733}734 735define <vscale x 16 x i8> @insertelement_nxv16i8_2(i8 %x, i64 %idx) {736  ; RV32-LABEL: name: insertelement_nxv16i8_2737  ; RV32: bb.1 (%ir-block.0):738  ; RV32-NEXT:   liveins: $x10, $x11, $x12739  ; RV32-NEXT: {{  $}}740  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10741  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)742  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x11743  ; RV32-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $x12744  ; RV32-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)745  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF746  ; RV32-NEXT:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MV]](s64)747  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[TRUNC1]](s32)748  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)749  ; RV32-NEXT:   PseudoRET implicit $v8m2750  ;751  ; RV64-LABEL: name: insertelement_nxv16i8_2752  ; RV64: bb.1 (%ir-block.0):753  ; RV64-NEXT:   liveins: $x10, $x11754  ; RV64-NEXT: {{  $}}755  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10756  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s64)757  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x11758  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF759  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s8>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s8), [[COPY1]](s64)760  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 16 x s8>)761  ; RV64-NEXT:   PseudoRET implicit $v8m2762  %a = insertelement <vscale x 16 x i8> poison, i8 %x, i64 %idx763  ret <vscale x 16 x i8> %a764}765 766define <vscale x 4 x i8> @insertelement_nxv4i8_3(<vscale x 4 x i8> %v, i8 %x) {767  ; RV32-LABEL: name: insertelement_nxv4i8_3768  ; RV32: bb.1 (%ir-block.0):769  ; RV32-NEXT:   liveins: $v8, $x10770  ; RV32-NEXT: {{  $}}771  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8772  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x10773  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)774  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0775  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s32)776  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)777  ; RV32-NEXT:   PseudoRET implicit $v8778  ;779  ; RV64-LABEL: name: insertelement_nxv4i8_3780  ; RV64: bb.1 (%ir-block.0):781  ; RV64-NEXT:   liveins: $v8, $x10782  ; RV64-NEXT: {{  $}}783  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v8784  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x10785  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s64)786  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0787  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s8), [[C]](s64)788  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s8>)789  ; RV64-NEXT:   PseudoRET implicit $v8790  %a = insertelement <vscale x 4 x i8> %v, i8 %x, i32 0791  ret <vscale x 4 x i8> %a792}793 794define <vscale x 1 x i16> @insertelement_nxv1i16_0() {795  ; RV32-LABEL: name: insertelement_nxv1i16_0796  ; RV32: bb.1 (%ir-block.0):797  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF798  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0799  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0800  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)801  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s16>)802  ; RV32-NEXT:   PseudoRET implicit $v8803  ;804  ; RV64-LABEL: name: insertelement_nxv1i16_0805  ; RV64: bb.1 (%ir-block.0):806  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF807  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0808  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0809  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)810  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s16>)811  ; RV64-NEXT:   PseudoRET implicit $v8812  %a = insertelement <vscale x 1 x i16> poison, i16 0, i32 0813  ret <vscale x 1 x i16> %a814}815 816define <vscale x 1 x i16> @insertelement_nxv1i16_1() {817  ; RV32-LABEL: name: insertelement_nxv1i16_1818  ; RV32: bb.1 (%ir-block.0):819  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF820  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1821  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0822  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)823  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s16>)824  ; RV32-NEXT:   PseudoRET implicit $v8825  ;826  ; RV64-LABEL: name: insertelement_nxv1i16_1827  ; RV64: bb.1 (%ir-block.0):828  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF829  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1830  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0831  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)832  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s16>)833  ; RV64-NEXT:   PseudoRET implicit $v8834  %a = insertelement <vscale x 1 x i16> poison, i16 -1, i32 0835  ret <vscale x 1 x i16> %a836}837 838define <vscale x 1 x i16> @insertelement_nxv1i16_2(i16 %x) {839  ; RV32-LABEL: name: insertelement_nxv1i16_2840  ; RV32: bb.1 (%ir-block.0):841  ; RV32-NEXT:   liveins: $x10842  ; RV32-NEXT: {{  $}}843  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10844  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)845  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF846  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0847  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)848  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s16>)849  ; RV32-NEXT:   PseudoRET implicit $v8850  ;851  ; RV64-LABEL: name: insertelement_nxv1i16_2852  ; RV64: bb.1 (%ir-block.0):853  ; RV64-NEXT:   liveins: $x10854  ; RV64-NEXT: {{  $}}855  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10856  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)857  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF858  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0859  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)860  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s16>)861  ; RV64-NEXT:   PseudoRET implicit $v8862  %a = insertelement <vscale x 1 x i16> poison, i16 %x, i32 0863  ret <vscale x 1 x i16> %a864}865 866define <vscale x 2 x i16> @insertelement_nxv2i16_0() {867  ; RV32-LABEL: name: insertelement_nxv2i16_0868  ; RV32: bb.1 (%ir-block.0):869  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF870  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0871  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1872  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)873  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s16>)874  ; RV32-NEXT:   PseudoRET implicit $v8875  ;876  ; RV64-LABEL: name: insertelement_nxv2i16_0877  ; RV64: bb.1 (%ir-block.0):878  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF879  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0880  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1881  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)882  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s16>)883  ; RV64-NEXT:   PseudoRET implicit $v8884  %a = insertelement <vscale x 2 x i16> poison, i16 0, i64 1885  ret <vscale x 2 x i16> %a886}887 888define <vscale x 2 x i16> @insertelement_nxv2i16_1() {889  ; RV32-LABEL: name: insertelement_nxv2i16_1890  ; RV32: bb.1 (%ir-block.0):891  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF892  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1893  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0894  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)895  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s16>)896  ; RV32-NEXT:   PseudoRET implicit $v8897  ;898  ; RV64-LABEL: name: insertelement_nxv2i16_1899  ; RV64: bb.1 (%ir-block.0):900  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF901  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1902  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0903  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)904  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s16>)905  ; RV64-NEXT:   PseudoRET implicit $v8906  %a = insertelement <vscale x 2 x i16> poison, i16 -1, i32 0907  ret <vscale x 2 x i16> %a908}909 910define <vscale x 2 x i16> @insertelement_nxv2i16_2(i16 %x) {911  ; RV32-LABEL: name: insertelement_nxv2i16_2912  ; RV32: bb.1 (%ir-block.0):913  ; RV32-NEXT:   liveins: $x10914  ; RV32-NEXT: {{  $}}915  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10916  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)917  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF918  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0919  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)920  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s16>)921  ; RV32-NEXT:   PseudoRET implicit $v8922  ;923  ; RV64-LABEL: name: insertelement_nxv2i16_2924  ; RV64: bb.1 (%ir-block.0):925  ; RV64-NEXT:   liveins: $x10926  ; RV64-NEXT: {{  $}}927  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x10928  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)929  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF930  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0931  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)932  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s16>)933  ; RV64-NEXT:   PseudoRET implicit $v8934  %a = insertelement <vscale x 2 x i16> poison, i16 %x, i32 0935  ret <vscale x 2 x i16> %a936}937 938define <vscale x 4 x i16> @insertelement_nxv4i16_0() {939  ; RV32-LABEL: name: insertelement_nxv4i16_0940  ; RV32: bb.1 (%ir-block.0):941  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF942  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0943  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0944  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)945  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)946  ; RV32-NEXT:   PseudoRET implicit $v8947  ;948  ; RV64-LABEL: name: insertelement_nxv4i16_0949  ; RV64: bb.1 (%ir-block.0):950  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF951  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0952  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0953  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)954  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)955  ; RV64-NEXT:   PseudoRET implicit $v8956  %a = insertelement <vscale x 4 x i16> poison, i16 0, i32 0957  ret <vscale x 4 x i16> %a958}959 960define <vscale x 4 x i16> @insertelement_nxv4i16_1() {961  ; RV32-LABEL: name: insertelement_nxv4i16_1962  ; RV32: bb.1 (%ir-block.0):963  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF964  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1965  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0966  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)967  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)968  ; RV32-NEXT:   PseudoRET implicit $v8969  ;970  ; RV64-LABEL: name: insertelement_nxv4i16_1971  ; RV64: bb.1 (%ir-block.0):972  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF973  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1974  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0975  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)976  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)977  ; RV64-NEXT:   PseudoRET implicit $v8978  %a = insertelement <vscale x 4 x i16> poison, i16 -1, i32 0979  ret <vscale x 4 x i16> %a980}981 982define <vscale x 4 x i16> @insertelement_nxv4i16_2(i16 %x) {983  ; RV32-LABEL: name: insertelement_nxv4i16_2984  ; RV32: bb.1 (%ir-block.0):985  ; RV32-NEXT:   liveins: $x10986  ; RV32-NEXT: {{  $}}987  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x10988  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)989  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF990  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0991  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)992  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)993  ; RV32-NEXT:   PseudoRET implicit $v8994  ;995  ; RV64-LABEL: name: insertelement_nxv4i16_2996  ; RV64: bb.1 (%ir-block.0):997  ; RV64-NEXT:   liveins: $x10998  ; RV64-NEXT: {{  $}}999  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101000  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)1001  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF1002  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01003  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)1004  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)1005  ; RV64-NEXT:   PseudoRET implicit $v81006  %a = insertelement <vscale x 4 x i16> poison, i16 %x, i32 01007  ret <vscale x 4 x i16> %a1008}1009 1010define <vscale x 8 x i16> @insertelement_nxv8i16_0() {1011  ; RV32-LABEL: name: insertelement_nxv8i16_01012  ; RV32: bb.1 (%ir-block.0):1013  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF1014  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 01015  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01016  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)1017  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)1018  ; RV32-NEXT:   PseudoRET implicit $v8m21019  ;1020  ; RV64-LABEL: name: insertelement_nxv8i16_01021  ; RV64: bb.1 (%ir-block.0):1022  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF1023  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 01024  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01025  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)1026  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)1027  ; RV64-NEXT:   PseudoRET implicit $v8m21028  %a = insertelement <vscale x 8 x i16> poison, i16 0, i32 01029  ret <vscale x 8 x i16> %a1030}1031 1032define <vscale x 8 x i16> @insertelement_nxv8i16_1() {1033  ; RV32-LABEL: name: insertelement_nxv8i16_11034  ; RV32: bb.1 (%ir-block.0):1035  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF1036  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -11037  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01038  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)1039  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)1040  ; RV32-NEXT:   PseudoRET implicit $v8m21041  ;1042  ; RV64-LABEL: name: insertelement_nxv8i16_11043  ; RV64: bb.1 (%ir-block.0):1044  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF1045  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -11046  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01047  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)1048  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)1049  ; RV64-NEXT:   PseudoRET implicit $v8m21050  %a = insertelement <vscale x 8 x i16> poison, i16 -1, i32 01051  ret <vscale x 8 x i16> %a1052}1053 1054define <vscale x 8 x i16> @insertelement_nxv8i16_2(i16 %x) {1055  ; RV32-LABEL: name: insertelement_nxv8i16_21056  ; RV32: bb.1 (%ir-block.0):1057  ; RV32-NEXT:   liveins: $x101058  ; RV32-NEXT: {{  $}}1059  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101060  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)1061  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF1062  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01063  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)1064  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)1065  ; RV32-NEXT:   PseudoRET implicit $v8m21066  ;1067  ; RV64-LABEL: name: insertelement_nxv8i16_21068  ; RV64: bb.1 (%ir-block.0):1069  ; RV64-NEXT:   liveins: $x101070  ; RV64-NEXT: {{  $}}1071  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101072  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)1073  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF1074  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01075  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)1076  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 8 x s16>)1077  ; RV64-NEXT:   PseudoRET implicit $v8m21078  %a = insertelement <vscale x 8 x i16> poison, i16 %x, i32 01079  ret <vscale x 8 x i16> %a1080}1081 1082define <vscale x 16 x i16> @insertelement_nxv16i16_0() {1083  ; RV32-LABEL: name: insertelement_nxv16i16_01084  ; RV32: bb.1 (%ir-block.0):1085  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF1086  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 01087  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01088  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)1089  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)1090  ; RV32-NEXT:   PseudoRET implicit $v8m41091  ;1092  ; RV64-LABEL: name: insertelement_nxv16i16_01093  ; RV64: bb.1 (%ir-block.0):1094  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF1095  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 01096  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01097  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)1098  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)1099  ; RV64-NEXT:   PseudoRET implicit $v8m41100  %a = insertelement <vscale x 16 x i16> poison, i16 0, i32 01101  ret <vscale x 16 x i16> %a1102}1103 1104define <vscale x 16 x i16> @insertelement_nxv16i16_1() {1105  ; RV32-LABEL: name: insertelement_nxv16i16_11106  ; RV32: bb.1 (%ir-block.0):1107  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF1108  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -11109  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01110  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s32)1111  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)1112  ; RV32-NEXT:   PseudoRET implicit $v8m41113  ;1114  ; RV64-LABEL: name: insertelement_nxv16i16_11115  ; RV64: bb.1 (%ir-block.0):1116  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF1117  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -11118  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01119  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s16), [[C1]](s64)1120  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)1121  ; RV64-NEXT:   PseudoRET implicit $v8m41122  %a = insertelement <vscale x 16 x i16> poison, i16 -1, i32 01123  ret <vscale x 16 x i16> %a1124}1125 1126define <vscale x 16 x i16> @insertelement_nxv16i16_2(i16 %x) {1127  ; RV32-LABEL: name: insertelement_nxv16i16_21128  ; RV32: bb.1 (%ir-block.0):1129  ; RV32-NEXT:   liveins: $x101130  ; RV32-NEXT: {{  $}}1131  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101132  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)1133  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF1134  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01135  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s32)1136  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)1137  ; RV32-NEXT:   PseudoRET implicit $v8m41138  ;1139  ; RV64-LABEL: name: insertelement_nxv16i16_21140  ; RV64: bb.1 (%ir-block.0):1141  ; RV64-NEXT:   liveins: $x101142  ; RV64-NEXT: {{  $}}1143  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101144  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)1145  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF1146  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01147  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s16>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s16), [[C]](s64)1148  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 16 x s16>)1149  ; RV64-NEXT:   PseudoRET implicit $v8m41150  %a = insertelement <vscale x 16 x i16> poison, i16 %x, i32 01151  ret <vscale x 16 x i16> %a1152}1153 1154define <vscale x 4 x i16> @insertelement_nxv4i16(<vscale x 4 x i16> %v, i16 %x) {1155  ; RV32-LABEL: name: insertelement_nxv4i161156  ; RV32: bb.1 (%ir-block.0):1157  ; RV32-NEXT:   liveins: $v8, $x101158  ; RV32-NEXT: {{  $}}1159  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v81160  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x101161  ; RV32-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)1162  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01163  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s32)1164  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)1165  ; RV32-NEXT:   PseudoRET implicit $v81166  ;1167  ; RV64-LABEL: name: insertelement_nxv4i161168  ; RV64: bb.1 (%ir-block.0):1169  ; RV64-NEXT:   liveins: $v8, $x101170  ; RV64-NEXT: {{  $}}1171  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v81172  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x101173  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s64)1174  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01175  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s16), [[C]](s64)1176  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 4 x s16>)1177  ; RV64-NEXT:   PseudoRET implicit $v81178  %a = insertelement <vscale x 4 x i16> %v, i16 %x, i32 01179  ret <vscale x 4 x i16> %a1180}1181 1182define <vscale x 1 x i32> @insertelement_nxv1i32_0() {1183  ; RV32-LABEL: name: insertelement_nxv1i32_01184  ; RV32: bb.1 (%ir-block.0):1185  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF1186  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01187  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)1188  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s32>)1189  ; RV32-NEXT:   PseudoRET implicit $v81190  ;1191  ; RV64-LABEL: name: insertelement_nxv1i32_01192  ; RV64: bb.1 (%ir-block.0):1193  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF1194  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01195  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01196  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1197  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s32>)1198  ; RV64-NEXT:   PseudoRET implicit $v81199  %a = insertelement <vscale x 1 x i32> poison, i32 0, i32 01200  ret <vscale x 1 x i32> %a1201}1202 1203define <vscale x 1 x i32> @insertelement_nxv1i32_1() {1204  ; RV32-LABEL: name: insertelement_nxv1i32_11205  ; RV32: bb.1 (%ir-block.0):1206  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF1207  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11208  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01209  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)1210  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s32>)1211  ; RV32-NEXT:   PseudoRET implicit $v81212  ;1213  ; RV64-LABEL: name: insertelement_nxv1i32_11214  ; RV64: bb.1 (%ir-block.0):1215  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF1216  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11217  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01218  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1219  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s32>)1220  ; RV64-NEXT:   PseudoRET implicit $v81221  %a = insertelement <vscale x 1 x i32> poison, i32 -1, i32 01222  ret <vscale x 1 x i32> %a1223}1224 1225define <vscale x 1 x i32> @insertelement_nxv1i32_2(i32 %x) {1226  ; RV32-LABEL: name: insertelement_nxv1i32_21227  ; RV32: bb.1 (%ir-block.0):1228  ; RV32-NEXT:   liveins: $x101229  ; RV32-NEXT: {{  $}}1230  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101231  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF1232  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01233  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)1234  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s32>)1235  ; RV32-NEXT:   PseudoRET implicit $v81236  ;1237  ; RV64-LABEL: name: insertelement_nxv1i32_21238  ; RV64: bb.1 (%ir-block.0):1239  ; RV64-NEXT:   liveins: $x101240  ; RV64-NEXT: {{  $}}1241  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101242  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1243  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF1244  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01245  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)1246  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s32>)1247  ; RV64-NEXT:   PseudoRET implicit $v81248  %a = insertelement <vscale x 1 x i32> poison, i32 %x, i32 01249  ret <vscale x 1 x i32> %a1250}1251 1252define <vscale x 2 x i32> @insertelement_nxv2i32_0() {1253  ; RV32-LABEL: name: insertelement_nxv2i32_01254  ; RV32: bb.1 (%ir-block.0):1255  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF1256  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01257  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)1258  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s32>)1259  ; RV32-NEXT:   PseudoRET implicit $v81260  ;1261  ; RV64-LABEL: name: insertelement_nxv2i32_01262  ; RV64: bb.1 (%ir-block.0):1263  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF1264  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01265  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01266  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1267  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s32>)1268  ; RV64-NEXT:   PseudoRET implicit $v81269  %a = insertelement <vscale x 2 x i32> poison, i32 0, i32 01270  ret <vscale x 2 x i32> %a1271}1272 1273define <vscale x 2 x i32> @insertelement_nxv2i32_1() {1274  ; RV32-LABEL: name: insertelement_nxv2i32_11275  ; RV32: bb.1 (%ir-block.0):1276  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF1277  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11278  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01279  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)1280  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s32>)1281  ; RV32-NEXT:   PseudoRET implicit $v81282  ;1283  ; RV64-LABEL: name: insertelement_nxv2i32_11284  ; RV64: bb.1 (%ir-block.0):1285  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF1286  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11287  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01288  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1289  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s32>)1290  ; RV64-NEXT:   PseudoRET implicit $v81291  %a = insertelement <vscale x 2 x i32> poison, i32 -1, i32 01292  ret <vscale x 2 x i32> %a1293}1294 1295define <vscale x 2 x i32> @insertelement_nxv2i32_2(i32 %x) {1296  ; RV32-LABEL: name: insertelement_nxv2i32_21297  ; RV32: bb.1 (%ir-block.0):1298  ; RV32-NEXT:   liveins: $x101299  ; RV32-NEXT: {{  $}}1300  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101301  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF1302  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01303  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)1304  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s32>)1305  ; RV32-NEXT:   PseudoRET implicit $v81306  ;1307  ; RV64-LABEL: name: insertelement_nxv2i32_21308  ; RV64: bb.1 (%ir-block.0):1309  ; RV64-NEXT:   liveins: $x101310  ; RV64-NEXT: {{  $}}1311  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101312  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1313  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF1314  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01315  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)1316  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 2 x s32>)1317  ; RV64-NEXT:   PseudoRET implicit $v81318  %a = insertelement <vscale x 2 x i32> poison, i32 %x, i32 01319  ret <vscale x 2 x i32> %a1320}1321 1322define <vscale x 4 x i32> @insertelement_nxv4i32_0() {1323  ; RV32-LABEL: name: insertelement_nxv4i32_01324  ; RV32: bb.1 (%ir-block.0):1325  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF1326  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01327  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)1328  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1329  ; RV32-NEXT:   PseudoRET implicit $v8m21330  ;1331  ; RV64-LABEL: name: insertelement_nxv4i32_01332  ; RV64: bb.1 (%ir-block.0):1333  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF1334  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01335  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01336  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1337  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1338  ; RV64-NEXT:   PseudoRET implicit $v8m21339  %a = insertelement <vscale x 4 x i32> poison, i32 0, i32 01340  ret <vscale x 4 x i32> %a1341}1342 1343define <vscale x 4 x i32> @insertelement_nxv4i32_1() {1344  ; RV32-LABEL: name: insertelement_nxv4i32_11345  ; RV32: bb.1 (%ir-block.0):1346  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF1347  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11348  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01349  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)1350  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1351  ; RV32-NEXT:   PseudoRET implicit $v8m21352  ;1353  ; RV64-LABEL: name: insertelement_nxv4i32_11354  ; RV64: bb.1 (%ir-block.0):1355  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF1356  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11357  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01358  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1359  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1360  ; RV64-NEXT:   PseudoRET implicit $v8m21361  %a = insertelement <vscale x 4 x i32> poison, i32 -1, i32 01362  ret <vscale x 4 x i32> %a1363}1364 1365define <vscale x 4 x i32> @insertelement_nxv4i32_2(i32 %x) {1366  ; RV32-LABEL: name: insertelement_nxv4i32_21367  ; RV32: bb.1 (%ir-block.0):1368  ; RV32-NEXT:   liveins: $x101369  ; RV32-NEXT: {{  $}}1370  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101371  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF1372  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01373  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)1374  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1375  ; RV32-NEXT:   PseudoRET implicit $v8m21376  ;1377  ; RV64-LABEL: name: insertelement_nxv4i32_21378  ; RV64: bb.1 (%ir-block.0):1379  ; RV64-NEXT:   liveins: $x101380  ; RV64-NEXT: {{  $}}1381  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101382  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1383  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF1384  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01385  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)1386  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1387  ; RV64-NEXT:   PseudoRET implicit $v8m21388  %a = insertelement <vscale x 4 x i32> poison, i32 %x, i32 01389  ret <vscale x 4 x i32> %a1390}1391 1392define <vscale x 8 x i32> @insertelement_nxv8i32_0() {1393  ; RV32-LABEL: name: insertelement_nxv8i32_01394  ; RV32: bb.1 (%ir-block.0):1395  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF1396  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01397  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)1398  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)1399  ; RV32-NEXT:   PseudoRET implicit $v8m41400  ;1401  ; RV64-LABEL: name: insertelement_nxv8i32_01402  ; RV64: bb.1 (%ir-block.0):1403  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF1404  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01405  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01406  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1407  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)1408  ; RV64-NEXT:   PseudoRET implicit $v8m41409  %a = insertelement <vscale x 8 x i32> poison, i32 0, i32 01410  ret <vscale x 8 x i32> %a1411}1412 1413define <vscale x 8 x i32> @insertelement_nxv8i32_1() {1414  ; RV32-LABEL: name: insertelement_nxv8i32_11415  ; RV32: bb.1 (%ir-block.0):1416  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF1417  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11418  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01419  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)1420  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)1421  ; RV32-NEXT:   PseudoRET implicit $v8m41422  ;1423  ; RV64-LABEL: name: insertelement_nxv8i32_11424  ; RV64: bb.1 (%ir-block.0):1425  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF1426  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11427  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01428  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1429  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)1430  ; RV64-NEXT:   PseudoRET implicit $v8m41431  %a = insertelement <vscale x 8 x i32> poison, i32 -1, i32 01432  ret <vscale x 8 x i32> %a1433}1434 1435define <vscale x 8 x i32> @insertelement_nxv8i32_2(i32 %x) {1436  ; RV32-LABEL: name: insertelement_nxv8i32_21437  ; RV32: bb.1 (%ir-block.0):1438  ; RV32-NEXT:   liveins: $x101439  ; RV32-NEXT: {{  $}}1440  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101441  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF1442  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01443  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)1444  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)1445  ; RV32-NEXT:   PseudoRET implicit $v8m41446  ;1447  ; RV64-LABEL: name: insertelement_nxv8i32_21448  ; RV64: bb.1 (%ir-block.0):1449  ; RV64-NEXT:   liveins: $x101450  ; RV64-NEXT: {{  $}}1451  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101452  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1453  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF1454  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01455  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)1456  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 8 x s32>)1457  ; RV64-NEXT:   PseudoRET implicit $v8m41458  %a = insertelement <vscale x 8 x i32> poison, i32 %x, i32 01459  ret <vscale x 8 x i32> %a1460}1461 1462define <vscale x 16 x i32> @insertelement_nxv16i32_0() {1463  ; RV32-LABEL: name: insertelement_nxv16i32_01464  ; RV32: bb.1 (%ir-block.0):1465  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF1466  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01467  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C]](s32)1468  ; RV32-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)1469  ; RV32-NEXT:   PseudoRET implicit $v8m81470  ;1471  ; RV64-LABEL: name: insertelement_nxv16i32_01472  ; RV64: bb.1 (%ir-block.0):1473  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF1474  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01475  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01476  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1477  ; RV64-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)1478  ; RV64-NEXT:   PseudoRET implicit $v8m81479  %a = insertelement <vscale x 16 x i32> poison, i32 0, i32 01480  ret <vscale x 16 x i32> %a1481}1482 1483define <vscale x 16 x i32> @insertelement_nxv16i32_1() {1484  ; RV32-LABEL: name: insertelement_nxv16i32_11485  ; RV32: bb.1 (%ir-block.0):1486  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF1487  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11488  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01489  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s32)1490  ; RV32-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)1491  ; RV32-NEXT:   PseudoRET implicit $v8m81492  ;1493  ; RV64-LABEL: name: insertelement_nxv16i32_11494  ; RV64: bb.1 (%ir-block.0):1495  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF1496  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -11497  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01498  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s32), [[C1]](s64)1499  ; RV64-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)1500  ; RV64-NEXT:   PseudoRET implicit $v8m81501  %a = insertelement <vscale x 16 x i32> poison, i32 -1, i32 01502  ret <vscale x 16 x i32> %a1503}1504 1505define <vscale x 16 x i32> @insertelement_nxv16i32_2(i32 %x) {1506  ; RV32-LABEL: name: insertelement_nxv16i32_21507  ; RV32: bb.1 (%ir-block.0):1508  ; RV32-NEXT:   liveins: $x101509  ; RV32-NEXT: {{  $}}1510  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101511  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF1512  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01513  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s32), [[C]](s32)1514  ; RV32-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)1515  ; RV32-NEXT:   PseudoRET implicit $v8m81516  ;1517  ; RV64-LABEL: name: insertelement_nxv16i32_21518  ; RV64: bb.1 (%ir-block.0):1519  ; RV64-NEXT:   liveins: $x101520  ; RV64-NEXT: {{  $}}1521  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101522  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1523  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF1524  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01525  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s32>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s32), [[C]](s64)1526  ; RV64-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 16 x s32>)1527  ; RV64-NEXT:   PseudoRET implicit $v8m81528  %a = insertelement <vscale x 16 x i32> poison, i32 %x, i32 01529  ret <vscale x 16 x i32> %a1530}1531 1532define <vscale x 4 x i32> @insertelement_nxv4i32(<vscale x 4 x i32> %v, i32 %x) {1533  ; RV32-LABEL: name: insertelement_nxv4i321534  ; RV32: bb.1 (%ir-block.0):1535  ; RV32-NEXT:   liveins: $x10, $v8m21536  ; RV32-NEXT: {{  $}}1537  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m21538  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x101539  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01540  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)1541  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1542  ; RV32-NEXT:   PseudoRET implicit $v8m21543  ;1544  ; RV64-LABEL: name: insertelement_nxv4i321545  ; RV64: bb.1 (%ir-block.0):1546  ; RV64-NEXT:   liveins: $x10, $v8m21547  ; RV64-NEXT: {{  $}}1548  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m21549  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x101550  ; RV64-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)1551  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01552  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[TRUNC]](s32), [[C]](s64)1553  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 4 x s32>)1554  ; RV64-NEXT:   PseudoRET implicit $v8m21555  %a = insertelement <vscale x 4 x i32> %v, i32 %x, i32 01556  ret <vscale x 4 x i32> %a1557}1558 1559define <vscale x 1 x i64> @insertelement_nxv1i64_0() {1560  ; RV32-LABEL: name: insertelement_nxv1i64_01561  ; RV32: bb.1 (%ir-block.0):1562  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF1563  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01564  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01565  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1566  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s64>)1567  ; RV32-NEXT:   PseudoRET implicit $v81568  ;1569  ; RV64-LABEL: name: insertelement_nxv1i64_01570  ; RV64: bb.1 (%ir-block.0):1571  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF1572  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01573  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)1574  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s64>)1575  ; RV64-NEXT:   PseudoRET implicit $v81576  %a = insertelement <vscale x 1 x i64> poison, i64 0, i32 01577  ret <vscale x 1 x i64> %a1578}1579 1580define <vscale x 1 x i64> @insertelement_nxv1i64_1() {1581  ; RV32-LABEL: name: insertelement_nxv1i64_11582  ; RV32: bb.1 (%ir-block.0):1583  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF1584  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11585  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01586  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1587  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s64>)1588  ; RV32-NEXT:   PseudoRET implicit $v81589  ;1590  ; RV64-LABEL: name: insertelement_nxv1i64_11591  ; RV64: bb.1 (%ir-block.0):1592  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF1593  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11594  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01595  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)1596  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s64>)1597  ; RV64-NEXT:   PseudoRET implicit $v81598  %a = insertelement <vscale x 1 x i64> poison, i64 -1, i32 01599  ret <vscale x 1 x i64> %a1600}1601 1602define <vscale x 1 x i64> @insertelement_nxv1i64_2(i64 %x) {1603  ; RV32-LABEL: name: insertelement_nxv1i64_21604  ; RV32: bb.1 (%ir-block.0):1605  ; RV32-NEXT:   liveins: $x10, $x111606  ; RV32-NEXT: {{  $}}1607  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101608  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x111609  ; RV32-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1610  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF1611  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01612  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)1613  ; RV32-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s64>)1614  ; RV32-NEXT:   PseudoRET implicit $v81615  ;1616  ; RV64-LABEL: name: insertelement_nxv1i64_21617  ; RV64: bb.1 (%ir-block.0):1618  ; RV64-NEXT:   liveins: $x101619  ; RV64-NEXT: {{  $}}1620  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101621  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF1622  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01623  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 1 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)1624  ; RV64-NEXT:   $v8 = COPY [[IVEC]](<vscale x 1 x s64>)1625  ; RV64-NEXT:   PseudoRET implicit $v81626  %a = insertelement <vscale x 1 x i64> poison, i64 %x, i32 01627  ret <vscale x 1 x i64> %a1628}1629 1630define <vscale x 2 x i64> @insertelement_nxv2i64_0() {1631  ; RV32-LABEL: name: insertelement_nxv2i64_01632  ; RV32: bb.1 (%ir-block.0):1633  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF1634  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01635  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01636  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1637  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)1638  ; RV32-NEXT:   PseudoRET implicit $v8m21639  ;1640  ; RV64-LABEL: name: insertelement_nxv2i64_01641  ; RV64: bb.1 (%ir-block.0):1642  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF1643  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01644  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)1645  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)1646  ; RV64-NEXT:   PseudoRET implicit $v8m21647  %a = insertelement <vscale x 2 x i64> poison, i64 0, i32 01648  ret <vscale x 2 x i64> %a1649}1650 1651define <vscale x 2 x i64> @insertelement_nxv2i64_1() {1652  ; RV32-LABEL: name: insertelement_nxv2i64_11653  ; RV32: bb.1 (%ir-block.0):1654  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF1655  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11656  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01657  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1658  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)1659  ; RV32-NEXT:   PseudoRET implicit $v8m21660  ;1661  ; RV64-LABEL: name: insertelement_nxv2i64_11662  ; RV64: bb.1 (%ir-block.0):1663  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF1664  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11665  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01666  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)1667  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)1668  ; RV64-NEXT:   PseudoRET implicit $v8m21669  %a = insertelement <vscale x 2 x i64> poison, i64 -1, i32 01670  ret <vscale x 2 x i64> %a1671}1672 1673define <vscale x 2 x i64> @insertelement_nxv2i64_2(i64 %x) {1674  ; RV32-LABEL: name: insertelement_nxv2i64_21675  ; RV32: bb.1 (%ir-block.0):1676  ; RV32-NEXT:   liveins: $x10, $x111677  ; RV32-NEXT: {{  $}}1678  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101679  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x111680  ; RV32-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1681  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF1682  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01683  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)1684  ; RV32-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)1685  ; RV32-NEXT:   PseudoRET implicit $v8m21686  ;1687  ; RV64-LABEL: name: insertelement_nxv2i64_21688  ; RV64: bb.1 (%ir-block.0):1689  ; RV64-NEXT:   liveins: $x101690  ; RV64-NEXT: {{  $}}1691  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101692  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF1693  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01694  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)1695  ; RV64-NEXT:   $v8m2 = COPY [[IVEC]](<vscale x 2 x s64>)1696  ; RV64-NEXT:   PseudoRET implicit $v8m21697  %a = insertelement <vscale x 2 x i64> poison, i64 %x, i32 01698  ret <vscale x 2 x i64> %a1699}1700 1701define <vscale x 4 x i64> @insertelement_nxv4i64_0() {1702  ; RV32-LABEL: name: insertelement_nxv4i64_01703  ; RV32: bb.1 (%ir-block.0):1704  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF1705  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01706  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01707  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1708  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1709  ; RV32-NEXT:   PseudoRET implicit $v8m41710  ;1711  ; RV64-LABEL: name: insertelement_nxv4i64_01712  ; RV64: bb.1 (%ir-block.0):1713  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF1714  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01715  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)1716  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1717  ; RV64-NEXT:   PseudoRET implicit $v8m41718  %a = insertelement <vscale x 4 x i64> poison, i64 0, i32 01719  ret <vscale x 4 x i64> %a1720}1721 1722define <vscale x 4 x i64> @insertelement_nxv4i64_1() {1723  ; RV32-LABEL: name: insertelement_nxv4i64_11724  ; RV32: bb.1 (%ir-block.0):1725  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF1726  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11727  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01728  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1729  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1730  ; RV32-NEXT:   PseudoRET implicit $v8m41731  ;1732  ; RV64-LABEL: name: insertelement_nxv4i64_11733  ; RV64: bb.1 (%ir-block.0):1734  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF1735  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11736  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01737  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)1738  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1739  ; RV64-NEXT:   PseudoRET implicit $v8m41740  %a = insertelement <vscale x 4 x i64> poison, i64 -1, i32 01741  ret <vscale x 4 x i64> %a1742}1743 1744define <vscale x 4 x i64> @insertelement_nxv4i64_2(i64 %x) {1745  ; RV32-LABEL: name: insertelement_nxv4i64_21746  ; RV32: bb.1 (%ir-block.0):1747  ; RV32-NEXT:   liveins: $x10, $x111748  ; RV32-NEXT: {{  $}}1749  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101750  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x111751  ; RV32-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1752  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF1753  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01754  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)1755  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1756  ; RV32-NEXT:   PseudoRET implicit $v8m41757  ;1758  ; RV64-LABEL: name: insertelement_nxv4i64_21759  ; RV64: bb.1 (%ir-block.0):1760  ; RV64-NEXT:   liveins: $x101761  ; RV64-NEXT: {{  $}}1762  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101763  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF1764  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01765  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)1766  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1767  ; RV64-NEXT:   PseudoRET implicit $v8m41768  %a = insertelement <vscale x 4 x i64> poison, i64 %x, i32 01769  ret <vscale x 4 x i64> %a1770}1771 1772define <vscale x 8 x i64> @insertelement_nxv8i64_0() {1773  ; RV32-LABEL: name: insertelement_nxv8i64_01774  ; RV32: bb.1 (%ir-block.0):1775  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF1776  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01777  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01778  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1779  ; RV32-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)1780  ; RV32-NEXT:   PseudoRET implicit $v8m81781  ;1782  ; RV64-LABEL: name: insertelement_nxv8i64_01783  ; RV64: bb.1 (%ir-block.0):1784  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF1785  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01786  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)1787  ; RV64-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)1788  ; RV64-NEXT:   PseudoRET implicit $v8m81789  %a = insertelement <vscale x 8 x i64> poison, i64 0, i32 01790  ret <vscale x 8 x i64> %a1791}1792 1793define <vscale x 8 x i64> @insertelement_nxv8i64_1() {1794  ; RV32-LABEL: name: insertelement_nxv8i64_11795  ; RV32: bb.1 (%ir-block.0):1796  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF1797  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11798  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01799  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1800  ; RV32-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)1801  ; RV32-NEXT:   PseudoRET implicit $v8m81802  ;1803  ; RV64-LABEL: name: insertelement_nxv8i64_11804  ; RV64: bb.1 (%ir-block.0):1805  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF1806  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11807  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01808  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)1809  ; RV64-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)1810  ; RV64-NEXT:   PseudoRET implicit $v8m81811  %a = insertelement <vscale x 8 x i64> poison, i64 -1, i32 01812  ret <vscale x 8 x i64> %a1813}1814 1815define <vscale x 8 x i64> @insertelement_nxv8i64_2(i64 %x) {1816  ; RV32-LABEL: name: insertelement_nxv8i64_21817  ; RV32: bb.1 (%ir-block.0):1818  ; RV32-NEXT:   liveins: $x10, $x111819  ; RV32-NEXT: {{  $}}1820  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101821  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x111822  ; RV32-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1823  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF1824  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01825  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)1826  ; RV32-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)1827  ; RV32-NEXT:   PseudoRET implicit $v8m81828  ;1829  ; RV64-LABEL: name: insertelement_nxv8i64_21830  ; RV64: bb.1 (%ir-block.0):1831  ; RV64-NEXT:   liveins: $x101832  ; RV64-NEXT: {{  $}}1833  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101834  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF1835  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01836  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)1837  ; RV64-NEXT:   $v8m8 = COPY [[IVEC]](<vscale x 8 x s64>)1838  ; RV64-NEXT:   PseudoRET implicit $v8m81839  %a = insertelement <vscale x 8 x i64> poison, i64 %x, i32 01840  ret <vscale x 8 x i64> %a1841}1842 1843define <vscale x 16 x i64> @insertelement_nxv16i64_0() {1844  ; RV32-LABEL: name: insertelement_nxv16i64_01845  ; RV32: bb.1 (%ir-block.0):1846  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF1847  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01848  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01849  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1850  ; RV32-NEXT:   [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>)1851  ; RV32-NEXT:   $v8m8 = COPY [[UV]](<vscale x 8 x s64>)1852  ; RV32-NEXT:   $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)1853  ; RV32-NEXT:   PseudoRET implicit $v8m8, implicit $v16m81854  ;1855  ; RV64-LABEL: name: insertelement_nxv16i64_01856  ; RV64: bb.1 (%ir-block.0):1857  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF1858  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01859  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C]](s64)1860  ; RV64-NEXT:   [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>)1861  ; RV64-NEXT:   $v8m8 = COPY [[UV]](<vscale x 8 x s64>)1862  ; RV64-NEXT:   $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)1863  ; RV64-NEXT:   PseudoRET implicit $v8m8, implicit $v16m81864  %a = insertelement <vscale x 16 x i64> poison, i64 0, i32 01865  ret <vscale x 16 x i64> %a1866}1867 1868define <vscale x 16 x i64> @insertelement_nxv16i64_1() {1869  ; RV32-LABEL: name: insertelement_nxv16i64_11870  ; RV32: bb.1 (%ir-block.0):1871  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF1872  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11873  ; RV32-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 01874  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s32)1875  ; RV32-NEXT:   [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>)1876  ; RV32-NEXT:   $v8m8 = COPY [[UV]](<vscale x 8 x s64>)1877  ; RV32-NEXT:   $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)1878  ; RV32-NEXT:   PseudoRET implicit $v8m8, implicit $v16m81879  ;1880  ; RV64-LABEL: name: insertelement_nxv16i64_11881  ; RV64: bb.1 (%ir-block.0):1882  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF1883  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -11884  ; RV64-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 01885  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[C]](s64), [[C1]](s64)1886  ; RV64-NEXT:   [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>)1887  ; RV64-NEXT:   $v8m8 = COPY [[UV]](<vscale x 8 x s64>)1888  ; RV64-NEXT:   $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)1889  ; RV64-NEXT:   PseudoRET implicit $v8m8, implicit $v16m81890  %a = insertelement <vscale x 16 x i64> poison, i64 -1, i32 01891  ret <vscale x 16 x i64> %a1892}1893 1894define <vscale x 16 x i64> @insertelement_nxv16i64_2(i64 %x) {1895  ; RV32-LABEL: name: insertelement_nxv16i64_21896  ; RV32: bb.1 (%ir-block.0):1897  ; RV32-NEXT:   liveins: $x10, $x111898  ; RV32-NEXT: {{  $}}1899  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $x101900  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x111901  ; RV32-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1902  ; RV32-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF1903  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01904  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV]](s64), [[C]](s32)1905  ; RV32-NEXT:   [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>)1906  ; RV32-NEXT:   $v8m8 = COPY [[UV]](<vscale x 8 x s64>)1907  ; RV32-NEXT:   $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)1908  ; RV32-NEXT:   PseudoRET implicit $v8m8, implicit $v16m81909  ;1910  ; RV64-LABEL: name: insertelement_nxv16i64_21911  ; RV64: bb.1 (%ir-block.0):1912  ; RV64-NEXT:   liveins: $x101913  ; RV64-NEXT: {{  $}}1914  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x101915  ; RV64-NEXT:   [[DEF:%[0-9]+]]:_(<vscale x 16 x s64>) = G_IMPLICIT_DEF1916  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01917  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 16 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[COPY]](s64), [[C]](s64)1918  ; RV64-NEXT:   [[UV:%[0-9]+]]:_(<vscale x 8 x s64>), [[UV1:%[0-9]+]]:_(<vscale x 8 x s64>) = G_UNMERGE_VALUES [[IVEC]](<vscale x 16 x s64>)1919  ; RV64-NEXT:   $v8m8 = COPY [[UV]](<vscale x 8 x s64>)1920  ; RV64-NEXT:   $v16m8 = COPY [[UV1]](<vscale x 8 x s64>)1921  ; RV64-NEXT:   PseudoRET implicit $v8m8, implicit $v16m81922  %a = insertelement <vscale x 16 x i64> poison, i64 %x, i32 01923  ret <vscale x 16 x i64> %a1924}1925 1926define <vscale x 4 x i64> @insertelement_nxv4i64(<vscale x 4 x i64> %v, i64 %x) {1927  ; RV32-LABEL: name: insertelement_nxv4i641928  ; RV32: bb.1 (%ir-block.0):1929  ; RV32-NEXT:   liveins: $x10, $x11, $v8m41930  ; RV32-NEXT: {{  $}}1931  ; RV32-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m41932  ; RV32-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $x101933  ; RV32-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $x111934  ; RV32-NEXT:   [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)1935  ; RV32-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 01936  ; RV32-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], [[MV]](s64), [[C]](s32)1937  ; RV32-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1938  ; RV32-NEXT:   PseudoRET implicit $v8m41939  ;1940  ; RV64-LABEL: name: insertelement_nxv4i641941  ; RV64: bb.1 (%ir-block.0):1942  ; RV64-NEXT:   liveins: $x10, $v8m41943  ; RV64-NEXT: {{  $}}1944  ; RV64-NEXT:   [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m41945  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x101946  ; RV64-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 01947  ; RV64-NEXT:   [[IVEC:%[0-9]+]]:_(<vscale x 4 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s64), [[C]](s64)1948  ; RV64-NEXT:   $v8m4 = COPY [[IVEC]](<vscale x 4 x s64>)1949  ; RV64-NEXT:   PseudoRET implicit $v8m41950  %a = insertelement <vscale x 4 x i64> %v, i64 %x, i32 01951  ret <vscale x 4 x i64> %a1952}1953