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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -global-isel -stop-after=irtranslator \3; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -global-isel -stop-after=irtranslator \5; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s6 7define <vscale x 1 x i1> @splat_zero_nxv1i1() {8 ; RV32-LABEL: name: splat_zero_nxv1i19 ; RV32: bb.1 (%ir-block.0):10 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false11 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[C]](s1)12 ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)13 ; RV32-NEXT: PseudoRET implicit $v014 ;15 ; RV64-LABEL: name: splat_zero_nxv1i116 ; RV64: bb.1 (%ir-block.0):17 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false18 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_SPLAT_VECTOR [[C]](s1)19 ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s1>)20 ; RV64-NEXT: PseudoRET implicit $v021 ret <vscale x 1 x i1> zeroinitializer22}23 24define <vscale x 2 x i1> @splat_zero_nxv2i1() {25 ; RV32-LABEL: name: splat_zero_nxv2i126 ; RV32: bb.1 (%ir-block.0):27 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false28 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[C]](s1)29 ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>)30 ; RV32-NEXT: PseudoRET implicit $v031 ;32 ; RV64-LABEL: name: splat_zero_nxv2i133 ; RV64: bb.1 (%ir-block.0):34 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false35 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s1>) = G_SPLAT_VECTOR [[C]](s1)36 ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s1>)37 ; RV64-NEXT: PseudoRET implicit $v038 ret <vscale x 2 x i1> zeroinitializer39}40 41define <vscale x 4 x i1> @splat_zero_nxv4i1() {42 ; RV32-LABEL: name: splat_zero_nxv4i143 ; RV32: bb.1 (%ir-block.0):44 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false45 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR [[C]](s1)46 ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s1>)47 ; RV32-NEXT: PseudoRET implicit $v048 ;49 ; RV64-LABEL: name: splat_zero_nxv4i150 ; RV64: bb.1 (%ir-block.0):51 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false52 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_SPLAT_VECTOR [[C]](s1)53 ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s1>)54 ; RV64-NEXT: PseudoRET implicit $v055 ret <vscale x 4 x i1> zeroinitializer56}57 58define <vscale x 8 x i1> @splat_zero_nxv8i1() {59 ; RV32-LABEL: name: splat_zero_nxv8i160 ; RV32: bb.1 (%ir-block.0):61 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false62 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR [[C]](s1)63 ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s1>)64 ; RV32-NEXT: PseudoRET implicit $v065 ;66 ; RV64-LABEL: name: splat_zero_nxv8i167 ; RV64: bb.1 (%ir-block.0):68 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false69 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s1>) = G_SPLAT_VECTOR [[C]](s1)70 ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s1>)71 ; RV64-NEXT: PseudoRET implicit $v072 ret <vscale x 8 x i1> zeroinitializer73}74 75define <vscale x 16 x i1> @splat_zero_nxv16i1() {76 ; RV32-LABEL: name: splat_zero_nxv16i177 ; RV32: bb.1 (%ir-block.0):78 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false79 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR [[C]](s1)80 ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s1>)81 ; RV32-NEXT: PseudoRET implicit $v082 ;83 ; RV64-LABEL: name: splat_zero_nxv16i184 ; RV64: bb.1 (%ir-block.0):85 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false86 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s1>) = G_SPLAT_VECTOR [[C]](s1)87 ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s1>)88 ; RV64-NEXT: PseudoRET implicit $v089 ret <vscale x 16 x i1> zeroinitializer90}91 92define <vscale x 32 x i1> @splat_zero_nxv32i1() {93 ; RV32-LABEL: name: splat_zero_nxv32i194 ; RV32: bb.1 (%ir-block.0):95 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false96 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR [[C]](s1)97 ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s1>)98 ; RV32-NEXT: PseudoRET implicit $v099 ;100 ; RV64-LABEL: name: splat_zero_nxv32i1101 ; RV64: bb.1 (%ir-block.0):102 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false103 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s1>) = G_SPLAT_VECTOR [[C]](s1)104 ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s1>)105 ; RV64-NEXT: PseudoRET implicit $v0106 ret <vscale x 32 x i1> zeroinitializer107}108 109define <vscale x 64 x i1> @splat_zero_nxv64i1() {110 ; RV32-LABEL: name: splat_zero_nxv64i1111 ; RV32: bb.1 (%ir-block.0):112 ; RV32-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false113 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR [[C]](s1)114 ; RV32-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 64 x s1>)115 ; RV32-NEXT: PseudoRET implicit $v0116 ;117 ; RV64-LABEL: name: splat_zero_nxv64i1118 ; RV64: bb.1 (%ir-block.0):119 ; RV64-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false120 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s1>) = G_SPLAT_VECTOR [[C]](s1)121 ; RV64-NEXT: $v0 = COPY [[SPLAT_VECTOR]](<vscale x 64 x s1>)122 ; RV64-NEXT: PseudoRET implicit $v0123 ret <vscale x 64 x i1> zeroinitializer124}125 126define <vscale x 1 x i8> @splat_zero_nxv1i8() {127 ; RV32-LABEL: name: splat_zero_nxv1i8128 ; RV32: bb.1 (%ir-block.0):129 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0130 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s8)131 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>)132 ; RV32-NEXT: PseudoRET implicit $v8133 ;134 ; RV64-LABEL: name: splat_zero_nxv1i8135 ; RV64: bb.1 (%ir-block.0):136 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0137 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s8)138 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>)139 ; RV64-NEXT: PseudoRET implicit $v8140 ret <vscale x 1 x i8> zeroinitializer141}142 143define <vscale x 2 x i8> @splat_zero_nxv2i8() {144 ; RV32-LABEL: name: splat_zero_nxv2i8145 ; RV32: bb.1 (%ir-block.0):146 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0147 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s8)148 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>)149 ; RV32-NEXT: PseudoRET implicit $v8150 ;151 ; RV64-LABEL: name: splat_zero_nxv2i8152 ; RV64: bb.1 (%ir-block.0):153 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0154 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s8)155 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>)156 ; RV64-NEXT: PseudoRET implicit $v8157 ret <vscale x 2 x i8> zeroinitializer158}159 160define <vscale x 4 x i8> @splat_zero_nxv4i8() {161 ; RV32-LABEL: name: splat_zero_nxv4i8162 ; RV32: bb.1 (%ir-block.0):163 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0164 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s8)165 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>)166 ; RV32-NEXT: PseudoRET implicit $v8167 ;168 ; RV64-LABEL: name: splat_zero_nxv4i8169 ; RV64: bb.1 (%ir-block.0):170 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0171 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s8)172 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>)173 ; RV64-NEXT: PseudoRET implicit $v8174 ret <vscale x 4 x i8> zeroinitializer175}176 177define <vscale x 8 x i8> @splat_zero_nxv8i8() {178 ; RV32-LABEL: name: splat_zero_nxv8i8179 ; RV32: bb.1 (%ir-block.0):180 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0181 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s8)182 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>)183 ; RV32-NEXT: PseudoRET implicit $v8184 ;185 ; RV64-LABEL: name: splat_zero_nxv8i8186 ; RV64: bb.1 (%ir-block.0):187 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0188 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s8)189 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>)190 ; RV64-NEXT: PseudoRET implicit $v8191 ret <vscale x 8 x i8> zeroinitializer192}193 194define <vscale x 16 x i8> @splat_zero_nxv16i8() {195 ; RV32-LABEL: name: splat_zero_nxv16i8196 ; RV32: bb.1 (%ir-block.0):197 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0198 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s8)199 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>)200 ; RV32-NEXT: PseudoRET implicit $v8m2201 ;202 ; RV64-LABEL: name: splat_zero_nxv16i8203 ; RV64: bb.1 (%ir-block.0):204 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0205 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s8)206 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>)207 ; RV64-NEXT: PseudoRET implicit $v8m2208 ret <vscale x 16 x i8> zeroinitializer209}210 211define <vscale x 32 x i8> @splat_zero_nxv32i8() {212 ; RV32-LABEL: name: splat_zero_nxv32i8213 ; RV32: bb.1 (%ir-block.0):214 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0215 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s8)216 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s8>)217 ; RV32-NEXT: PseudoRET implicit $v8m4218 ;219 ; RV64-LABEL: name: splat_zero_nxv32i8220 ; RV64: bb.1 (%ir-block.0):221 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0222 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s8)223 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s8>)224 ; RV64-NEXT: PseudoRET implicit $v8m4225 ret <vscale x 32 x i8> zeroinitializer226}227 228define <vscale x 64 x i8> @splat_zero_nxv64i8() {229 ; RV32-LABEL: name: splat_zero_nxv64i8230 ; RV32: bb.1 (%ir-block.0):231 ; RV32-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0232 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s8)233 ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 64 x s8>)234 ; RV32-NEXT: PseudoRET implicit $v8m8235 ;236 ; RV64-LABEL: name: splat_zero_nxv64i8237 ; RV64: bb.1 (%ir-block.0):238 ; RV64-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 0239 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s8)240 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 64 x s8>)241 ; RV64-NEXT: PseudoRET implicit $v8m8242 ret <vscale x 64 x i8> zeroinitializer243}244 245define <vscale x 1 x i16> @splat_zero_nxv1i16() {246 ; RV32-LABEL: name: splat_zero_nxv1i16247 ; RV32: bb.1 (%ir-block.0):248 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0249 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s16)250 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)251 ; RV32-NEXT: PseudoRET implicit $v8252 ;253 ; RV64-LABEL: name: splat_zero_nxv1i16254 ; RV64: bb.1 (%ir-block.0):255 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0256 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s16)257 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)258 ; RV64-NEXT: PseudoRET implicit $v8259 ret <vscale x 1 x i16> zeroinitializer260}261 262define <vscale x 2 x i16> @splat_zero_nxv2i16() {263 ; RV32-LABEL: name: splat_zero_nxv2i16264 ; RV32: bb.1 (%ir-block.0):265 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0266 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s16)267 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)268 ; RV32-NEXT: PseudoRET implicit $v8269 ;270 ; RV64-LABEL: name: splat_zero_nxv2i16271 ; RV64: bb.1 (%ir-block.0):272 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0273 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s16)274 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)275 ; RV64-NEXT: PseudoRET implicit $v8276 ret <vscale x 2 x i16> zeroinitializer277}278 279define <vscale x 4 x i16> @splat_zero_nxv4i16() {280 ; RV32-LABEL: name: splat_zero_nxv4i16281 ; RV32: bb.1 (%ir-block.0):282 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0283 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s16)284 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)285 ; RV32-NEXT: PseudoRET implicit $v8286 ;287 ; RV64-LABEL: name: splat_zero_nxv4i16288 ; RV64: bb.1 (%ir-block.0):289 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0290 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s16)291 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)292 ; RV64-NEXT: PseudoRET implicit $v8293 ret <vscale x 4 x i16> zeroinitializer294}295 296define <vscale x 8 x i16> @splat_zero_nxv8i16() {297 ; RV32-LABEL: name: splat_zero_nxv8i16298 ; RV32: bb.1 (%ir-block.0):299 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0300 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s16)301 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)302 ; RV32-NEXT: PseudoRET implicit $v8m2303 ;304 ; RV64-LABEL: name: splat_zero_nxv8i16305 ; RV64: bb.1 (%ir-block.0):306 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0307 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s16)308 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)309 ; RV64-NEXT: PseudoRET implicit $v8m2310 ret <vscale x 8 x i16> zeroinitializer311}312 313define <vscale x 16 x i16> @splat_zero_nxv16i16() {314 ; RV32-LABEL: name: splat_zero_nxv16i16315 ; RV32: bb.1 (%ir-block.0):316 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0317 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s16)318 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)319 ; RV32-NEXT: PseudoRET implicit $v8m4320 ;321 ; RV64-LABEL: name: splat_zero_nxv16i16322 ; RV64: bb.1 (%ir-block.0):323 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0324 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s16)325 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)326 ; RV64-NEXT: PseudoRET implicit $v8m4327 ret <vscale x 16 x i16> zeroinitializer328}329 330define <vscale x 32 x i16> @splat_zero_nxv32i16() {331 ; RV32-LABEL: name: splat_zero_nxv32i16332 ; RV32: bb.1 (%ir-block.0):333 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0334 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s16)335 ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s16>)336 ; RV32-NEXT: PseudoRET implicit $v8m8337 ;338 ; RV64-LABEL: name: splat_zero_nxv32i16339 ; RV64: bb.1 (%ir-block.0):340 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 0341 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s16)342 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s16>)343 ; RV64-NEXT: PseudoRET implicit $v8m8344 ret <vscale x 32 x i16> zeroinitializer345}346 347define <vscale x 1 x i32> @splat_zero_nxv1i32() {348 ; RV32-LABEL: name: splat_zero_nxv1i32349 ; RV32: bb.1 (%ir-block.0):350 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0351 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32)352 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>)353 ; RV32-NEXT: PseudoRET implicit $v8354 ;355 ; RV64-LABEL: name: splat_zero_nxv1i32356 ; RV64: bb.1 (%ir-block.0):357 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0358 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32)359 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>)360 ; RV64-NEXT: PseudoRET implicit $v8361 ret <vscale x 1 x i32> zeroinitializer362}363 364define <vscale x 2 x i32> @splat_zero_nxv2i32() {365 ; RV32-LABEL: name: splat_zero_nxv2i32366 ; RV32: bb.1 (%ir-block.0):367 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0368 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32)369 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>)370 ; RV32-NEXT: PseudoRET implicit $v8371 ;372 ; RV64-LABEL: name: splat_zero_nxv2i32373 ; RV64: bb.1 (%ir-block.0):374 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0375 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32)376 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>)377 ; RV64-NEXT: PseudoRET implicit $v8378 ret <vscale x 2 x i32> zeroinitializer379}380 381define <vscale x 4 x i32> @splat_zero_nxv4i32() {382 ; RV32-LABEL: name: splat_zero_nxv4i32383 ; RV32: bb.1 (%ir-block.0):384 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0385 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32)386 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>)387 ; RV32-NEXT: PseudoRET implicit $v8m2388 ;389 ; RV64-LABEL: name: splat_zero_nxv4i32390 ; RV64: bb.1 (%ir-block.0):391 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0392 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32)393 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>)394 ; RV64-NEXT: PseudoRET implicit $v8m2395 ret <vscale x 4 x i32> zeroinitializer396}397 398define <vscale x 8 x i32> @splat_zero_nxv8i32() {399 ; RV32-LABEL: name: splat_zero_nxv8i32400 ; RV32: bb.1 (%ir-block.0):401 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0402 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32)403 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>)404 ; RV32-NEXT: PseudoRET implicit $v8m4405 ;406 ; RV64-LABEL: name: splat_zero_nxv8i32407 ; RV64: bb.1 (%ir-block.0):408 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0409 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32)410 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>)411 ; RV64-NEXT: PseudoRET implicit $v8m4412 ret <vscale x 8 x i32> zeroinitializer413}414 415define <vscale x 16 x i32> @splat_zero_nxv16i32() {416 ; RV32-LABEL: name: splat_zero_nxv16i32417 ; RV32: bb.1 (%ir-block.0):418 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0419 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32)420 ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>)421 ; RV32-NEXT: PseudoRET implicit $v8m8422 ;423 ; RV64-LABEL: name: splat_zero_nxv16i32424 ; RV64: bb.1 (%ir-block.0):425 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0426 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32)427 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>)428 ; RV64-NEXT: PseudoRET implicit $v8m8429 ret <vscale x 16 x i32> zeroinitializer430}431 432define <vscale x 1 x i64> @splat_zero_nxv1i64() {433 ; RV32-LABEL: name: splat_zero_nxv1i64434 ; RV32: bb.1 (%ir-block.0):435 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0436 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64)437 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>)438 ; RV32-NEXT: PseudoRET implicit $v8439 ;440 ; RV64-LABEL: name: splat_zero_nxv1i64441 ; RV64: bb.1 (%ir-block.0):442 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0443 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64)444 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>)445 ; RV64-NEXT: PseudoRET implicit $v8446 ret <vscale x 1 x i64> zeroinitializer447}448 449define <vscale x 2 x i64> @splat_zero_nxv2i64() {450 ; RV32-LABEL: name: splat_zero_nxv2i64451 ; RV32: bb.1 (%ir-block.0):452 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0453 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64)454 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>)455 ; RV32-NEXT: PseudoRET implicit $v8m2456 ;457 ; RV64-LABEL: name: splat_zero_nxv2i64458 ; RV64: bb.1 (%ir-block.0):459 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0460 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64)461 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>)462 ; RV64-NEXT: PseudoRET implicit $v8m2463 ret <vscale x 2 x i64> zeroinitializer464}465 466define <vscale x 4 x i64> @splat_zero_nxv4i64() {467 ; RV32-LABEL: name: splat_zero_nxv4i64468 ; RV32: bb.1 (%ir-block.0):469 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0470 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64)471 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>)472 ; RV32-NEXT: PseudoRET implicit $v8m4473 ;474 ; RV64-LABEL: name: splat_zero_nxv4i64475 ; RV64: bb.1 (%ir-block.0):476 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0477 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64)478 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>)479 ; RV64-NEXT: PseudoRET implicit $v8m4480 ret <vscale x 4 x i64> zeroinitializer481}482 483define <vscale x 8 x i64> @splat_zero_nxv8i64() {484 ; RV32-LABEL: name: splat_zero_nxv8i64485 ; RV32: bb.1 (%ir-block.0):486 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0487 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64)488 ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>)489 ; RV32-NEXT: PseudoRET implicit $v8m8490 ;491 ; RV64-LABEL: name: splat_zero_nxv8i64492 ; RV64: bb.1 (%ir-block.0):493 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0494 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64)495 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>)496 ; RV64-NEXT: PseudoRET implicit $v8m8497 ret <vscale x 8 x i64> zeroinitializer498}499 500define <vscale x 1 x half> @splat_zero_nxv1half() {501 ; RV32-LABEL: name: splat_zero_nxv1half502 ; RV32: bb.1 (%ir-block.0):503 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000504 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s16)505 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)506 ; RV32-NEXT: PseudoRET implicit $v8507 ;508 ; RV64-LABEL: name: splat_zero_nxv1half509 ; RV64: bb.1 (%ir-block.0):510 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000511 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s16)512 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)513 ; RV64-NEXT: PseudoRET implicit $v8514 ret <vscale x 1 x half> zeroinitializer515}516 517define <vscale x 2 x half> @splat_zero_nxv2half() {518 ; RV32-LABEL: name: splat_zero_nxv2half519 ; RV32: bb.1 (%ir-block.0):520 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000521 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s16)522 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)523 ; RV32-NEXT: PseudoRET implicit $v8524 ;525 ; RV64-LABEL: name: splat_zero_nxv2half526 ; RV64: bb.1 (%ir-block.0):527 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000528 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s16)529 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)530 ; RV64-NEXT: PseudoRET implicit $v8531 ret <vscale x 2 x half> zeroinitializer532}533 534define <vscale x 4 x half> @splat_zero_nxv4half() {535 ; RV32-LABEL: name: splat_zero_nxv4half536 ; RV32: bb.1 (%ir-block.0):537 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000538 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s16)539 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)540 ; RV32-NEXT: PseudoRET implicit $v8541 ;542 ; RV64-LABEL: name: splat_zero_nxv4half543 ; RV64: bb.1 (%ir-block.0):544 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000545 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s16)546 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)547 ; RV64-NEXT: PseudoRET implicit $v8548 ret <vscale x 4 x half> zeroinitializer549}550 551define <vscale x 8 x half> @splat_zero_nxv8half() {552 ; RV32-LABEL: name: splat_zero_nxv8half553 ; RV32: bb.1 (%ir-block.0):554 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000555 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s16)556 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)557 ; RV32-NEXT: PseudoRET implicit $v8m2558 ;559 ; RV64-LABEL: name: splat_zero_nxv8half560 ; RV64: bb.1 (%ir-block.0):561 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000562 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s16)563 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)564 ; RV64-NEXT: PseudoRET implicit $v8m2565 ret <vscale x 8 x half> zeroinitializer566}567 568define <vscale x 16 x half> @splat_zero_nxv16half() {569 ; RV32-LABEL: name: splat_zero_nxv16half570 ; RV32: bb.1 (%ir-block.0):571 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000572 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s16)573 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)574 ; RV32-NEXT: PseudoRET implicit $v8m4575 ;576 ; RV64-LABEL: name: splat_zero_nxv16half577 ; RV64: bb.1 (%ir-block.0):578 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000579 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s16)580 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)581 ; RV64-NEXT: PseudoRET implicit $v8m4582 ret <vscale x 16 x half> zeroinitializer583}584 585define <vscale x 32 x half> @splat_zero_nxv32half() {586 ; RV32-LABEL: name: splat_zero_nxv32half587 ; RV32: bb.1 (%ir-block.0):588 ; RV32-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000589 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s16)590 ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s16>)591 ; RV32-NEXT: PseudoRET implicit $v8m8592 ;593 ; RV64-LABEL: name: splat_zero_nxv32half594 ; RV64: bb.1 (%ir-block.0):595 ; RV64-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH0000596 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s16)597 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s16>)598 ; RV64-NEXT: PseudoRET implicit $v8m8599 ret <vscale x 32 x half> zeroinitializer600}601 602define <vscale x 1 x float> @splat_zero_nxv1float() {603 ; RV32-LABEL: name: splat_zero_nxv1float604 ; RV32: bb.1 (%ir-block.0):605 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00606 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32)607 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>)608 ; RV32-NEXT: PseudoRET implicit $v8609 ;610 ; RV64-LABEL: name: splat_zero_nxv1float611 ; RV64: bb.1 (%ir-block.0):612 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00613 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32)614 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>)615 ; RV64-NEXT: PseudoRET implicit $v8616 ret <vscale x 1 x float> zeroinitializer617}618 619define <vscale x 2 x float> @splat_zero_nxv2float() {620 ; RV32-LABEL: name: splat_zero_nxv2float621 ; RV32: bb.1 (%ir-block.0):622 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00623 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32)624 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>)625 ; RV32-NEXT: PseudoRET implicit $v8626 ;627 ; RV64-LABEL: name: splat_zero_nxv2float628 ; RV64: bb.1 (%ir-block.0):629 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00630 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32)631 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>)632 ; RV64-NEXT: PseudoRET implicit $v8633 ret <vscale x 2 x float> zeroinitializer634}635 636define <vscale x 4 x float> @splat_zero_nxv4float() {637 ; RV32-LABEL: name: splat_zero_nxv4float638 ; RV32: bb.1 (%ir-block.0):639 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00640 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32)641 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>)642 ; RV32-NEXT: PseudoRET implicit $v8m2643 ;644 ; RV64-LABEL: name: splat_zero_nxv4float645 ; RV64: bb.1 (%ir-block.0):646 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00647 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32)648 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>)649 ; RV64-NEXT: PseudoRET implicit $v8m2650 ret <vscale x 4 x float> zeroinitializer651}652 653define <vscale x 8 x float> @splat_zero_nxv8float() {654 ; RV32-LABEL: name: splat_zero_nxv8float655 ; RV32: bb.1 (%ir-block.0):656 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00657 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32)658 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>)659 ; RV32-NEXT: PseudoRET implicit $v8m4660 ;661 ; RV64-LABEL: name: splat_zero_nxv8float662 ; RV64: bb.1 (%ir-block.0):663 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00664 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32)665 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>)666 ; RV64-NEXT: PseudoRET implicit $v8m4667 ret <vscale x 8 x float> zeroinitializer668}669 670define <vscale x 16 x float> @splat_zero_nxv16float() {671 ; RV32-LABEL: name: splat_zero_nxv16float672 ; RV32: bb.1 (%ir-block.0):673 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00674 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32)675 ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>)676 ; RV32-NEXT: PseudoRET implicit $v8m8677 ;678 ; RV64-LABEL: name: splat_zero_nxv16float679 ; RV64: bb.1 (%ir-block.0):680 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00681 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32)682 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>)683 ; RV64-NEXT: PseudoRET implicit $v8m8684 ret <vscale x 16 x float> zeroinitializer685}686 687define <vscale x 1 x double> @splat_zero_nxv1double() {688 ; RV32-LABEL: name: splat_zero_nxv1double689 ; RV32: bb.1 (%ir-block.0):690 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00691 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64)692 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>)693 ; RV32-NEXT: PseudoRET implicit $v8694 ;695 ; RV64-LABEL: name: splat_zero_nxv1double696 ; RV64: bb.1 (%ir-block.0):697 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00698 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64)699 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>)700 ; RV64-NEXT: PseudoRET implicit $v8701 ret <vscale x 1 x double> zeroinitializer702}703 704define <vscale x 2 x double> @splat_zero_nxv2double() {705 ; RV32-LABEL: name: splat_zero_nxv2double706 ; RV32: bb.1 (%ir-block.0):707 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00708 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64)709 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>)710 ; RV32-NEXT: PseudoRET implicit $v8m2711 ;712 ; RV64-LABEL: name: splat_zero_nxv2double713 ; RV64: bb.1 (%ir-block.0):714 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00715 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64)716 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>)717 ; RV64-NEXT: PseudoRET implicit $v8m2718 ret <vscale x 2 x double> zeroinitializer719}720 721define <vscale x 4 x double> @splat_zero_nxv4double() {722 ; RV32-LABEL: name: splat_zero_nxv4double723 ; RV32: bb.1 (%ir-block.0):724 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00725 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64)726 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>)727 ; RV32-NEXT: PseudoRET implicit $v8m4728 ;729 ; RV64-LABEL: name: splat_zero_nxv4double730 ; RV64: bb.1 (%ir-block.0):731 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00732 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64)733 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>)734 ; RV64-NEXT: PseudoRET implicit $v8m4735 ret <vscale x 4 x double> zeroinitializer736}737 738define <vscale x 8 x double> @splat_zero_nxv8double() {739 ; RV32-LABEL: name: splat_zero_nxv8double740 ; RV32: bb.1 (%ir-block.0):741 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00742 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64)743 ; RV32-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>)744 ; RV32-NEXT: PseudoRET implicit $v8m8745 ;746 ; RV64-LABEL: name: splat_zero_nxv8double747 ; RV64: bb.1 (%ir-block.0):748 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00749 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64)750 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>)751 ; RV64-NEXT: PseudoRET implicit $v8m8752 ret <vscale x 8 x double> zeroinitializer753}754 755define <vscale x 1 x ptr> @splat_zero_nxv1ptr() {756 ; RV32-LABEL: name: splat_zero_nxv1ptr757 ; RV32: bb.1 (%ir-block.0):758 ; RV32-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i32 0759 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x p0>) = G_SPLAT_VECTOR [[C]](p0)760 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x p0>)761 ; RV32-NEXT: PseudoRET implicit $v8762 ;763 ; RV64-LABEL: name: splat_zero_nxv1ptr764 ; RV64: bb.1 (%ir-block.0):765 ; RV64-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0766 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 1 x p0>) = G_SPLAT_VECTOR [[C]](p0)767 ; RV64-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x p0>)768 ; RV64-NEXT: PseudoRET implicit $v8769 ret <vscale x 1 x ptr> zeroinitializer770}771 772define <vscale x 2 x ptr> @splat_zero_nxv2ptr() {773 ; RV32-LABEL: name: splat_zero_nxv2ptr774 ; RV32: bb.1 (%ir-block.0):775 ; RV32-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i32 0776 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x p0>) = G_SPLAT_VECTOR [[C]](p0)777 ; RV32-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x p0>)778 ; RV32-NEXT: PseudoRET implicit $v8779 ;780 ; RV64-LABEL: name: splat_zero_nxv2ptr781 ; RV64: bb.1 (%ir-block.0):782 ; RV64-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0783 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 2 x p0>) = G_SPLAT_VECTOR [[C]](p0)784 ; RV64-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x p0>)785 ; RV64-NEXT: PseudoRET implicit $v8m2786 ret <vscale x 2 x ptr> zeroinitializer787}788 789define <vscale x 4 x ptr> @splat_zero_nxv4ptr() {790 ; RV32-LABEL: name: splat_zero_nxv4ptr791 ; RV32: bb.1 (%ir-block.0):792 ; RV32-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i32 0793 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x p0>) = G_SPLAT_VECTOR [[C]](p0)794 ; RV32-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x p0>)795 ; RV32-NEXT: PseudoRET implicit $v8m2796 ;797 ; RV64-LABEL: name: splat_zero_nxv4ptr798 ; RV64: bb.1 (%ir-block.0):799 ; RV64-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0800 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x p0>) = G_SPLAT_VECTOR [[C]](p0)801 ; RV64-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x p0>)802 ; RV64-NEXT: PseudoRET implicit $v8m4803 ret <vscale x 4 x ptr> zeroinitializer804}805 806define <vscale x 8 x ptr> @splat_zero_nxv8ptr() {807 ; RV32-LABEL: name: splat_zero_nxv8ptr808 ; RV32: bb.1 (%ir-block.0):809 ; RV32-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i32 0810 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x p0>) = G_SPLAT_VECTOR [[C]](p0)811 ; RV32-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x p0>)812 ; RV32-NEXT: PseudoRET implicit $v8m4813 ;814 ; RV64-LABEL: name: splat_zero_nxv8ptr815 ; RV64: bb.1 (%ir-block.0):816 ; RV64-NEXT: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0817 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x p0>) = G_SPLAT_VECTOR [[C]](p0)818 ; RV64-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x p0>)819 ; RV64-NEXT: PseudoRET implicit $v8m8820 ret <vscale x 8 x ptr> zeroinitializer821}822