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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefixes=RV32,ILP32 %s4; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32 %s6; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -target-abi ilp32f \7; RUN: -verify-machineinstrs < %s \8; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32F %s9; RUN: llc -mtriple=riscv32 -global-isel -stop-after=irtranslator -mattr=+d -target-abi ilp32d \10; RUN: -verify-machineinstrs < %s \11; RUN: | FileCheck -check-prefixes=RV32,RV32D-ILP32D %s12; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \13; RUN: | FileCheck -check-prefixes=RV64,LP64 %s14; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -mattr=+d -target-abi lp64f \15; RUN: -verify-machineinstrs < %s \16; RUN: | FileCheck -check-prefixes=RV64,LP64F %s17; RUN: llc -mtriple=riscv64 -global-isel -stop-after=irtranslator -mattr=+d -target-abi lp64d \18; RUN: -verify-machineinstrs < %s \19; RUN: | FileCheck -check-prefixes=RV64,LP64D %s20 21; The same vararg calling convention is used for ilp32/ilp32f/ilp32d and for22; lp64/lp64f/lp64d. Different CHECK lines are required due to slight23; codegen differences due to the way the f64 load operations are lowered and24; because the PseudoCALL specifies the calling convention.25; The nounwind attribute is omitted for some of the tests, to check that CFI26; directives are correctly generated.27 28declare void @notdead(ptr)29 30; Although frontends are recommended to not generate va_arg due to the lack of31; support for aggregate types, we test simple cases here to ensure they are32; lowered correctly33 34define i32 @va1(ptr %fmt, ...) {35 ; RV32-LABEL: name: va136 ; RV32: bb.1 (%ir-block.0):37 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x1738 ; RV32-NEXT: {{ $}}39 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1040 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.141 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 442 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1143 ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)44 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)45 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x1246 ; RV32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)47 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)48 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x1349 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)50 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)51 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x1452 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)53 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)54 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x1555 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)56 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)57 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x1658 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)59 ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)60 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x1761 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)62 ; RV32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)63 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va64 ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)65 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (p0) from %ir.va)66 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 467 ; RV32-NEXT: %20:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s32)68 ; RV32-NEXT: G_STORE %20(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va)69 ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)70 ; RV32-NEXT: $x10 = COPY [[LOAD1]](s32)71 ; RV32-NEXT: PseudoRET implicit $x1072 ;73 ; RV64-LABEL: name: va174 ; RV64: bb.1 (%ir-block.0):75 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x1776 ; RV64-NEXT: {{ $}}77 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1078 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.179 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 880 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1181 ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)82 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)83 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x1284 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)85 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)86 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x1387 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)88 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)89 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x1490 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)91 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)92 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x1593 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)94 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)95 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x1696 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)97 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)98 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x1799 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)100 ; RV64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)101 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va102 ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)103 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (p0) from %ir.va, align 4)104 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4105 ; RV64-NEXT: %20:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s64)106 ; RV64-NEXT: G_STORE %20(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va, align 4)107 ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)108 ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD1]](s32)109 ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)110 ; RV64-NEXT: PseudoRET implicit $x10111 %va = alloca ptr112 call void @llvm.va_start(ptr %va)113 %argp.cur = load ptr, ptr %va, align 4114 %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 4115 store ptr %argp.next, ptr %va, align 4116 %1 = load i32, ptr %argp.cur, align 4117 call void @llvm.va_end(ptr %va)118 ret i32 %1119}120 121; Ensure the adjustment when restoring the stack pointer using the frame122; pointer is correct123define i32 @va1_va_arg_alloca(ptr %fmt, ...) nounwind {124 ; ILP32-LABEL: name: va1_va_arg_alloca125 ; ILP32: bb.1 (%ir-block.0):126 ; ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17127 ; ILP32-NEXT: {{ $}}128 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10129 ; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1130 ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4131 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11132 ; ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)133 ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)134 ; ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12135 ; ILP32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)136 ; ILP32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)137 ; ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13138 ; ILP32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)139 ; ILP32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)140 ; ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14141 ; ILP32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)142 ; ILP32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)143 ; ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15144 ; ILP32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)145 ; ILP32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)146 ; ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16147 ; ILP32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)148 ; ILP32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)149 ; ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17150 ; ILP32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)151 ; ILP32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)152 ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1153 ; ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va154 ; ILP32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)155 ; ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4156 ; ILP32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C1]]157 ; ILP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15158 ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C2]]159 ; ILP32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16160 ; ILP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]161 ; ILP32-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1162 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2163 ; ILP32-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)164 ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10165 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2166 ; ILP32-NEXT: $x10 = COPY [[VAARG]](s32)167 ; ILP32-NEXT: PseudoRET implicit $x10168 ;169 ; RV32D-ILP32-LABEL: name: va1_va_arg_alloca170 ; RV32D-ILP32: bb.1 (%ir-block.0):171 ; RV32D-ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17172 ; RV32D-ILP32-NEXT: {{ $}}173 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10174 ; RV32D-ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1175 ; RV32D-ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4176 ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11177 ; RV32D-ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)178 ; RV32D-ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)179 ; RV32D-ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12180 ; RV32D-ILP32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)181 ; RV32D-ILP32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)182 ; RV32D-ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13183 ; RV32D-ILP32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)184 ; RV32D-ILP32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)185 ; RV32D-ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14186 ; RV32D-ILP32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)187 ; RV32D-ILP32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)188 ; RV32D-ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15189 ; RV32D-ILP32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)190 ; RV32D-ILP32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)191 ; RV32D-ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16192 ; RV32D-ILP32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)193 ; RV32D-ILP32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)194 ; RV32D-ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17195 ; RV32D-ILP32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)196 ; RV32D-ILP32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)197 ; RV32D-ILP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1198 ; RV32D-ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va199 ; RV32D-ILP32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)200 ; RV32D-ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4201 ; RV32D-ILP32-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C1]]202 ; RV32D-ILP32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15203 ; RV32D-ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C2]]204 ; RV32D-ILP32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16205 ; RV32D-ILP32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]206 ; RV32D-ILP32-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1207 ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2208 ; RV32D-ILP32-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)209 ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10210 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2211 ; RV32D-ILP32-NEXT: $x10 = COPY [[VAARG]](s32)212 ; RV32D-ILP32-NEXT: PseudoRET implicit $x10213 ;214 ; RV32D-ILP32F-LABEL: name: va1_va_arg_alloca215 ; RV32D-ILP32F: bb.1 (%ir-block.0):216 ; RV32D-ILP32F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17217 ; RV32D-ILP32F-NEXT: {{ $}}218 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10219 ; RV32D-ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1220 ; RV32D-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4221 ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11222 ; RV32D-ILP32F-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)223 ; RV32D-ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)224 ; RV32D-ILP32F-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12225 ; RV32D-ILP32F-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)226 ; RV32D-ILP32F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)227 ; RV32D-ILP32F-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13228 ; RV32D-ILP32F-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)229 ; RV32D-ILP32F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)230 ; RV32D-ILP32F-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14231 ; RV32D-ILP32F-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)232 ; RV32D-ILP32F-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)233 ; RV32D-ILP32F-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15234 ; RV32D-ILP32F-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)235 ; RV32D-ILP32F-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)236 ; RV32D-ILP32F-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16237 ; RV32D-ILP32F-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)238 ; RV32D-ILP32F-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)239 ; RV32D-ILP32F-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17240 ; RV32D-ILP32F-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)241 ; RV32D-ILP32F-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)242 ; RV32D-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1243 ; RV32D-ILP32F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va244 ; RV32D-ILP32F-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)245 ; RV32D-ILP32F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4246 ; RV32D-ILP32F-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C1]]247 ; RV32D-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15248 ; RV32D-ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C2]]249 ; RV32D-ILP32F-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16250 ; RV32D-ILP32F-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]251 ; RV32D-ILP32F-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1252 ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2253 ; RV32D-ILP32F-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)254 ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10255 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2256 ; RV32D-ILP32F-NEXT: $x10 = COPY [[VAARG]](s32)257 ; RV32D-ILP32F-NEXT: PseudoRET implicit $x10258 ;259 ; RV32D-ILP32D-LABEL: name: va1_va_arg_alloca260 ; RV32D-ILP32D: bb.1 (%ir-block.0):261 ; RV32D-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17262 ; RV32D-ILP32D-NEXT: {{ $}}263 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10264 ; RV32D-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1265 ; RV32D-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4266 ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11267 ; RV32D-ILP32D-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)268 ; RV32D-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)269 ; RV32D-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12270 ; RV32D-ILP32D-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)271 ; RV32D-ILP32D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)272 ; RV32D-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13273 ; RV32D-ILP32D-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)274 ; RV32D-ILP32D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)275 ; RV32D-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14276 ; RV32D-ILP32D-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)277 ; RV32D-ILP32D-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)278 ; RV32D-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15279 ; RV32D-ILP32D-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)280 ; RV32D-ILP32D-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)281 ; RV32D-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16282 ; RV32D-ILP32D-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)283 ; RV32D-ILP32D-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)284 ; RV32D-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17285 ; RV32D-ILP32D-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)286 ; RV32D-ILP32D-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)287 ; RV32D-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1288 ; RV32D-ILP32D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va289 ; RV32D-ILP32D-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)290 ; RV32D-ILP32D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4291 ; RV32D-ILP32D-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[VAARG]], [[C1]]292 ; RV32D-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 15293 ; RV32D-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = nuw G_ADD [[MUL]], [[C2]]294 ; RV32D-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -16295 ; RV32D-ILP32D-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C3]]296 ; RV32D-ILP32D-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s32), 1297 ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2298 ; RV32D-ILP32D-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)299 ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10300 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2301 ; RV32D-ILP32D-NEXT: $x10 = COPY [[VAARG]](s32)302 ; RV32D-ILP32D-NEXT: PseudoRET implicit $x10303 ;304 ; LP64-LABEL: name: va1_va_arg_alloca305 ; LP64: bb.1 (%ir-block.0):306 ; LP64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17307 ; LP64-NEXT: {{ $}}308 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10309 ; LP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1310 ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8311 ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11312 ; LP64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)313 ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)314 ; LP64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12315 ; LP64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)316 ; LP64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)317 ; LP64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13318 ; LP64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)319 ; LP64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)320 ; LP64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14321 ; LP64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)322 ; LP64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)323 ; LP64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15324 ; LP64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)325 ; LP64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)326 ; LP64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16327 ; LP64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)328 ; LP64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)329 ; LP64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17330 ; LP64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)331 ; LP64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)332 ; LP64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1333 ; LP64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va334 ; LP64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)335 ; LP64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4336 ; LP64-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VAARG]](s32)337 ; LP64-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C1]]338 ; LP64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15339 ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C2]]340 ; LP64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16341 ; LP64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C3]]342 ; LP64-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1343 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2344 ; LP64-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)345 ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x10346 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2347 ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)348 ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64)349 ; LP64-NEXT: PseudoRET implicit $x10350 ;351 ; LP64F-LABEL: name: va1_va_arg_alloca352 ; LP64F: bb.1 (%ir-block.0):353 ; LP64F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17354 ; LP64F-NEXT: {{ $}}355 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10356 ; LP64F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1357 ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8358 ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11359 ; LP64F-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)360 ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)361 ; LP64F-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12362 ; LP64F-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)363 ; LP64F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)364 ; LP64F-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13365 ; LP64F-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)366 ; LP64F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)367 ; LP64F-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14368 ; LP64F-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)369 ; LP64F-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)370 ; LP64F-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15371 ; LP64F-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)372 ; LP64F-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)373 ; LP64F-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16374 ; LP64F-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)375 ; LP64F-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)376 ; LP64F-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17377 ; LP64F-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)378 ; LP64F-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)379 ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1380 ; LP64F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va381 ; LP64F-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)382 ; LP64F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4383 ; LP64F-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VAARG]](s32)384 ; LP64F-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C1]]385 ; LP64F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15386 ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C2]]387 ; LP64F-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16388 ; LP64F-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C3]]389 ; LP64F-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1390 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2391 ; LP64F-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)392 ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10393 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2394 ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)395 ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64)396 ; LP64F-NEXT: PseudoRET implicit $x10397 ;398 ; LP64D-LABEL: name: va1_va_arg_alloca399 ; LP64D: bb.1 (%ir-block.0):400 ; LP64D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17401 ; LP64D-NEXT: {{ $}}402 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10403 ; LP64D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1404 ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8405 ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11406 ; LP64D-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)407 ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)408 ; LP64D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12409 ; LP64D-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)410 ; LP64D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)411 ; LP64D-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13412 ; LP64D-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)413 ; LP64D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)414 ; LP64D-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14415 ; LP64D-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)416 ; LP64D-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)417 ; LP64D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15418 ; LP64D-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)419 ; LP64D-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)420 ; LP64D-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16421 ; LP64D-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)422 ; LP64D-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)423 ; LP64D-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17424 ; LP64D-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)425 ; LP64D-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)426 ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1427 ; LP64D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va428 ; LP64D-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)429 ; LP64D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4430 ; LP64D-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[VAARG]](s32)431 ; LP64D-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ZEXT]], [[C1]]432 ; LP64D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 15433 ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s64) = nuw G_ADD [[MUL]], [[C2]]434 ; LP64D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -16435 ; LP64D-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ADD]], [[C3]]436 ; LP64D-NEXT: [[DYN_STACKALLOC:%[0-9]+]]:_(p0) = G_DYN_STACKALLOC [[AND]](s64), 1437 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2438 ; LP64D-NEXT: $x10 = COPY [[DYN_STACKALLOC]](p0)439 ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10440 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2441 ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)442 ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64)443 ; LP64D-NEXT: PseudoRET implicit $x10444 %va = alloca ptr445 call void @llvm.va_start(ptr %va)446 %1 = va_arg ptr %va, i32447 %2 = alloca i8, i32 %1448 call void @notdead(ptr %2)449 call void @llvm.va_end(ptr %va)450 ret i32 %1451}452 453define i32 @va1_va_arg(ptr %fmt, ...) nounwind {454 ; RV32-LABEL: name: va1_va_arg455 ; RV32: bb.1 (%ir-block.0):456 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17457 ; RV32-NEXT: {{ $}}458 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10459 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1460 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4461 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11462 ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)463 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)464 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12465 ; RV32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)466 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)467 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13468 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)469 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)470 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14471 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)472 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)473 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15474 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)475 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)476 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16477 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)478 ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)479 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17480 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)481 ; RV32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)482 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va483 ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)484 ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4485 ; RV32-NEXT: $x10 = COPY [[VAARG]](s32)486 ; RV32-NEXT: PseudoRET implicit $x10487 ;488 ; RV64-LABEL: name: va1_va_arg489 ; RV64: bb.1 (%ir-block.0):490 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17491 ; RV64-NEXT: {{ $}}492 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10493 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1494 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8495 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11496 ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)497 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)498 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12499 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)500 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)501 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13502 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)503 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)504 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14505 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)506 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)507 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15508 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)509 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)510 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16511 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)512 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)513 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17514 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)515 ; RV64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)516 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va517 ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)518 ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 4519 ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)520 ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)521 ; RV64-NEXT: PseudoRET implicit $x10522 %va = alloca ptr523 call void @llvm.va_start(ptr %va)524 %1 = va_arg ptr %va, i32525 call void @llvm.va_end(ptr %va)526 ret i32 %1527}528 529define void @va1_caller() nounwind {530 ; ILP32-LABEL: name: va1_caller531 ; ILP32: bb.1 (%ir-block.0):532 ; ILP32-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF533 ; ILP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00534 ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2535 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2536 ; ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)537 ; ILP32-NEXT: $x10 = COPY [[DEF]](p0)538 ; ILP32-NEXT: $x12 = COPY [[UV]](s32)539 ; ILP32-NEXT: $x13 = COPY [[UV1]](s32)540 ; ILP32-NEXT: $x14 = COPY [[C1]](s32)541 ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10542 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2543 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10544 ; ILP32-NEXT: PseudoRET545 ;546 ; RV32D-ILP32-LABEL: name: va1_caller547 ; RV32D-ILP32: bb.1 (%ir-block.0):548 ; RV32D-ILP32-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF549 ; RV32D-ILP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00550 ; RV32D-ILP32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2551 ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2552 ; RV32D-ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)553 ; RV32D-ILP32-NEXT: $x10 = COPY [[DEF]](p0)554 ; RV32D-ILP32-NEXT: $x12 = COPY [[UV]](s32)555 ; RV32D-ILP32-NEXT: $x13 = COPY [[UV1]](s32)556 ; RV32D-ILP32-NEXT: $x14 = COPY [[C1]](s32)557 ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10558 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2559 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10560 ; RV32D-ILP32-NEXT: PseudoRET561 ;562 ; RV32D-ILP32F-LABEL: name: va1_caller563 ; RV32D-ILP32F: bb.1 (%ir-block.0):564 ; RV32D-ILP32F-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF565 ; RV32D-ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00566 ; RV32D-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2567 ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2568 ; RV32D-ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)569 ; RV32D-ILP32F-NEXT: $x10 = COPY [[DEF]](p0)570 ; RV32D-ILP32F-NEXT: $x12 = COPY [[UV]](s32)571 ; RV32D-ILP32F-NEXT: $x13 = COPY [[UV1]](s32)572 ; RV32D-ILP32F-NEXT: $x14 = COPY [[C1]](s32)573 ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10574 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2575 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10576 ; RV32D-ILP32F-NEXT: PseudoRET577 ;578 ; RV32D-ILP32D-LABEL: name: va1_caller579 ; RV32D-ILP32D: bb.1 (%ir-block.0):580 ; RV32D-ILP32D-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF581 ; RV32D-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00582 ; RV32D-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2583 ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2584 ; RV32D-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)585 ; RV32D-ILP32D-NEXT: $x10 = COPY [[DEF]](p0)586 ; RV32D-ILP32D-NEXT: $x12 = COPY [[UV]](s32)587 ; RV32D-ILP32D-NEXT: $x13 = COPY [[UV1]](s32)588 ; RV32D-ILP32D-NEXT: $x14 = COPY [[C1]](s32)589 ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit $x14, implicit-def $x10590 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2591 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10592 ; RV32D-ILP32D-NEXT: PseudoRET593 ;594 ; LP64-LABEL: name: va1_caller595 ; LP64: bb.1 (%ir-block.0):596 ; LP64-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF597 ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00598 ; LP64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2599 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2600 ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)601 ; LP64-NEXT: $x10 = COPY [[DEF]](p0)602 ; LP64-NEXT: $x11 = COPY [[C]](s64)603 ; LP64-NEXT: $x12 = COPY [[ANYEXT]](s64)604 ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10605 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2606 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10607 ; LP64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)608 ; LP64-NEXT: PseudoRET609 ;610 ; LP64F-LABEL: name: va1_caller611 ; LP64F: bb.1 (%ir-block.0):612 ; LP64F-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF613 ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00614 ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2615 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2616 ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)617 ; LP64F-NEXT: $x10 = COPY [[DEF]](p0)618 ; LP64F-NEXT: $x11 = COPY [[C]](s64)619 ; LP64F-NEXT: $x12 = COPY [[ANYEXT]](s64)620 ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10621 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2622 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10623 ; LP64F-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)624 ; LP64F-NEXT: PseudoRET625 ;626 ; LP64D-LABEL: name: va1_caller627 ; LP64D: bb.1 (%ir-block.0):628 ; LP64D-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF629 ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00630 ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2631 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2632 ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C1]](s32)633 ; LP64D-NEXT: $x10 = COPY [[DEF]](p0)634 ; LP64D-NEXT: $x11 = COPY [[C]](s64)635 ; LP64D-NEXT: $x12 = COPY [[ANYEXT]](s64)636 ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @va1, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x10637 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2638 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10639 ; LP64D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)640 ; LP64D-NEXT: PseudoRET641 %1 = call i32 (ptr, ...) @va1(ptr poison, double 1.0, i32 2)642 ret void643}644 645; Ensure that 2x xlen size+alignment varargs are accessed via an "aligned"646; register pair (where the first register is even-numbered).647 648define i64 @va2(ptr %fmt, ...) nounwind {649 ; RV32-LABEL: name: va2650 ; RV32: bb.1 (%ir-block.0):651 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17652 ; RV32-NEXT: {{ $}}653 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10654 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1655 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4656 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11657 ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)658 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)659 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12660 ; RV32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)661 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)662 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13663 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)664 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)665 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14666 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)667 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)668 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15669 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)670 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)671 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16672 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)673 ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)674 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17675 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)676 ; RV32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)677 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7678 ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8679 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va680 ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)681 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s32) from %ir.va)682 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C1]]683 ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]684 ; RV32-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)685 ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8686 ; RV32-NEXT: %25:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s32)687 ; RV32-NEXT: G_STORE %25(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va)688 ; RV32-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)689 ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)690 ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD1]](s64)691 ; RV32-NEXT: $x10 = COPY [[UV]](s32)692 ; RV32-NEXT: $x11 = COPY [[UV1]](s32)693 ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11694 ;695 ; RV64-LABEL: name: va2696 ; RV64: bb.1 (%ir-block.0):697 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17698 ; RV64-NEXT: {{ $}}699 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10700 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1701 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8702 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11703 ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)704 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)705 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12706 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)707 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)708 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13709 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)710 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)711 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14712 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)713 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)714 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15715 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)716 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)717 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16718 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)719 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)720 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17721 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)722 ; RV64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)723 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7724 ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8725 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va726 ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)727 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s32) from %ir.va)728 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C1]]729 ; RV64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]730 ; RV64-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)731 ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8732 ; RV64-NEXT: %25:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s64)733 ; RV64-NEXT: G_STORE %25(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va, align 4)734 ; RV64-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)735 ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)736 ; RV64-NEXT: $x10 = COPY [[LOAD1]](s64)737 ; RV64-NEXT: PseudoRET implicit $x10738 %va = alloca ptr739 call void @llvm.va_start(ptr %va)740 %argp.cur = load i32, ptr %va, align 4741 %1 = add i32 %argp.cur, 7742 %2 = and i32 %1, -8743 %argp.cur.aligned = inttoptr i32 %1 to ptr744 %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 8745 store ptr %argp.next, ptr %va, align 4746 %3 = inttoptr i32 %2 to ptr747 %4 = load double, ptr %3, align 8748 %5 = bitcast double %4 to i64749 call void @llvm.va_end(ptr %va)750 ret i64 %5751}752 753define i64 @va2_va_arg(ptr %fmt, ...) nounwind {754 ; RV32-LABEL: name: va2_va_arg755 ; RV32: bb.1 (%ir-block.0):756 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17757 ; RV32-NEXT: {{ $}}758 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10759 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1760 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4761 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11762 ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)763 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)764 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12765 ; RV32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)766 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)767 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13768 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)769 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)770 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14771 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)772 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)773 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15774 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)775 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)776 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16777 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)778 ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)779 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17780 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)781 ; RV32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)782 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va783 ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)784 ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX1]](p0), 8785 ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[VAARG]](s64)786 ; RV32-NEXT: $x10 = COPY [[UV]](s32)787 ; RV32-NEXT: $x11 = COPY [[UV1]](s32)788 ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11789 ;790 ; RV64-LABEL: name: va2_va_arg791 ; RV64: bb.1 (%ir-block.0):792 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17793 ; RV64-NEXT: {{ $}}794 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10795 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1796 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8797 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11798 ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)799 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)800 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12801 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)802 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)803 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13804 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)805 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)806 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14807 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)808 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)809 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x15810 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)811 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)812 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x16813 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)814 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)815 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x17816 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)817 ; RV64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)818 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va819 ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)820 ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX1]](p0), 8821 ; RV64-NEXT: $x10 = COPY [[VAARG]](s64)822 ; RV64-NEXT: PseudoRET implicit $x10823 %va = alloca ptr824 call void @llvm.va_start(ptr %va)825 %1 = va_arg ptr %va, double826 call void @llvm.va_end(ptr %va)827 %2 = bitcast double %1 to i64828 ret i64 %2829}830 831define void @va2_caller() nounwind {832 ; ILP32-LABEL: name: va2_caller833 ; ILP32: bb.1 (%ir-block.0):834 ; ILP32-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF835 ; ILP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00836 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2837 ; ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)838 ; ILP32-NEXT: $x10 = COPY [[DEF]](p0)839 ; ILP32-NEXT: $x12 = COPY [[UV]](s32)840 ; ILP32-NEXT: $x13 = COPY [[UV1]](s32)841 ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11842 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2843 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10844 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11845 ; ILP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)846 ; ILP32-NEXT: PseudoRET847 ;848 ; RV32D-ILP32-LABEL: name: va2_caller849 ; RV32D-ILP32: bb.1 (%ir-block.0):850 ; RV32D-ILP32-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF851 ; RV32D-ILP32-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00852 ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2853 ; RV32D-ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)854 ; RV32D-ILP32-NEXT: $x10 = COPY [[DEF]](p0)855 ; RV32D-ILP32-NEXT: $x12 = COPY [[UV]](s32)856 ; RV32D-ILP32-NEXT: $x13 = COPY [[UV1]](s32)857 ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11858 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2859 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10860 ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11861 ; RV32D-ILP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)862 ; RV32D-ILP32-NEXT: PseudoRET863 ;864 ; RV32D-ILP32F-LABEL: name: va2_caller865 ; RV32D-ILP32F: bb.1 (%ir-block.0):866 ; RV32D-ILP32F-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF867 ; RV32D-ILP32F-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00868 ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2869 ; RV32D-ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)870 ; RV32D-ILP32F-NEXT: $x10 = COPY [[DEF]](p0)871 ; RV32D-ILP32F-NEXT: $x12 = COPY [[UV]](s32)872 ; RV32D-ILP32F-NEXT: $x13 = COPY [[UV1]](s32)873 ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11874 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2875 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10876 ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11877 ; RV32D-ILP32F-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)878 ; RV32D-ILP32F-NEXT: PseudoRET879 ;880 ; RV32D-ILP32D-LABEL: name: va2_caller881 ; RV32D-ILP32D: bb.1 (%ir-block.0):882 ; RV32D-ILP32D-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF883 ; RV32D-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00884 ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2885 ; RV32D-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)886 ; RV32D-ILP32D-NEXT: $x10 = COPY [[DEF]](p0)887 ; RV32D-ILP32D-NEXT: $x12 = COPY [[UV]](s32)888 ; RV32D-ILP32D-NEXT: $x13 = COPY [[UV1]](s32)889 ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11890 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2891 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10892 ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11893 ; RV32D-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)894 ; RV32D-ILP32D-NEXT: PseudoRET895 ;896 ; LP64-LABEL: name: va2_caller897 ; LP64: bb.1 (%ir-block.0):898 ; LP64-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF899 ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00900 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2901 ; LP64-NEXT: $x10 = COPY [[DEF]](p0)902 ; LP64-NEXT: $x11 = COPY [[C]](s64)903 ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10904 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2905 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10906 ; LP64-NEXT: PseudoRET907 ;908 ; LP64F-LABEL: name: va2_caller909 ; LP64F: bb.1 (%ir-block.0):910 ; LP64F-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF911 ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00912 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2913 ; LP64F-NEXT: $x10 = COPY [[DEF]](p0)914 ; LP64F-NEXT: $x11 = COPY [[C]](s64)915 ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10916 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2917 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10918 ; LP64F-NEXT: PseudoRET919 ;920 ; LP64D-LABEL: name: va2_caller921 ; LP64D: bb.1 (%ir-block.0):922 ; LP64D-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF923 ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00924 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2925 ; LP64D-NEXT: $x10 = COPY [[DEF]](p0)926 ; LP64D-NEXT: $x11 = COPY [[C]](s64)927 ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @va2, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10928 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2929 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10930 ; LP64D-NEXT: PseudoRET931 %1 = call i64 (ptr, ...) @va2(ptr poison, double 1.000000e+00)932 ret void933}934 935; On RV32, Ensure a named 2*xlen argument is passed in a1 and a2, while the936; vararg double is passed in a4 and a5 (rather than a3 and a4)937 938define i64 @va3(i32 %a, i64 %b, ...) nounwind {939 ; RV32-LABEL: name: va3940 ; RV32: bb.1 (%ir-block.0):941 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17942 ; RV32-NEXT: {{ $}}943 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10944 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11945 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12946 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)947 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1948 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4949 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13950 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)951 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)952 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14953 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)954 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)955 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15956 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)957 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)958 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16959 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)960 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)961 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17962 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)963 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)964 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7965 ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -8966 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va967 ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)968 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s32) from %ir.va)969 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C1]]970 ; RV32-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]971 ; RV32-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)972 ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8973 ; RV32-NEXT: %24:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s32)974 ; RV32-NEXT: G_STORE %24(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va)975 ; RV32-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)976 ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)977 ; RV32-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[MV]], [[LOAD1]]978 ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD1]](s64)979 ; RV32-NEXT: $x10 = COPY [[UV]](s32)980 ; RV32-NEXT: $x11 = COPY [[UV1]](s32)981 ; RV32-NEXT: PseudoRET implicit $x10, implicit $x11982 ;983 ; RV64-LABEL: name: va3984 ; RV64: bb.1 (%ir-block.0):985 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17986 ; RV64-NEXT: {{ $}}987 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10988 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)989 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11990 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0991 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8992 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x12993 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.0, align 16)994 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)995 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x13996 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.0 + 8)997 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)998 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x14999 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.0 + 16, align 16)1000 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)1001 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x151002 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.0 + 24)1003 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)1004 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x161005 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.0 + 32, align 16)1006 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)1007 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x171008 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.0 + 40)1009 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)1010 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 71011 ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -81012 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va1013 ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)1014 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s32) from %ir.va)1015 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[C1]]1016 ; RV64-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C2]]1017 ; RV64-NEXT: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[ADD]](s32)1018 ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 81019 ; RV64-NEXT: %25:_(p0) = nuw nusw inbounds G_PTR_ADD [[INTTOPTR]], [[C3]](s64)1020 ; RV64-NEXT: G_STORE %25(p0), [[FRAME_INDEX1]](p0) :: (store (p0) into %ir.va, align 4)1021 ; RV64-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p0) = G_INTTOPTR [[AND]](s32)1022 ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[INTTOPTR1]](p0) :: (load (s64) from %ir.3)1023 ; RV64-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[LOAD1]]1024 ; RV64-NEXT: $x10 = COPY [[ADD1]](s64)1025 ; RV64-NEXT: PseudoRET implicit $x101026 %va = alloca ptr1027 call void @llvm.va_start(ptr %va)1028 %argp.cur = load i32, ptr %va, align 41029 %1 = add i32 %argp.cur, 71030 %2 = and i32 %1, -81031 %argp.cur.aligned = inttoptr i32 %1 to ptr1032 %argp.next = getelementptr inbounds i8, ptr %argp.cur.aligned, i32 81033 store ptr %argp.next, ptr %va, align 41034 %3 = inttoptr i32 %2 to ptr1035 %4 = load double, ptr %3, align 81036 call void @llvm.va_end(ptr %va)1037 %5 = bitcast double %4 to i641038 %6 = add i64 %b, %51039 ret i64 %61040}1041 1042define i64 @va3_va_arg(i32 %a, i64 %b, ...) nounwind {1043 ; RV32-LABEL: name: va3_va_arg1044 ; RV32: bb.1 (%ir-block.0):1045 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171046 ; RV32-NEXT: {{ $}}1047 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101048 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111049 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x121050 ; RV32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)1051 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11052 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 41053 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x131054 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)1055 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)1056 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x141057 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)1058 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)1059 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x151060 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)1061 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)1062 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x161063 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)1064 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)1065 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x171066 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)1067 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)1068 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va1069 ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)1070 ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX1]](p0), 81071 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[MV]], [[VAARG]]1072 ; RV32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ADD]](s64)1073 ; RV32-NEXT: $x10 = COPY [[UV]](s32)1074 ; RV32-NEXT: $x11 = COPY [[UV1]](s32)1075 ; RV32-NEXT: PseudoRET implicit $x10, implicit $x111076 ;1077 ; RV64-LABEL: name: va3_va_arg1078 ; RV64: bb.1 (%ir-block.0):1079 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171080 ; RV64-NEXT: {{ $}}1081 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101082 ; RV64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1083 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x111084 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.01085 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 81086 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x121087 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.0, align 16)1088 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)1089 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x131090 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.0 + 8)1091 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)1092 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x141093 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.0 + 16, align 16)1094 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)1095 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x151096 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.0 + 24)1097 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)1098 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x161099 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.0 + 32, align 16)1100 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)1101 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x171102 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.0 + 40)1103 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)1104 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va1105 ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)1106 ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s64) = G_VAARG [[FRAME_INDEX1]](p0), 81107 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[VAARG]]1108 ; RV64-NEXT: $x10 = COPY [[ADD]](s64)1109 ; RV64-NEXT: PseudoRET implicit $x101110 %va = alloca ptr1111 call void @llvm.va_start(ptr %va)1112 %1 = va_arg ptr %va, double1113 call void @llvm.va_end(ptr %va)1114 %2 = bitcast double %1 to i641115 %3 = add i64 %b, %21116 ret i64 %31117}1118 1119define void @va3_caller() nounwind {1120 ; ILP32-LABEL: name: va3_caller1121 ; ILP32: bb.1 (%ir-block.0):1122 ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21123 ; ILP32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 11111124 ; ILP32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001125 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21126 ; ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)1127 ; ILP32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)1128 ; ILP32-NEXT: $x10 = COPY [[C]](s32)1129 ; ILP32-NEXT: $x11 = COPY [[UV]](s32)1130 ; ILP32-NEXT: $x12 = COPY [[UV1]](s32)1131 ; ILP32-NEXT: $x14 = COPY [[UV2]](s32)1132 ; ILP32-NEXT: $x15 = COPY [[UV3]](s32)1133 ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x111134 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21135 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101136 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111137 ; ILP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1138 ; ILP32-NEXT: PseudoRET1139 ;1140 ; RV32D-ILP32-LABEL: name: va3_caller1141 ; RV32D-ILP32: bb.1 (%ir-block.0):1142 ; RV32D-ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21143 ; RV32D-ILP32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 11111144 ; RV32D-ILP32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001145 ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21146 ; RV32D-ILP32-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)1147 ; RV32D-ILP32-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)1148 ; RV32D-ILP32-NEXT: $x10 = COPY [[C]](s32)1149 ; RV32D-ILP32-NEXT: $x11 = COPY [[UV]](s32)1150 ; RV32D-ILP32-NEXT: $x12 = COPY [[UV1]](s32)1151 ; RV32D-ILP32-NEXT: $x14 = COPY [[UV2]](s32)1152 ; RV32D-ILP32-NEXT: $x15 = COPY [[UV3]](s32)1153 ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x111154 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21155 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101156 ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111157 ; RV32D-ILP32-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1158 ; RV32D-ILP32-NEXT: PseudoRET1159 ;1160 ; RV32D-ILP32F-LABEL: name: va3_caller1161 ; RV32D-ILP32F: bb.1 (%ir-block.0):1162 ; RV32D-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21163 ; RV32D-ILP32F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 11111164 ; RV32D-ILP32F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001165 ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21166 ; RV32D-ILP32F-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)1167 ; RV32D-ILP32F-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)1168 ; RV32D-ILP32F-NEXT: $x10 = COPY [[C]](s32)1169 ; RV32D-ILP32F-NEXT: $x11 = COPY [[UV]](s32)1170 ; RV32D-ILP32F-NEXT: $x12 = COPY [[UV1]](s32)1171 ; RV32D-ILP32F-NEXT: $x14 = COPY [[UV2]](s32)1172 ; RV32D-ILP32F-NEXT: $x15 = COPY [[UV3]](s32)1173 ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x111174 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21175 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101176 ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111177 ; RV32D-ILP32F-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1178 ; RV32D-ILP32F-NEXT: PseudoRET1179 ;1180 ; RV32D-ILP32D-LABEL: name: va3_caller1181 ; RV32D-ILP32D: bb.1 (%ir-block.0):1182 ; RV32D-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21183 ; RV32D-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 11111184 ; RV32D-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001185 ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21186 ; RV32D-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)1187 ; RV32D-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)1188 ; RV32D-ILP32D-NEXT: $x10 = COPY [[C]](s32)1189 ; RV32D-ILP32D-NEXT: $x11 = COPY [[UV]](s32)1190 ; RV32D-ILP32D-NEXT: $x12 = COPY [[UV1]](s32)1191 ; RV32D-ILP32D-NEXT: $x14 = COPY [[UV2]](s32)1192 ; RV32D-ILP32D-NEXT: $x15 = COPY [[UV3]](s32)1193 ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x14, implicit $x15, implicit-def $x10, implicit-def $x111194 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21195 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101196 ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111197 ; RV32D-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)1198 ; RV32D-ILP32D-NEXT: PseudoRET1199 ;1200 ; LP64-LABEL: name: va3_caller1201 ; LP64: bb.1 (%ir-block.0):1202 ; LP64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21203 ; LP64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 11111204 ; LP64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001205 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21206 ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)1207 ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64)1208 ; LP64-NEXT: $x11 = COPY [[C1]](s64)1209 ; LP64-NEXT: $x12 = COPY [[C2]](s64)1210 ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x101211 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21212 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101213 ; LP64-NEXT: PseudoRET1214 ;1215 ; LP64F-LABEL: name: va3_caller1216 ; LP64F: bb.1 (%ir-block.0):1217 ; LP64F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21218 ; LP64F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 11111219 ; LP64F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001220 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21221 ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)1222 ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64)1223 ; LP64F-NEXT: $x11 = COPY [[C1]](s64)1224 ; LP64F-NEXT: $x12 = COPY [[C2]](s64)1225 ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32f_lp64f, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x101226 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21227 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101228 ; LP64F-NEXT: PseudoRET1229 ;1230 ; LP64D-LABEL: name: va3_caller1231 ; LP64D: bb.1 (%ir-block.0):1232 ; LP64D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 21233 ; LP64D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 11111234 ; LP64D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+001235 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21236 ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)1237 ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64)1238 ; LP64D-NEXT: $x11 = COPY [[C1]](s64)1239 ; LP64D-NEXT: $x12 = COPY [[C2]](s64)1240 ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @va3, csr_ilp32d_lp64d, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit-def $x101241 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21242 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101243 ; LP64D-NEXT: PseudoRET1244 %1 = call i64 (i32, i64, ...) @va3(i32 2, i64 1111, double 2.000000e+00)1245 ret void1246}1247 1248define i32 @va4_va_copy(i32 %argno, ...) nounwind {1249 ; ILP32-LABEL: name: va4_va_copy1250 ; ILP32: bb.1 (%ir-block.0):1251 ; ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171252 ; ILP32-NEXT: {{ $}}1253 ; ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101254 ; ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11255 ; ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 41256 ; ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111257 ; ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)1258 ; ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)1259 ; ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x121260 ; ILP32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)1261 ; ILP32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)1262 ; ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x131263 ; ILP32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)1264 ; ILP32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)1265 ; ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x141266 ; ILP32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)1267 ; ILP32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)1268 ; ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x151269 ; ILP32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)1270 ; ILP32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)1271 ; ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x161272 ; ILP32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)1273 ; ILP32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)1274 ; ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x171275 ; ILP32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)1276 ; ILP32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)1277 ; ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs1278 ; ILP32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs1279 ; ILP32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.vargs)1280 ; ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41281 ; ILP32-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX2]](p0), [[FRAME_INDEX1]](p0)1282 ; ILP32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs)1283 ; ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21284 ; ILP32-NEXT: $x10 = COPY [[LOAD]](p0)1285 ; ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x101286 ; ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21287 ; ILP32-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41288 ; ILP32-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41289 ; ILP32-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41290 ; ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]1291 ; ILP32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]1292 ; ILP32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]1293 ; ILP32-NEXT: $x10 = COPY [[ADD2]](s32)1294 ; ILP32-NEXT: PseudoRET implicit $x101295 ;1296 ; RV32D-ILP32-LABEL: name: va4_va_copy1297 ; RV32D-ILP32: bb.1 (%ir-block.0):1298 ; RV32D-ILP32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171299 ; RV32D-ILP32-NEXT: {{ $}}1300 ; RV32D-ILP32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101301 ; RV32D-ILP32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11302 ; RV32D-ILP32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 41303 ; RV32D-ILP32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111304 ; RV32D-ILP32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)1305 ; RV32D-ILP32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)1306 ; RV32D-ILP32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x121307 ; RV32D-ILP32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)1308 ; RV32D-ILP32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)1309 ; RV32D-ILP32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x131310 ; RV32D-ILP32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)1311 ; RV32D-ILP32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)1312 ; RV32D-ILP32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x141313 ; RV32D-ILP32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)1314 ; RV32D-ILP32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)1315 ; RV32D-ILP32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x151316 ; RV32D-ILP32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)1317 ; RV32D-ILP32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)1318 ; RV32D-ILP32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x161319 ; RV32D-ILP32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)1320 ; RV32D-ILP32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)1321 ; RV32D-ILP32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x171322 ; RV32D-ILP32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)1323 ; RV32D-ILP32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)1324 ; RV32D-ILP32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs1325 ; RV32D-ILP32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs1326 ; RV32D-ILP32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.vargs)1327 ; RV32D-ILP32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41328 ; RV32D-ILP32-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX2]](p0), [[FRAME_INDEX1]](p0)1329 ; RV32D-ILP32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs)1330 ; RV32D-ILP32-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21331 ; RV32D-ILP32-NEXT: $x10 = COPY [[LOAD]](p0)1332 ; RV32D-ILP32-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x101333 ; RV32D-ILP32-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21334 ; RV32D-ILP32-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41335 ; RV32D-ILP32-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41336 ; RV32D-ILP32-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41337 ; RV32D-ILP32-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]1338 ; RV32D-ILP32-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]1339 ; RV32D-ILP32-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]1340 ; RV32D-ILP32-NEXT: $x10 = COPY [[ADD2]](s32)1341 ; RV32D-ILP32-NEXT: PseudoRET implicit $x101342 ;1343 ; RV32D-ILP32F-LABEL: name: va4_va_copy1344 ; RV32D-ILP32F: bb.1 (%ir-block.0):1345 ; RV32D-ILP32F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171346 ; RV32D-ILP32F-NEXT: {{ $}}1347 ; RV32D-ILP32F-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101348 ; RV32D-ILP32F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11349 ; RV32D-ILP32F-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 41350 ; RV32D-ILP32F-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111351 ; RV32D-ILP32F-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)1352 ; RV32D-ILP32F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)1353 ; RV32D-ILP32F-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x121354 ; RV32D-ILP32F-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)1355 ; RV32D-ILP32F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)1356 ; RV32D-ILP32F-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x131357 ; RV32D-ILP32F-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)1358 ; RV32D-ILP32F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)1359 ; RV32D-ILP32F-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x141360 ; RV32D-ILP32F-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)1361 ; RV32D-ILP32F-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)1362 ; RV32D-ILP32F-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x151363 ; RV32D-ILP32F-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)1364 ; RV32D-ILP32F-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)1365 ; RV32D-ILP32F-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x161366 ; RV32D-ILP32F-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)1367 ; RV32D-ILP32F-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)1368 ; RV32D-ILP32F-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x171369 ; RV32D-ILP32F-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)1370 ; RV32D-ILP32F-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)1371 ; RV32D-ILP32F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs1372 ; RV32D-ILP32F-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs1373 ; RV32D-ILP32F-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.vargs)1374 ; RV32D-ILP32F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41375 ; RV32D-ILP32F-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX2]](p0), [[FRAME_INDEX1]](p0)1376 ; RV32D-ILP32F-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs)1377 ; RV32D-ILP32F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21378 ; RV32D-ILP32F-NEXT: $x10 = COPY [[LOAD]](p0)1379 ; RV32D-ILP32F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x101380 ; RV32D-ILP32F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21381 ; RV32D-ILP32F-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41382 ; RV32D-ILP32F-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41383 ; RV32D-ILP32F-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41384 ; RV32D-ILP32F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]1385 ; RV32D-ILP32F-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]1386 ; RV32D-ILP32F-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]1387 ; RV32D-ILP32F-NEXT: $x10 = COPY [[ADD2]](s32)1388 ; RV32D-ILP32F-NEXT: PseudoRET implicit $x101389 ;1390 ; RV32D-ILP32D-LABEL: name: va4_va_copy1391 ; RV32D-ILP32D: bb.1 (%ir-block.0):1392 ; RV32D-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171393 ; RV32D-ILP32D-NEXT: {{ $}}1394 ; RV32D-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101395 ; RV32D-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11396 ; RV32D-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 41397 ; RV32D-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111398 ; RV32D-ILP32D-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)1399 ; RV32D-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)1400 ; RV32D-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x121401 ; RV32D-ILP32D-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)1402 ; RV32D-ILP32D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)1403 ; RV32D-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x131404 ; RV32D-ILP32D-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)1405 ; RV32D-ILP32D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)1406 ; RV32D-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x141407 ; RV32D-ILP32D-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)1408 ; RV32D-ILP32D-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)1409 ; RV32D-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x151410 ; RV32D-ILP32D-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)1411 ; RV32D-ILP32D-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)1412 ; RV32D-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x161413 ; RV32D-ILP32D-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)1414 ; RV32D-ILP32D-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)1415 ; RV32D-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x171416 ; RV32D-ILP32D-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)1417 ; RV32D-ILP32D-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)1418 ; RV32D-ILP32D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs1419 ; RV32D-ILP32D-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs1420 ; RV32D-ILP32D-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.vargs)1421 ; RV32D-ILP32D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41422 ; RV32D-ILP32D-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX2]](p0), [[FRAME_INDEX1]](p0)1423 ; RV32D-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs)1424 ; RV32D-ILP32D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21425 ; RV32D-ILP32D-NEXT: $x10 = COPY [[LOAD]](p0)1426 ; RV32D-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x101427 ; RV32D-ILP32D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21428 ; RV32D-ILP32D-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41429 ; RV32D-ILP32D-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41430 ; RV32D-ILP32D-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41431 ; RV32D-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]1432 ; RV32D-ILP32D-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]1433 ; RV32D-ILP32D-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]1434 ; RV32D-ILP32D-NEXT: $x10 = COPY [[ADD2]](s32)1435 ; RV32D-ILP32D-NEXT: PseudoRET implicit $x101436 ;1437 ; LP64-LABEL: name: va4_va_copy1438 ; LP64: bb.1 (%ir-block.0):1439 ; LP64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171440 ; LP64-NEXT: {{ $}}1441 ; LP64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101442 ; LP64-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1443 ; LP64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11444 ; LP64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 81445 ; LP64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x111446 ; LP64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)1447 ; LP64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)1448 ; LP64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x121449 ; LP64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)1450 ; LP64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)1451 ; LP64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x131452 ; LP64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)1453 ; LP64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)1454 ; LP64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x141455 ; LP64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)1456 ; LP64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)1457 ; LP64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x151458 ; LP64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)1459 ; LP64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)1460 ; LP64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x161461 ; LP64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)1462 ; LP64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)1463 ; LP64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x171464 ; LP64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)1465 ; LP64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)1466 ; LP64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs1467 ; LP64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs1468 ; LP64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.vargs)1469 ; LP64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41470 ; LP64-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX2]](p0), [[FRAME_INDEX1]](p0)1471 ; LP64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4)1472 ; LP64-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21473 ; LP64-NEXT: $x10 = COPY [[LOAD]](p0)1474 ; LP64-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32_lp64, implicit-def $x1, implicit $x101475 ; LP64-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21476 ; LP64-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41477 ; LP64-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41478 ; LP64-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41479 ; LP64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]1480 ; LP64-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]1481 ; LP64-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]1482 ; LP64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD2]](s32)1483 ; LP64-NEXT: $x10 = COPY [[ANYEXT]](s64)1484 ; LP64-NEXT: PseudoRET implicit $x101485 ;1486 ; LP64F-LABEL: name: va4_va_copy1487 ; LP64F: bb.1 (%ir-block.0):1488 ; LP64F-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171489 ; LP64F-NEXT: {{ $}}1490 ; LP64F-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101491 ; LP64F-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1492 ; LP64F-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11493 ; LP64F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 81494 ; LP64F-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x111495 ; LP64F-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)1496 ; LP64F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)1497 ; LP64F-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x121498 ; LP64F-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)1499 ; LP64F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)1500 ; LP64F-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x131501 ; LP64F-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)1502 ; LP64F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)1503 ; LP64F-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x141504 ; LP64F-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)1505 ; LP64F-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)1506 ; LP64F-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x151507 ; LP64F-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)1508 ; LP64F-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)1509 ; LP64F-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x161510 ; LP64F-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)1511 ; LP64F-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)1512 ; LP64F-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x171513 ; LP64F-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)1514 ; LP64F-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)1515 ; LP64F-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs1516 ; LP64F-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs1517 ; LP64F-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.vargs)1518 ; LP64F-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41519 ; LP64F-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX2]](p0), [[FRAME_INDEX1]](p0)1520 ; LP64F-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4)1521 ; LP64F-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21522 ; LP64F-NEXT: $x10 = COPY [[LOAD]](p0)1523 ; LP64F-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32f_lp64f, implicit-def $x1, implicit $x101524 ; LP64F-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21525 ; LP64F-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41526 ; LP64F-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41527 ; LP64F-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41528 ; LP64F-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]1529 ; LP64F-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]1530 ; LP64F-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]1531 ; LP64F-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD2]](s32)1532 ; LP64F-NEXT: $x10 = COPY [[ANYEXT]](s64)1533 ; LP64F-NEXT: PseudoRET implicit $x101534 ;1535 ; LP64D-LABEL: name: va4_va_copy1536 ; LP64D: bb.1 (%ir-block.0):1537 ; LP64D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171538 ; LP64D-NEXT: {{ $}}1539 ; LP64D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101540 ; LP64D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)1541 ; LP64D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11542 ; LP64D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 81543 ; LP64D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x111544 ; LP64D-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)1545 ; LP64D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)1546 ; LP64D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x121547 ; LP64D-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)1548 ; LP64D-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)1549 ; LP64D-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x131550 ; LP64D-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)1551 ; LP64D-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)1552 ; LP64D-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x141553 ; LP64D-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)1554 ; LP64D-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)1555 ; LP64D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x151556 ; LP64D-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)1557 ; LP64D-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)1558 ; LP64D-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x161559 ; LP64D-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)1560 ; LP64D-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)1561 ; LP64D-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x171562 ; LP64D-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)1563 ; LP64D-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)1564 ; LP64D-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.vargs1565 ; LP64D-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.wargs1566 ; LP64D-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.vargs)1567 ; LP64D-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41568 ; LP64D-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.va_copy), [[FRAME_INDEX2]](p0), [[FRAME_INDEX1]](p0)1569 ; LP64D-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.wargs, align 4)1570 ; LP64D-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x21571 ; LP64D-NEXT: $x10 = COPY [[LOAD]](p0)1572 ; LP64D-NEXT: PseudoCALL target-flags(riscv-call) @notdead, csr_ilp32d_lp64d, implicit-def $x1, implicit $x101573 ; LP64D-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x21574 ; LP64D-NEXT: [[VAARG1:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41575 ; LP64D-NEXT: [[VAARG2:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41576 ; LP64D-NEXT: [[VAARG3:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41577 ; LP64D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[VAARG1]], [[VAARG]]1578 ; LP64D-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ADD]], [[VAARG2]]1579 ; LP64D-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[VAARG3]]1580 ; LP64D-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD2]](s32)1581 ; LP64D-NEXT: $x10 = COPY [[ANYEXT]](s64)1582 ; LP64D-NEXT: PseudoRET implicit $x101583 %vargs = alloca ptr1584 %wargs = alloca ptr1585 call void @llvm.va_start(ptr %vargs)1586 %1 = va_arg ptr %vargs, i321587 call void @llvm.va_copy(ptr %wargs, ptr %vargs)1588 %2 = load ptr, ptr %wargs, align 41589 call void @notdead(ptr %2)1590 %3 = va_arg ptr %vargs, i321591 %4 = va_arg ptr %vargs, i321592 %5 = va_arg ptr %vargs, i321593 call void @llvm.va_end(ptr %vargs)1594 call void @llvm.va_end(ptr %wargs)1595 %add1 = add i32 %3, %11596 %add2 = add i32 %add1, %41597 %add3 = add i32 %add2, %51598 ret i32 %add31599}1600 1601; A function with no fixed arguments is not valid C, but can be1602; specified in LLVM IR. We must ensure the vararg save area is1603; still set up correctly.1604 1605define i32 @va6_no_fixed_args(...) nounwind {1606 ; RV32-LABEL: name: va6_no_fixed_args1607 ; RV32: bb.1 (%ir-block.0):1608 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171609 ; RV32-NEXT: {{ $}}1610 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.01611 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 41612 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x101613 ; RV32-NEXT: G_STORE [[COPY]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.0, align 16)1614 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)1615 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111616 ; RV32-NEXT: G_STORE [[COPY1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.0 + 4)1617 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)1618 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x121619 ; RV32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.0 + 8, align 8)1620 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)1621 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x131622 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.0 + 12)1623 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)1624 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x141625 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.0 + 16, align 16)1626 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)1627 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x151628 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.0 + 20)1629 ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)1630 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x161631 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.0 + 24, align 8)1632 ; RV32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)1633 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x171634 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD6]](p0) :: (store (s32) into %fixed-stack.0 + 28)1635 ; RV32-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD6]], [[C]](s32)1636 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va1637 ; RV32-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s32) into %ir.va)1638 ; RV32-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41639 ; RV32-NEXT: $x10 = COPY [[VAARG]](s32)1640 ; RV32-NEXT: PseudoRET implicit $x101641 ;1642 ; RV64-LABEL: name: va6_no_fixed_args1643 ; RV64: bb.1 (%ir-block.0):1644 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171645 ; RV64-NEXT: {{ $}}1646 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.01647 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 81648 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x101649 ; RV64-NEXT: G_STORE [[COPY]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.0, align 16)1650 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)1651 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x111652 ; RV64-NEXT: G_STORE [[COPY1]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.0 + 8)1653 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)1654 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x121655 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.0 + 16, align 16)1656 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)1657 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x131658 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.0 + 24)1659 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)1660 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x141661 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.0 + 32, align 16)1662 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)1663 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x151664 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.0 + 40)1665 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)1666 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x161667 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.0 + 48, align 16)1668 ; RV64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)1669 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x171670 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD6]](p0) :: (store (s64) into %fixed-stack.0 + 56)1671 ; RV64-NEXT: [[PTR_ADD7:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD6]], [[C]](s64)1672 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.va1673 ; RV64-NEXT: G_VASTART [[FRAME_INDEX1]](p0) :: (store (s64) into %ir.va)1674 ; RV64-NEXT: [[VAARG:%[0-9]+]]:_(s32) = G_VAARG [[FRAME_INDEX1]](p0), 41675 ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[VAARG]](s32)1676 ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)1677 ; RV64-NEXT: PseudoRET implicit $x101678 %va = alloca ptr1679 call void @llvm.va_start(ptr %va)1680 %1 = va_arg ptr %va, i321681 call void @llvm.va_end(ptr %va)1682 ret i32 %11683}1684 1685; TODO: improve constant materialization of stack addresses1686 1687define i32 @va_large_stack(ptr %fmt, ...) {1688 ; RV32-LABEL: name: va_large_stack1689 ; RV32: bb.1 (%ir-block.0):1690 ; RV32-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171691 ; RV32-NEXT: {{ $}}1692 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x101693 ; RV32-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11694 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 41695 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x111696 ; RV32-NEXT: G_STORE [[COPY1]](s32), [[FRAME_INDEX]](p0) :: (store (s32) into %fixed-stack.1)1697 ; RV32-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s32)1698 ; RV32-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x121699 ; RV32-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %fixed-stack.1 + 4)1700 ; RV32-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s32)1701 ; RV32-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x131702 ; RV32-NEXT: G_STORE [[COPY3]](s32), [[PTR_ADD1]](p0) :: (store (s32) into %fixed-stack.1 + 8)1703 ; RV32-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s32)1704 ; RV32-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x141705 ; RV32-NEXT: G_STORE [[COPY4]](s32), [[PTR_ADD2]](p0) :: (store (s32) into %fixed-stack.1 + 12)1706 ; RV32-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s32)1707 ; RV32-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x151708 ; RV32-NEXT: G_STORE [[COPY5]](s32), [[PTR_ADD3]](p0) :: (store (s32) into %fixed-stack.1 + 16)1709 ; RV32-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s32)1710 ; RV32-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x161711 ; RV32-NEXT: G_STORE [[COPY6]](s32), [[PTR_ADD4]](p0) :: (store (s32) into %fixed-stack.1 + 20)1712 ; RV32-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s32)1713 ; RV32-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x171714 ; RV32-NEXT: G_STORE [[COPY7]](s32), [[PTR_ADD5]](p0) :: (store (s32) into %fixed-stack.1 + 24)1715 ; RV32-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s32)1716 ; RV32-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.large1717 ; RV32-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.va1718 ; RV32-NEXT: G_VASTART [[FRAME_INDEX2]](p0) :: (store (s32) into %ir.va)1719 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.va)1720 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 41721 ; RV32-NEXT: %21:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s32)1722 ; RV32-NEXT: G_STORE %21(p0), [[FRAME_INDEX2]](p0) :: (store (p0) into %ir.va)1723 ; RV32-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)1724 ; RV32-NEXT: $x10 = COPY [[LOAD1]](s32)1725 ; RV32-NEXT: PseudoRET implicit $x101726 ;1727 ; RV64-LABEL: name: va_large_stack1728 ; RV64: bb.1 (%ir-block.0):1729 ; RV64-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x171730 ; RV64-NEXT: {{ $}}1731 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x101732 ; RV64-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.11733 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 81734 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x111735 ; RV64-NEXT: G_STORE [[COPY1]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %fixed-stack.1)1736 ; RV64-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)1737 ; RV64-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x121738 ; RV64-NEXT: G_STORE [[COPY2]](s64), [[PTR_ADD]](p0) :: (store (s64) into %fixed-stack.1 + 8)1739 ; RV64-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C]](s64)1740 ; RV64-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x131741 ; RV64-NEXT: G_STORE [[COPY3]](s64), [[PTR_ADD1]](p0) :: (store (s64) into %fixed-stack.1 + 16)1742 ; RV64-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD1]], [[C]](s64)1743 ; RV64-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x141744 ; RV64-NEXT: G_STORE [[COPY4]](s64), [[PTR_ADD2]](p0) :: (store (s64) into %fixed-stack.1 + 24)1745 ; RV64-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD2]], [[C]](s64)1746 ; RV64-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x151747 ; RV64-NEXT: G_STORE [[COPY5]](s64), [[PTR_ADD3]](p0) :: (store (s64) into %fixed-stack.1 + 32)1748 ; RV64-NEXT: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD3]], [[C]](s64)1749 ; RV64-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x161750 ; RV64-NEXT: G_STORE [[COPY6]](s64), [[PTR_ADD4]](p0) :: (store (s64) into %fixed-stack.1 + 40)1751 ; RV64-NEXT: [[PTR_ADD5:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD4]], [[C]](s64)1752 ; RV64-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x171753 ; RV64-NEXT: G_STORE [[COPY7]](s64), [[PTR_ADD5]](p0) :: (store (s64) into %fixed-stack.1 + 48)1754 ; RV64-NEXT: [[PTR_ADD6:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD5]], [[C]](s64)1755 ; RV64-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.large1756 ; RV64-NEXT: [[FRAME_INDEX2:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.va1757 ; RV64-NEXT: G_VASTART [[FRAME_INDEX2]](p0) :: (store (s64) into %ir.va)1758 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX2]](p0) :: (dereferenceable load (p0) from %ir.va, align 4)1759 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 41760 ; RV64-NEXT: %21:_(p0) = nuw nusw inbounds G_PTR_ADD [[LOAD]], [[C1]](s64)1761 ; RV64-NEXT: G_STORE %21(p0), [[FRAME_INDEX2]](p0) :: (store (p0) into %ir.va, align 4)1762 ; RV64-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.argp.cur)1763 ; RV64-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD1]](s32)1764 ; RV64-NEXT: $x10 = COPY [[ANYEXT]](s64)1765 ; RV64-NEXT: PseudoRET implicit $x101766 %large = alloca [ 100000000 x i8 ]1767 %va = alloca ptr1768 call void @llvm.va_start(ptr %va)1769 %argp.cur = load ptr, ptr %va, align 41770 %argp.next = getelementptr inbounds i8, ptr %argp.cur, i32 41771 store ptr %argp.next, ptr %va, align 41772 %1 = load i32, ptr %argp.cur, align 41773 call void @llvm.va_end(ptr %va)1774 ret i32 %11775}1776