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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK3; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-before=legalizer -simplify-mir < %s | FileCheck %s --check-prefixes=CHECK4 5define void @add_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {6 ; CHECK-LABEL: name: add_nxv2i327 ; CHECK: bb.1 (%ir-block.0):8 ; CHECK-NEXT: liveins: $v8, $v99 ; CHECK-NEXT: {{ $}}10 ; CHECK-NEXT: PseudoRET11 %c = add <vscale x 2 x i32> %a, %b12 ret void13}14 15define void @sub_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {16 ; CHECK-LABEL: name: sub_nxv2i3217 ; CHECK: bb.1 (%ir-block.0):18 ; CHECK-NEXT: liveins: $v8, $v919 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: PseudoRET21 %c = sub <vscale x 2 x i32> %a, %b22 ret void23}24 25define void @and_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {26 ; CHECK-LABEL: name: and_nxv2i3227 ; CHECK: bb.1 (%ir-block.0):28 ; CHECK-NEXT: liveins: $v8, $v929 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: PseudoRET31 %c = and <vscale x 2 x i32> %a, %b32 ret void33}34 35define void @or_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {36 ; CHECK-LABEL: name: or_nxv2i3237 ; CHECK: bb.1 (%ir-block.0):38 ; CHECK-NEXT: liveins: $v8, $v939 ; CHECK-NEXT: {{ $}}40 ; CHECK-NEXT: PseudoRET41 %c = or <vscale x 2 x i32> %a, %b42 ret void43}44 45define void @xor_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {46 ; CHECK-LABEL: name: xor_nxv2i3247 ; CHECK: bb.1 (%ir-block.0):48 ; CHECK-NEXT: liveins: $v8, $v949 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: PseudoRET51 %c = xor <vscale x 2 x i32> %a, %b52 ret void53}54