970 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \3; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfh -global-isel -stop-after=irtranslator \5; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s6 7; ==========================================================================8; ============================= Scalable Types =============================9; ==========================================================================10 11define void @test_args_nxv1i8(<vscale x 1 x i8> %a) {12 ; RV32-LABEL: name: test_args_nxv1i813 ; RV32: bb.1.entry:14 ; RV32-NEXT: liveins: $v815 ; RV32-NEXT: {{ $}}16 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v817 ; RV32-NEXT: PseudoRET18 ;19 ; RV64-LABEL: name: test_args_nxv1i820 ; RV64: bb.1.entry:21 ; RV64-NEXT: liveins: $v822 ; RV64-NEXT: {{ $}}23 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v824 ; RV64-NEXT: PseudoRET25entry:26 ret void27}28 29define void @test_args_nxv2i8(<vscale x 2 x i8> %a) {30 ; RV32-LABEL: name: test_args_nxv2i831 ; RV32: bb.1.entry:32 ; RV32-NEXT: liveins: $v833 ; RV32-NEXT: {{ $}}34 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v835 ; RV32-NEXT: PseudoRET36 ;37 ; RV64-LABEL: name: test_args_nxv2i838 ; RV64: bb.1.entry:39 ; RV64-NEXT: liveins: $v840 ; RV64-NEXT: {{ $}}41 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v842 ; RV64-NEXT: PseudoRET43entry:44 ret void45}46 47define void @test_args_nxv4i8(<vscale x 4 x i8> %a) {48 ; RV32-LABEL: name: test_args_nxv4i849 ; RV32: bb.1.entry:50 ; RV32-NEXT: liveins: $v851 ; RV32-NEXT: {{ $}}52 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v853 ; RV32-NEXT: PseudoRET54 ;55 ; RV64-LABEL: name: test_args_nxv4i856 ; RV64: bb.1.entry:57 ; RV64-NEXT: liveins: $v858 ; RV64-NEXT: {{ $}}59 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v860 ; RV64-NEXT: PseudoRET61entry:62 ret void63}64 65define void @test_args_nxv8i8(<vscale x 8 x i8> %a) {66 ; RV32-LABEL: name: test_args_nxv8i867 ; RV32: bb.1.entry:68 ; RV32-NEXT: liveins: $v869 ; RV32-NEXT: {{ $}}70 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v871 ; RV32-NEXT: PseudoRET72 ;73 ; RV64-LABEL: name: test_args_nxv8i874 ; RV64: bb.1.entry:75 ; RV64-NEXT: liveins: $v876 ; RV64-NEXT: {{ $}}77 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v878 ; RV64-NEXT: PseudoRET79entry:80 ret void81}82 83define void @test_args_nxv16i8(<vscale x 16 x i8> %a) {84 ; RV32-LABEL: name: test_args_nxv16i885 ; RV32: bb.1.entry:86 ; RV32-NEXT: liveins: $v8m287 ; RV32-NEXT: {{ $}}88 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m289 ; RV32-NEXT: PseudoRET90 ;91 ; RV64-LABEL: name: test_args_nxv16i892 ; RV64: bb.1.entry:93 ; RV64-NEXT: liveins: $v8m294 ; RV64-NEXT: {{ $}}95 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m296 ; RV64-NEXT: PseudoRET97entry:98 ret void99}100 101define void @test_args_nxv32i8(<vscale x 32 x i8> %a) {102 ; RV32-LABEL: name: test_args_nxv32i8103 ; RV32: bb.1.entry:104 ; RV32-NEXT: liveins: $v8m4105 ; RV32-NEXT: {{ $}}106 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4107 ; RV32-NEXT: PseudoRET108 ;109 ; RV64-LABEL: name: test_args_nxv32i8110 ; RV64: bb.1.entry:111 ; RV64-NEXT: liveins: $v8m4112 ; RV64-NEXT: {{ $}}113 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4114 ; RV64-NEXT: PseudoRET115entry:116 ret void117}118 119define void @test_args_nxv64i8(<vscale x 64 x i8> %a) {120 ; RV32-LABEL: name: test_args_nxv64i8121 ; RV32: bb.1.entry:122 ; RV32-NEXT: liveins: $v8m8123 ; RV32-NEXT: {{ $}}124 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8125 ; RV32-NEXT: PseudoRET126 ;127 ; RV64-LABEL: name: test_args_nxv64i8128 ; RV64: bb.1.entry:129 ; RV64-NEXT: liveins: $v8m8130 ; RV64-NEXT: {{ $}}131 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8132 ; RV64-NEXT: PseudoRET133entry:134 ret void135}136 137define void @test_args_nxv1i16(<vscale x 1 x i16> %a) {138 ; RV32-LABEL: name: test_args_nxv1i16139 ; RV32: bb.1.entry:140 ; RV32-NEXT: liveins: $v8141 ; RV32-NEXT: {{ $}}142 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8143 ; RV32-NEXT: PseudoRET144 ;145 ; RV64-LABEL: name: test_args_nxv1i16146 ; RV64: bb.1.entry:147 ; RV64-NEXT: liveins: $v8148 ; RV64-NEXT: {{ $}}149 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8150 ; RV64-NEXT: PseudoRET151entry:152 ret void153}154 155define void @test_args_nxv2i16(<vscale x 2 x i16> %a) {156 ; RV32-LABEL: name: test_args_nxv2i16157 ; RV32: bb.1.entry:158 ; RV32-NEXT: liveins: $v8159 ; RV32-NEXT: {{ $}}160 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8161 ; RV32-NEXT: PseudoRET162 ;163 ; RV64-LABEL: name: test_args_nxv2i16164 ; RV64: bb.1.entry:165 ; RV64-NEXT: liveins: $v8166 ; RV64-NEXT: {{ $}}167 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8168 ; RV64-NEXT: PseudoRET169entry:170 ret void171}172 173define void @test_args_nxv4i16(<vscale x 4 x i16> %a) {174 ; RV32-LABEL: name: test_args_nxv4i16175 ; RV32: bb.1.entry:176 ; RV32-NEXT: liveins: $v8177 ; RV32-NEXT: {{ $}}178 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8179 ; RV32-NEXT: PseudoRET180 ;181 ; RV64-LABEL: name: test_args_nxv4i16182 ; RV64: bb.1.entry:183 ; RV64-NEXT: liveins: $v8184 ; RV64-NEXT: {{ $}}185 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8186 ; RV64-NEXT: PseudoRET187entry:188 ret void189}190 191define void @test_args_nxv8i16(<vscale x 8 x i16> %a) {192 ; RV32-LABEL: name: test_args_nxv8i16193 ; RV32: bb.1.entry:194 ; RV32-NEXT: liveins: $v8m2195 ; RV32-NEXT: {{ $}}196 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2197 ; RV32-NEXT: PseudoRET198 ;199 ; RV64-LABEL: name: test_args_nxv8i16200 ; RV64: bb.1.entry:201 ; RV64-NEXT: liveins: $v8m2202 ; RV64-NEXT: {{ $}}203 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2204 ; RV64-NEXT: PseudoRET205entry:206 ret void207}208 209define void @test_args_nxv16i16(<vscale x 16 x i16> %a) {210 ; RV32-LABEL: name: test_args_nxv16i16211 ; RV32: bb.1.entry:212 ; RV32-NEXT: liveins: $v8m4213 ; RV32-NEXT: {{ $}}214 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4215 ; RV32-NEXT: PseudoRET216 ;217 ; RV64-LABEL: name: test_args_nxv16i16218 ; RV64: bb.1.entry:219 ; RV64-NEXT: liveins: $v8m4220 ; RV64-NEXT: {{ $}}221 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4222 ; RV64-NEXT: PseudoRET223entry:224 ret void225}226 227define void @test_args_nxv32i16(<vscale x 32 x i16> %a) {228 ; RV32-LABEL: name: test_args_nxv32i16229 ; RV32: bb.1.entry:230 ; RV32-NEXT: liveins: $v8m8231 ; RV32-NEXT: {{ $}}232 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8233 ; RV32-NEXT: PseudoRET234 ;235 ; RV64-LABEL: name: test_args_nxv32i16236 ; RV64: bb.1.entry:237 ; RV64-NEXT: liveins: $v8m8238 ; RV64-NEXT: {{ $}}239 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8240 ; RV64-NEXT: PseudoRET241entry:242 ret void243}244 245define void @test_args_nxv1i32(<vscale x 1 x i32> %a) {246 ; RV32-LABEL: name: test_args_nxv1i32247 ; RV32: bb.1.entry:248 ; RV32-NEXT: liveins: $v8249 ; RV32-NEXT: {{ $}}250 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8251 ; RV32-NEXT: PseudoRET252 ;253 ; RV64-LABEL: name: test_args_nxv1i32254 ; RV64: bb.1.entry:255 ; RV64-NEXT: liveins: $v8256 ; RV64-NEXT: {{ $}}257 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8258 ; RV64-NEXT: PseudoRET259entry:260 ret void261}262 263define void @test_args_nxv2i32(<vscale x 2 x i32> %a) {264 ; RV32-LABEL: name: test_args_nxv2i32265 ; RV32: bb.1.entry:266 ; RV32-NEXT: liveins: $v8267 ; RV32-NEXT: {{ $}}268 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8269 ; RV32-NEXT: PseudoRET270 ;271 ; RV64-LABEL: name: test_args_nxv2i32272 ; RV64: bb.1.entry:273 ; RV64-NEXT: liveins: $v8274 ; RV64-NEXT: {{ $}}275 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8276 ; RV64-NEXT: PseudoRET277entry:278 ret void279}280 281define void @test_args_nxv4i32(<vscale x 4 x i32> %a) {282 ; RV32-LABEL: name: test_args_nxv4i32283 ; RV32: bb.1.entry:284 ; RV32-NEXT: liveins: $v8m2285 ; RV32-NEXT: {{ $}}286 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2287 ; RV32-NEXT: PseudoRET288 ;289 ; RV64-LABEL: name: test_args_nxv4i32290 ; RV64: bb.1.entry:291 ; RV64-NEXT: liveins: $v8m2292 ; RV64-NEXT: {{ $}}293 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2294 ; RV64-NEXT: PseudoRET295entry:296 ret void297}298 299define void @test_args_nxv8i32(<vscale x 8 x i32> %a) {300 ; RV32-LABEL: name: test_args_nxv8i32301 ; RV32: bb.1.entry:302 ; RV32-NEXT: liveins: $v8m4303 ; RV32-NEXT: {{ $}}304 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4305 ; RV32-NEXT: PseudoRET306 ;307 ; RV64-LABEL: name: test_args_nxv8i32308 ; RV64: bb.1.entry:309 ; RV64-NEXT: liveins: $v8m4310 ; RV64-NEXT: {{ $}}311 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4312 ; RV64-NEXT: PseudoRET313entry:314 ret void315}316 317define void @test_args_nxv16i32(<vscale x 16 x i32> %a) {318 ; RV32-LABEL: name: test_args_nxv16i32319 ; RV32: bb.1.entry:320 ; RV32-NEXT: liveins: $v8m8321 ; RV32-NEXT: {{ $}}322 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8323 ; RV32-NEXT: PseudoRET324 ;325 ; RV64-LABEL: name: test_args_nxv16i32326 ; RV64: bb.1.entry:327 ; RV64-NEXT: liveins: $v8m8328 ; RV64-NEXT: {{ $}}329 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8330 ; RV64-NEXT: PseudoRET331entry:332 ret void333}334 335define void @test_args_nxv1i64(<vscale x 1 x i64> %a) {336 ; RV32-LABEL: name: test_args_nxv1i64337 ; RV32: bb.1.entry:338 ; RV32-NEXT: liveins: $v8339 ; RV32-NEXT: {{ $}}340 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8341 ; RV32-NEXT: PseudoRET342 ;343 ; RV64-LABEL: name: test_args_nxv1i64344 ; RV64: bb.1.entry:345 ; RV64-NEXT: liveins: $v8346 ; RV64-NEXT: {{ $}}347 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8348 ; RV64-NEXT: PseudoRET349entry:350 ret void351}352 353define void @test_args_nxv2i64(<vscale x 2 x i64> %a) {354 ; RV32-LABEL: name: test_args_nxv2i64355 ; RV32: bb.1.entry:356 ; RV32-NEXT: liveins: $v8m2357 ; RV32-NEXT: {{ $}}358 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2359 ; RV32-NEXT: PseudoRET360 ;361 ; RV64-LABEL: name: test_args_nxv2i64362 ; RV64: bb.1.entry:363 ; RV64-NEXT: liveins: $v8m2364 ; RV64-NEXT: {{ $}}365 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2366 ; RV64-NEXT: PseudoRET367entry:368 ret void369}370 371define void @test_args_nxv4i64(<vscale x 4 x i64> %a) {372 ; RV32-LABEL: name: test_args_nxv4i64373 ; RV32: bb.1.entry:374 ; RV32-NEXT: liveins: $v8m4375 ; RV32-NEXT: {{ $}}376 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4377 ; RV32-NEXT: PseudoRET378 ;379 ; RV64-LABEL: name: test_args_nxv4i64380 ; RV64: bb.1.entry:381 ; RV64-NEXT: liveins: $v8m4382 ; RV64-NEXT: {{ $}}383 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4384 ; RV64-NEXT: PseudoRET385entry:386 ret void387}388 389define void @test_args_nxv8i64(<vscale x 8 x i64> %a) {390 ; RV32-LABEL: name: test_args_nxv8i64391 ; RV32: bb.1.entry:392 ; RV32-NEXT: liveins: $v8m8393 ; RV32-NEXT: {{ $}}394 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8395 ; RV32-NEXT: PseudoRET396 ;397 ; RV64-LABEL: name: test_args_nxv8i64398 ; RV64: bb.1.entry:399 ; RV64-NEXT: liveins: $v8m8400 ; RV64-NEXT: {{ $}}401 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8402 ; RV64-NEXT: PseudoRET403entry:404 ret void405}406 407define void @test_args_nxv64i1(<vscale x 64 x i1> %a) {408 ; RV32-LABEL: name: test_args_nxv64i1409 ; RV32: bb.1.entry:410 ; RV32-NEXT: liveins: $v0411 ; RV32-NEXT: {{ $}}412 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0413 ; RV32-NEXT: PseudoRET414 ;415 ; RV64-LABEL: name: test_args_nxv64i1416 ; RV64: bb.1.entry:417 ; RV64-NEXT: liveins: $v0418 ; RV64-NEXT: {{ $}}419 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v0420 ; RV64-NEXT: PseudoRET421entry:422 ret void423}424 425define void @test_args_nxv32i1(<vscale x 32 x i1> %a) {426 ; RV32-LABEL: name: test_args_nxv32i1427 ; RV32: bb.1.entry:428 ; RV32-NEXT: liveins: $v0429 ; RV32-NEXT: {{ $}}430 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0431 ; RV32-NEXT: PseudoRET432 ;433 ; RV64-LABEL: name: test_args_nxv32i1434 ; RV64: bb.1.entry:435 ; RV64-NEXT: liveins: $v0436 ; RV64-NEXT: {{ $}}437 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s1>) = COPY $v0438 ; RV64-NEXT: PseudoRET439entry:440 ret void441}442 443define void @test_args_nxv16i1(<vscale x 16 x i1> %a) {444 ; RV32-LABEL: name: test_args_nxv16i1445 ; RV32: bb.1.entry:446 ; RV32-NEXT: liveins: $v0447 ; RV32-NEXT: {{ $}}448 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0449 ; RV32-NEXT: PseudoRET450 ;451 ; RV64-LABEL: name: test_args_nxv16i1452 ; RV64: bb.1.entry:453 ; RV64-NEXT: liveins: $v0454 ; RV64-NEXT: {{ $}}455 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s1>) = COPY $v0456 ; RV64-NEXT: PseudoRET457entry:458 ret void459}460 461define void @test_args_nxv8i1(<vscale x 8 x i1> %a) {462 ; RV32-LABEL: name: test_args_nxv8i1463 ; RV32: bb.1.entry:464 ; RV32-NEXT: liveins: $v0465 ; RV32-NEXT: {{ $}}466 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0467 ; RV32-NEXT: PseudoRET468 ;469 ; RV64-LABEL: name: test_args_nxv8i1470 ; RV64: bb.1.entry:471 ; RV64-NEXT: liveins: $v0472 ; RV64-NEXT: {{ $}}473 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v0474 ; RV64-NEXT: PseudoRET475entry:476 ret void477}478 479define void @test_args_nxv4i1(<vscale x 4 x i1> %a) {480 ; RV32-LABEL: name: test_args_nxv4i1481 ; RV32: bb.1.entry:482 ; RV32-NEXT: liveins: $v0483 ; RV32-NEXT: {{ $}}484 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0485 ; RV32-NEXT: PseudoRET486 ;487 ; RV64-LABEL: name: test_args_nxv4i1488 ; RV64: bb.1.entry:489 ; RV64-NEXT: liveins: $v0490 ; RV64-NEXT: {{ $}}491 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v0492 ; RV64-NEXT: PseudoRET493entry:494 ret void495}496 497define void @test_args_nxv2i1(<vscale x 2 x i1> %a) {498 ; RV32-LABEL: name: test_args_nxv2i1499 ; RV32: bb.1.entry:500 ; RV32-NEXT: liveins: $v0501 ; RV32-NEXT: {{ $}}502 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0503 ; RV32-NEXT: PseudoRET504 ;505 ; RV64-LABEL: name: test_args_nxv2i1506 ; RV64: bb.1.entry:507 ; RV64-NEXT: liveins: $v0508 ; RV64-NEXT: {{ $}}509 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s1>) = COPY $v0510 ; RV64-NEXT: PseudoRET511entry:512 ret void513}514 515define void @test_args_nxv1i1(<vscale x 1 x i1> %a) {516 ; RV32-LABEL: name: test_args_nxv1i1517 ; RV32: bb.1.entry:518 ; RV32-NEXT: liveins: $v0519 ; RV32-NEXT: {{ $}}520 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0521 ; RV32-NEXT: PseudoRET522 ;523 ; RV64-LABEL: name: test_args_nxv1i1524 ; RV64: bb.1.entry:525 ; RV64-NEXT: liveins: $v0526 ; RV64-NEXT: {{ $}}527 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0528 ; RV64-NEXT: PseudoRET529entry:530 ret void531}532 533define void @test_args_nxv1f32(<vscale x 1 x float> %a) {534 ; RV32-LABEL: name: test_args_nxv1f32535 ; RV32: bb.1.entry:536 ; RV32-NEXT: liveins: $v8537 ; RV32-NEXT: {{ $}}538 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8539 ; RV32-NEXT: PseudoRET540 ;541 ; RV64-LABEL: name: test_args_nxv1f32542 ; RV64: bb.1.entry:543 ; RV64-NEXT: liveins: $v8544 ; RV64-NEXT: {{ $}}545 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8546 ; RV64-NEXT: PseudoRET547entry:548 ret void549}550 551define void @test_args_nxv2f32(<vscale x 2 x float> %a) {552 ; RV32-LABEL: name: test_args_nxv2f32553 ; RV32: bb.1.entry:554 ; RV32-NEXT: liveins: $v8555 ; RV32-NEXT: {{ $}}556 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8557 ; RV32-NEXT: PseudoRET558 ;559 ; RV64-LABEL: name: test_args_nxv2f32560 ; RV64: bb.1.entry:561 ; RV64-NEXT: liveins: $v8562 ; RV64-NEXT: {{ $}}563 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8564 ; RV64-NEXT: PseudoRET565entry:566 ret void567}568 569define void @test_args_nxv4f32(<vscale x 4 x float> %a) {570 ; RV32-LABEL: name: test_args_nxv4f32571 ; RV32: bb.1.entry:572 ; RV32-NEXT: liveins: $v8m2573 ; RV32-NEXT: {{ $}}574 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2575 ; RV32-NEXT: PseudoRET576 ;577 ; RV64-LABEL: name: test_args_nxv4f32578 ; RV64: bb.1.entry:579 ; RV64-NEXT: liveins: $v8m2580 ; RV64-NEXT: {{ $}}581 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2582 ; RV64-NEXT: PseudoRET583entry:584 ret void585}586 587define void @test_args_nxv8f32(<vscale x 8 x float> %a) {588 ; RV32-LABEL: name: test_args_nxv8f32589 ; RV32: bb.1.entry:590 ; RV32-NEXT: liveins: $v8m4591 ; RV32-NEXT: {{ $}}592 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4593 ; RV32-NEXT: PseudoRET594 ;595 ; RV64-LABEL: name: test_args_nxv8f32596 ; RV64: bb.1.entry:597 ; RV64-NEXT: liveins: $v8m4598 ; RV64-NEXT: {{ $}}599 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4600 ; RV64-NEXT: PseudoRET601entry:602 ret void603}604 605define void @test_args_nxv16f32(<vscale x 16 x float> %a) {606 ; RV32-LABEL: name: test_args_nxv16f32607 ; RV32: bb.1.entry:608 ; RV32-NEXT: liveins: $v8m8609 ; RV32-NEXT: {{ $}}610 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8611 ; RV32-NEXT: PseudoRET612 ;613 ; RV64-LABEL: name: test_args_nxv16f32614 ; RV64: bb.1.entry:615 ; RV64-NEXT: liveins: $v8m8616 ; RV64-NEXT: {{ $}}617 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8618 ; RV64-NEXT: PseudoRET619entry:620 ret void621}622 623define void @test_args_nxv1f64(<vscale x 1 x double> %a) {624 ; RV32-LABEL: name: test_args_nxv1f64625 ; RV32: bb.1.entry:626 ; RV32-NEXT: liveins: $v8627 ; RV32-NEXT: {{ $}}628 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8629 ; RV32-NEXT: PseudoRET630 ;631 ; RV64-LABEL: name: test_args_nxv1f64632 ; RV64: bb.1.entry:633 ; RV64-NEXT: liveins: $v8634 ; RV64-NEXT: {{ $}}635 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8636 ; RV64-NEXT: PseudoRET637entry:638 ret void639}640 641define void @test_args_nxv2f64(<vscale x 2 x double> %a) {642 ; RV32-LABEL: name: test_args_nxv2f64643 ; RV32: bb.1.entry:644 ; RV32-NEXT: liveins: $v8m2645 ; RV32-NEXT: {{ $}}646 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2647 ; RV32-NEXT: PseudoRET648 ;649 ; RV64-LABEL: name: test_args_nxv2f64650 ; RV64: bb.1.entry:651 ; RV64-NEXT: liveins: $v8m2652 ; RV64-NEXT: {{ $}}653 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2654 ; RV64-NEXT: PseudoRET655entry:656 ret void657}658 659define void @test_args_nxv4f64(<vscale x 4 x double> %a) {660 ; RV32-LABEL: name: test_args_nxv4f64661 ; RV32: bb.1.entry:662 ; RV32-NEXT: liveins: $v8m4663 ; RV32-NEXT: {{ $}}664 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4665 ; RV32-NEXT: PseudoRET666 ;667 ; RV64-LABEL: name: test_args_nxv4f64668 ; RV64: bb.1.entry:669 ; RV64-NEXT: liveins: $v8m4670 ; RV64-NEXT: {{ $}}671 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4672 ; RV64-NEXT: PseudoRET673entry:674 ret void675}676 677define void @test_args_nxv8f64(<vscale x 8 x double> %a) {678 ; RV32-LABEL: name: test_args_nxv8f64679 ; RV32: bb.1.entry:680 ; RV32-NEXT: liveins: $v8m8681 ; RV32-NEXT: {{ $}}682 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8683 ; RV32-NEXT: PseudoRET684 ;685 ; RV64-LABEL: name: test_args_nxv8f64686 ; RV64: bb.1.entry:687 ; RV64-NEXT: liveins: $v8m8688 ; RV64-NEXT: {{ $}}689 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8690 ; RV64-NEXT: PseudoRET691entry:692 ret void693}694 695define void @test_args_nxv1f16(<vscale x 1 x half> %a) {696 ; RV32-LABEL: name: test_args_nxv1f16697 ; RV32: bb.1.entry:698 ; RV32-NEXT: liveins: $v8699 ; RV32-NEXT: {{ $}}700 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8701 ; RV32-NEXT: PseudoRET702 ;703 ; RV64-LABEL: name: test_args_nxv1f16704 ; RV64: bb.1.entry:705 ; RV64-NEXT: liveins: $v8706 ; RV64-NEXT: {{ $}}707 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8708 ; RV64-NEXT: PseudoRET709entry:710 ret void711}712 713define void @test_args_nxv2f16(<vscale x 2 x half> %a) {714 ; RV32-LABEL: name: test_args_nxv2f16715 ; RV32: bb.1.entry:716 ; RV32-NEXT: liveins: $v8717 ; RV32-NEXT: {{ $}}718 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8719 ; RV32-NEXT: PseudoRET720 ;721 ; RV64-LABEL: name: test_args_nxv2f16722 ; RV64: bb.1.entry:723 ; RV64-NEXT: liveins: $v8724 ; RV64-NEXT: {{ $}}725 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8726 ; RV64-NEXT: PseudoRET727entry:728 ret void729}730 731define void @test_args_nxv4f16(<vscale x 4 x half> %a) {732 ; RV32-LABEL: name: test_args_nxv4f16733 ; RV32: bb.1.entry:734 ; RV32-NEXT: liveins: $v8735 ; RV32-NEXT: {{ $}}736 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8737 ; RV32-NEXT: PseudoRET738 ;739 ; RV64-LABEL: name: test_args_nxv4f16740 ; RV64: bb.1.entry:741 ; RV64-NEXT: liveins: $v8742 ; RV64-NEXT: {{ $}}743 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8744 ; RV64-NEXT: PseudoRET745entry:746 ret void747}748 749define void @test_args_nxv8f16(<vscale x 8 x half> %a) {750 ; RV32-LABEL: name: test_args_nxv8f16751 ; RV32: bb.1.entry:752 ; RV32-NEXT: liveins: $v8m2753 ; RV32-NEXT: {{ $}}754 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2755 ; RV32-NEXT: PseudoRET756 ;757 ; RV64-LABEL: name: test_args_nxv8f16758 ; RV64: bb.1.entry:759 ; RV64-NEXT: liveins: $v8m2760 ; RV64-NEXT: {{ $}}761 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2762 ; RV64-NEXT: PseudoRET763entry:764 ret void765}766 767define void @test_args_nxv16f16(<vscale x 16 x half> %a) {768 ; RV32-LABEL: name: test_args_nxv16f16769 ; RV32: bb.1.entry:770 ; RV32-NEXT: liveins: $v8m4771 ; RV32-NEXT: {{ $}}772 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4773 ; RV32-NEXT: PseudoRET774 ;775 ; RV64-LABEL: name: test_args_nxv16f16776 ; RV64: bb.1.entry:777 ; RV64-NEXT: liveins: $v8m4778 ; RV64-NEXT: {{ $}}779 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4780 ; RV64-NEXT: PseudoRET781entry:782 ret void783}784 785define void @test_args_nxv32f16(<vscale x 32 x half> %a) {786 ; RV32-LABEL: name: test_args_nxv32f16787 ; RV32: bb.1.entry:788 ; RV32-NEXT: liveins: $v8m8789 ; RV32-NEXT: {{ $}}790 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8791 ; RV32-NEXT: PseudoRET792 ;793 ; RV64-LABEL: name: test_args_nxv32f16794 ; RV64: bb.1.entry:795 ; RV64-NEXT: liveins: $v8m8796 ; RV64-NEXT: {{ $}}797 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8798 ; RV64-NEXT: PseudoRET799entry:800 ret void801}802 803define void @test_args_nxv1b16(<vscale x 1 x bfloat> %a) {804 ; RV32-LABEL: name: test_args_nxv1b16805 ; RV32: bb.1.entry:806 ; RV32-NEXT: liveins: $v8807 ; RV32-NEXT: {{ $}}808 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8809 ; RV32-NEXT: PseudoRET810 ;811 ; RV64-LABEL: name: test_args_nxv1b16812 ; RV64: bb.1.entry:813 ; RV64-NEXT: liveins: $v8814 ; RV64-NEXT: {{ $}}815 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8816 ; RV64-NEXT: PseudoRET817entry:818 ret void819}820 821define void @test_args_nxv2b16(<vscale x 2 x bfloat> %a) {822 ; RV32-LABEL: name: test_args_nxv2b16823 ; RV32: bb.1.entry:824 ; RV32-NEXT: liveins: $v8825 ; RV32-NEXT: {{ $}}826 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8827 ; RV32-NEXT: PseudoRET828 ;829 ; RV64-LABEL: name: test_args_nxv2b16830 ; RV64: bb.1.entry:831 ; RV64-NEXT: liveins: $v8832 ; RV64-NEXT: {{ $}}833 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8834 ; RV64-NEXT: PseudoRET835entry:836 ret void837}838 839define void @test_args_nxv4b16(<vscale x 4 x bfloat> %a) {840 ; RV32-LABEL: name: test_args_nxv4b16841 ; RV32: bb.1.entry:842 ; RV32-NEXT: liveins: $v8843 ; RV32-NEXT: {{ $}}844 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8845 ; RV32-NEXT: PseudoRET846 ;847 ; RV64-LABEL: name: test_args_nxv4b16848 ; RV64: bb.1.entry:849 ; RV64-NEXT: liveins: $v8850 ; RV64-NEXT: {{ $}}851 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8852 ; RV64-NEXT: PseudoRET853entry:854 ret void855}856 857define void @test_args_nxv8b16(<vscale x 8 x bfloat> %a) {858 ; RV32-LABEL: name: test_args_nxv8b16859 ; RV32: bb.1.entry:860 ; RV32-NEXT: liveins: $v8m2861 ; RV32-NEXT: {{ $}}862 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2863 ; RV32-NEXT: PseudoRET864 ;865 ; RV64-LABEL: name: test_args_nxv8b16866 ; RV64: bb.1.entry:867 ; RV64-NEXT: liveins: $v8m2868 ; RV64-NEXT: {{ $}}869 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2870 ; RV64-NEXT: PseudoRET871entry:872 ret void873}874 875define void @test_args_nxv16b16(<vscale x 16 x bfloat> %a) {876 ; RV32-LABEL: name: test_args_nxv16b16877 ; RV32: bb.1.entry:878 ; RV32-NEXT: liveins: $v8m4879 ; RV32-NEXT: {{ $}}880 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4881 ; RV32-NEXT: PseudoRET882 ;883 ; RV64-LABEL: name: test_args_nxv16b16884 ; RV64: bb.1.entry:885 ; RV64-NEXT: liveins: $v8m4886 ; RV64-NEXT: {{ $}}887 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4888 ; RV64-NEXT: PseudoRET889entry:890 ret void891}892 893define void @test_args_nxv32b16(<vscale x 32 x bfloat> %a) {894 ; RV32-LABEL: name: test_args_nxv32b16895 ; RV32: bb.1.entry:896 ; RV32-NEXT: liveins: $v8m8897 ; RV32-NEXT: {{ $}}898 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8899 ; RV32-NEXT: PseudoRET900 ;901 ; RV64-LABEL: name: test_args_nxv32b16902 ; RV64: bb.1.entry:903 ; RV64-NEXT: liveins: $v8m8904 ; RV64-NEXT: {{ $}}905 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8906 ; RV64-NEXT: PseudoRET907entry:908 ret void909}910 911define void @test_args_nxv1i1_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b) {912 ; RV32-LABEL: name: test_args_nxv1i1_nxv1i1913 ; RV32: bb.1.entry:914 ; RV32-NEXT: liveins: $v0, $v8915 ; RV32-NEXT: {{ $}}916 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0917 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8918 ; RV32-NEXT: PseudoRET919 ;920 ; RV64-LABEL: name: test_args_nxv1i1_nxv1i1921 ; RV64: bb.1.entry:922 ; RV64-NEXT: liveins: $v0, $v8923 ; RV64-NEXT: {{ $}}924 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0925 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v8926 ; RV64-NEXT: PseudoRET927entry:928 ret void929}930 931define void @test_args_nxv1i1_nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b) {932 ; RV32-LABEL: name: test_args_nxv1i1_nxv1i32933 ; RV32: bb.1.entry:934 ; RV32-NEXT: liveins: $v0, $v8935 ; RV32-NEXT: {{ $}}936 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0937 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8938 ; RV32-NEXT: PseudoRET939 ;940 ; RV64-LABEL: name: test_args_nxv1i1_nxv1i32941 ; RV64: bb.1.entry:942 ; RV64-NEXT: liveins: $v0, $v8943 ; RV64-NEXT: {{ $}}944 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0945 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8946 ; RV64-NEXT: PseudoRET947entry:948 ret void949}950 951define void @test_args_nxv1i32_nxv1i1(<vscale x 1 x i32> %a, <vscale x 1 x i1> %b) {952 ; RV32-LABEL: name: test_args_nxv1i32_nxv1i1953 ; RV32: bb.1.entry:954 ; RV32-NEXT: liveins: $v0, $v8955 ; RV32-NEXT: {{ $}}956 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8957 ; RV32-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0958 ; RV32-NEXT: PseudoRET959 ;960 ; RV64-LABEL: name: test_args_nxv1i32_nxv1i1961 ; RV64: bb.1.entry:962 ; RV64-NEXT: liveins: $v0, $v8963 ; RV64-NEXT: {{ $}}964 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8965 ; RV64-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s1>) = COPY $v0966 ; RV64-NEXT: PseudoRET967entry:968 ret void969}970