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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s3; RUN: llc -mtriple=riscv64 -mattr=+v -global-isel -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s4 5define <vscale x 1 x i8> @vload_nx1i8(ptr %pa) {6 ; RV32-LABEL: name: vload_nx1i87 ; RV32: bb.1 (%ir-block.0):8 ; RV32-NEXT: liveins: $x109 ; RV32-NEXT: {{ $}}10 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1011 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s8>) from %ir.pa)12 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s8>)13 ; RV32-NEXT: PseudoRET implicit $v814 ;15 ; RV64-LABEL: name: vload_nx1i816 ; RV64: bb.1 (%ir-block.0):17 ; RV64-NEXT: liveins: $x1018 ; RV64-NEXT: {{ $}}19 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1020 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s8>) from %ir.pa)21 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s8>)22 ; RV64-NEXT: PseudoRET implicit $v823 %va = load <vscale x 1 x i8>, ptr %pa24 ret <vscale x 1 x i8> %va25}26 27define <vscale x 2 x i8> @vload_nx2i8(ptr %pa) {28 ; RV32-LABEL: name: vload_nx2i829 ; RV32: bb.1 (%ir-block.0):30 ; RV32-NEXT: liveins: $x1031 ; RV32-NEXT: {{ $}}32 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1033 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s8>) from %ir.pa)34 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s8>)35 ; RV32-NEXT: PseudoRET implicit $v836 ;37 ; RV64-LABEL: name: vload_nx2i838 ; RV64: bb.1 (%ir-block.0):39 ; RV64-NEXT: liveins: $x1040 ; RV64-NEXT: {{ $}}41 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1042 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s8>) from %ir.pa)43 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s8>)44 ; RV64-NEXT: PseudoRET implicit $v845 %va = load <vscale x 2 x i8>, ptr %pa46 ret <vscale x 2 x i8> %va47}48 49define <vscale x 4 x i8> @vload_nx4i8(ptr %pa) {50 ; RV32-LABEL: name: vload_nx4i851 ; RV32: bb.1 (%ir-block.0):52 ; RV32-NEXT: liveins: $x1053 ; RV32-NEXT: {{ $}}54 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1055 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s8>) from %ir.pa)56 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s8>)57 ; RV32-NEXT: PseudoRET implicit $v858 ;59 ; RV64-LABEL: name: vload_nx4i860 ; RV64: bb.1 (%ir-block.0):61 ; RV64-NEXT: liveins: $x1062 ; RV64-NEXT: {{ $}}63 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1064 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s8>) from %ir.pa)65 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s8>)66 ; RV64-NEXT: PseudoRET implicit $v867 %va = load <vscale x 4 x i8>, ptr %pa68 ret <vscale x 4 x i8> %va69}70 71define <vscale x 8 x i8> @vload_nx8i8(ptr %pa) {72 ; RV32-LABEL: name: vload_nx8i873 ; RV32: bb.1 (%ir-block.0):74 ; RV32-NEXT: liveins: $x1075 ; RV32-NEXT: {{ $}}76 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1077 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa)78 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 8 x s8>)79 ; RV32-NEXT: PseudoRET implicit $v880 ;81 ; RV64-LABEL: name: vload_nx8i882 ; RV64: bb.1 (%ir-block.0):83 ; RV64-NEXT: liveins: $x1084 ; RV64-NEXT: {{ $}}85 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1086 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa)87 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 8 x s8>)88 ; RV64-NEXT: PseudoRET implicit $v889 %va = load <vscale x 8 x i8>, ptr %pa90 ret <vscale x 8 x i8> %va91}92 93define <vscale x 16 x i8> @vload_nx16i8(ptr %pa) {94 ; RV32-LABEL: name: vload_nx16i895 ; RV32: bb.1 (%ir-block.0):96 ; RV32-NEXT: liveins: $x1097 ; RV32-NEXT: {{ $}}98 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x1099 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)100 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)101 ; RV32-NEXT: PseudoRET implicit $v8m2102 ;103 ; RV64-LABEL: name: vload_nx16i8104 ; RV64: bb.1 (%ir-block.0):105 ; RV64-NEXT: liveins: $x10106 ; RV64-NEXT: {{ $}}107 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10108 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)109 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)110 ; RV64-NEXT: PseudoRET implicit $v8m2111 %va = load <vscale x 16 x i8>, ptr %pa112 ret <vscale x 16 x i8> %va113}114 115define <vscale x 32 x i8> @vload_nx32i8(ptr %pa) {116 ; RV32-LABEL: name: vload_nx32i8117 ; RV32: bb.1 (%ir-block.0):118 ; RV32-NEXT: liveins: $x10119 ; RV32-NEXT: {{ $}}120 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10121 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s8>) from %ir.pa)122 ; RV32-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 32 x s8>)123 ; RV32-NEXT: PseudoRET implicit $v8m4124 ;125 ; RV64-LABEL: name: vload_nx32i8126 ; RV64: bb.1 (%ir-block.0):127 ; RV64-NEXT: liveins: $x10128 ; RV64-NEXT: {{ $}}129 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10130 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s8>) from %ir.pa)131 ; RV64-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 32 x s8>)132 ; RV64-NEXT: PseudoRET implicit $v8m4133 %va = load <vscale x 32 x i8>, ptr %pa134 ret <vscale x 32 x i8> %va135}136 137define <vscale x 64 x i8> @vload_nx64i8(ptr %pa) {138 ; RV32-LABEL: name: vload_nx64i8139 ; RV32: bb.1 (%ir-block.0):140 ; RV32-NEXT: liveins: $x10141 ; RV32-NEXT: {{ $}}142 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10143 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 64 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 64 x s8>) from %ir.pa)144 ; RV32-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 64 x s8>)145 ; RV32-NEXT: PseudoRET implicit $v8m8146 ;147 ; RV64-LABEL: name: vload_nx64i8148 ; RV64: bb.1 (%ir-block.0):149 ; RV64-NEXT: liveins: $x10150 ; RV64-NEXT: {{ $}}151 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10152 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 64 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 64 x s8>) from %ir.pa)153 ; RV64-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 64 x s8>)154 ; RV64-NEXT: PseudoRET implicit $v8m8155 %va = load <vscale x 64 x i8>, ptr %pa156 ret <vscale x 64 x i8> %va157}158 159define <vscale x 1 x i16> @vload_nx1i16(ptr %pa) {160 ; RV32-LABEL: name: vload_nx1i16161 ; RV32: bb.1 (%ir-block.0):162 ; RV32-NEXT: liveins: $x10163 ; RV32-NEXT: {{ $}}164 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10165 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s16>) from %ir.pa)166 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s16>)167 ; RV32-NEXT: PseudoRET implicit $v8168 ;169 ; RV64-LABEL: name: vload_nx1i16170 ; RV64: bb.1 (%ir-block.0):171 ; RV64-NEXT: liveins: $x10172 ; RV64-NEXT: {{ $}}173 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10174 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s16>) from %ir.pa)175 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s16>)176 ; RV64-NEXT: PseudoRET implicit $v8177 %va = load <vscale x 1 x i16>, ptr %pa178 ret <vscale x 1 x i16> %va179}180 181define <vscale x 2 x i16> @vload_nx2i16(ptr %pa) {182 ; RV32-LABEL: name: vload_nx2i16183 ; RV32: bb.1 (%ir-block.0):184 ; RV32-NEXT: liveins: $x10185 ; RV32-NEXT: {{ $}}186 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10187 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s16>) from %ir.pa)188 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s16>)189 ; RV32-NEXT: PseudoRET implicit $v8190 ;191 ; RV64-LABEL: name: vload_nx2i16192 ; RV64: bb.1 (%ir-block.0):193 ; RV64-NEXT: liveins: $x10194 ; RV64-NEXT: {{ $}}195 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10196 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s16>) from %ir.pa)197 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s16>)198 ; RV64-NEXT: PseudoRET implicit $v8199 %va = load <vscale x 2 x i16>, ptr %pa200 ret <vscale x 2 x i16> %va201}202 203define <vscale x 4 x i16> @vload_nx4i16(ptr %pa) {204 ; RV32-LABEL: name: vload_nx4i16205 ; RV32: bb.1 (%ir-block.0):206 ; RV32-NEXT: liveins: $x10207 ; RV32-NEXT: {{ $}}208 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10209 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)210 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)211 ; RV32-NEXT: PseudoRET implicit $v8212 ;213 ; RV64-LABEL: name: vload_nx4i16214 ; RV64: bb.1 (%ir-block.0):215 ; RV64-NEXT: liveins: $x10216 ; RV64-NEXT: {{ $}}217 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10218 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)219 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)220 ; RV64-NEXT: PseudoRET implicit $v8221 %va = load <vscale x 4 x i16>, ptr %pa222 ret <vscale x 4 x i16> %va223}224 225define <vscale x 8 x i16> @vload_nx8i16(ptr %pa) {226 ; RV32-LABEL: name: vload_nx8i16227 ; RV32: bb.1 (%ir-block.0):228 ; RV32-NEXT: liveins: $x10229 ; RV32-NEXT: {{ $}}230 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10231 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s16>) from %ir.pa)232 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 8 x s16>)233 ; RV32-NEXT: PseudoRET implicit $v8m2234 ;235 ; RV64-LABEL: name: vload_nx8i16236 ; RV64: bb.1 (%ir-block.0):237 ; RV64-NEXT: liveins: $x10238 ; RV64-NEXT: {{ $}}239 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10240 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s16>) from %ir.pa)241 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 8 x s16>)242 ; RV64-NEXT: PseudoRET implicit $v8m2243 %va = load <vscale x 8 x i16>, ptr %pa244 ret <vscale x 8 x i16> %va245}246 247define <vscale x 16 x i16> @vload_nx16i16(ptr %pa) {248 ; RV32-LABEL: name: vload_nx16i16249 ; RV32: bb.1 (%ir-block.0):250 ; RV32-NEXT: liveins: $x10251 ; RV32-NEXT: {{ $}}252 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10253 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s16>) from %ir.pa)254 ; RV32-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x s16>)255 ; RV32-NEXT: PseudoRET implicit $v8m4256 ;257 ; RV64-LABEL: name: vload_nx16i16258 ; RV64: bb.1 (%ir-block.0):259 ; RV64-NEXT: liveins: $x10260 ; RV64-NEXT: {{ $}}261 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10262 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s16>) from %ir.pa)263 ; RV64-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x s16>)264 ; RV64-NEXT: PseudoRET implicit $v8m4265 %va = load <vscale x 16 x i16>, ptr %pa266 ret <vscale x 16 x i16> %va267}268 269define <vscale x 32 x i16> @vload_nx32i16(ptr %pa) {270 ; RV32-LABEL: name: vload_nx32i16271 ; RV32: bb.1 (%ir-block.0):272 ; RV32-NEXT: liveins: $x10273 ; RV32-NEXT: {{ $}}274 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10275 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s16>) from %ir.pa)276 ; RV32-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 32 x s16>)277 ; RV32-NEXT: PseudoRET implicit $v8m8278 ;279 ; RV64-LABEL: name: vload_nx32i16280 ; RV64: bb.1 (%ir-block.0):281 ; RV64-NEXT: liveins: $x10282 ; RV64-NEXT: {{ $}}283 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10284 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s16>) from %ir.pa)285 ; RV64-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 32 x s16>)286 ; RV64-NEXT: PseudoRET implicit $v8m8287 %va = load <vscale x 32 x i16>, ptr %pa288 ret <vscale x 32 x i16> %va289}290 291define <vscale x 1 x i32> @vload_nx1i32(ptr %pa) {292 ; RV32-LABEL: name: vload_nx1i32293 ; RV32: bb.1 (%ir-block.0):294 ; RV32-NEXT: liveins: $x10295 ; RV32-NEXT: {{ $}}296 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10297 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s32>) from %ir.pa)298 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s32>)299 ; RV32-NEXT: PseudoRET implicit $v8300 ;301 ; RV64-LABEL: name: vload_nx1i32302 ; RV64: bb.1 (%ir-block.0):303 ; RV64-NEXT: liveins: $x10304 ; RV64-NEXT: {{ $}}305 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10306 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s32>) from %ir.pa)307 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s32>)308 ; RV64-NEXT: PseudoRET implicit $v8309 %va = load <vscale x 1 x i32>, ptr %pa310 ret <vscale x 1 x i32> %va311}312 313define <vscale x 2 x i32> @vload_nx2i32(ptr %pa) {314 ; RV32-LABEL: name: vload_nx2i32315 ; RV32: bb.1 (%ir-block.0):316 ; RV32-NEXT: liveins: $x10317 ; RV32-NEXT: {{ $}}318 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10319 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)320 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)321 ; RV32-NEXT: PseudoRET implicit $v8322 ;323 ; RV64-LABEL: name: vload_nx2i32324 ; RV64: bb.1 (%ir-block.0):325 ; RV64-NEXT: liveins: $x10326 ; RV64-NEXT: {{ $}}327 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10328 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)329 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)330 ; RV64-NEXT: PseudoRET implicit $v8331 %va = load <vscale x 2 x i32>, ptr %pa332 ret <vscale x 2 x i32> %va333}334 335define <vscale x 4 x i32> @vload_nx4i32(ptr %pa) {336 ; RV32-LABEL: name: vload_nx4i32337 ; RV32: bb.1 (%ir-block.0):338 ; RV32-NEXT: liveins: $x10339 ; RV32-NEXT: {{ $}}340 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10341 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s32>) from %ir.pa)342 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 4 x s32>)343 ; RV32-NEXT: PseudoRET implicit $v8m2344 ;345 ; RV64-LABEL: name: vload_nx4i32346 ; RV64: bb.1 (%ir-block.0):347 ; RV64-NEXT: liveins: $x10348 ; RV64-NEXT: {{ $}}349 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10350 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s32>) from %ir.pa)351 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 4 x s32>)352 ; RV64-NEXT: PseudoRET implicit $v8m2353 %va = load <vscale x 4 x i32>, ptr %pa354 ret <vscale x 4 x i32> %va355}356 357define <vscale x 8 x i32> @vload_nx8i32(ptr %pa) {358 ; RV32-LABEL: name: vload_nx8i32359 ; RV32: bb.1 (%ir-block.0):360 ; RV32-NEXT: liveins: $x10361 ; RV32-NEXT: {{ $}}362 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10363 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s32>) from %ir.pa)364 ; RV32-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x s32>)365 ; RV32-NEXT: PseudoRET implicit $v8m4366 ;367 ; RV64-LABEL: name: vload_nx8i32368 ; RV64: bb.1 (%ir-block.0):369 ; RV64-NEXT: liveins: $x10370 ; RV64-NEXT: {{ $}}371 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10372 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s32>) from %ir.pa)373 ; RV64-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x s32>)374 ; RV64-NEXT: PseudoRET implicit $v8m4375 %va = load <vscale x 8 x i32>, ptr %pa376 ret <vscale x 8 x i32> %va377}378 379define <vscale x 16 x i32> @vload_nx16i32(ptr %pa) {380 ; RV32-LABEL: name: vload_nx16i32381 ; RV32: bb.1 (%ir-block.0):382 ; RV32-NEXT: liveins: $x10383 ; RV32-NEXT: {{ $}}384 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10385 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s32>) from %ir.pa)386 ; RV32-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 16 x s32>)387 ; RV32-NEXT: PseudoRET implicit $v8m8388 ;389 ; RV64-LABEL: name: vload_nx16i32390 ; RV64: bb.1 (%ir-block.0):391 ; RV64-NEXT: liveins: $x10392 ; RV64-NEXT: {{ $}}393 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10394 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s32>) from %ir.pa)395 ; RV64-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 16 x s32>)396 ; RV64-NEXT: PseudoRET implicit $v8m8397 %va = load <vscale x 16 x i32>, ptr %pa398 ret <vscale x 16 x i32> %va399}400 401define <vscale x 1 x i64> @vload_nx1i64(ptr %pa) {402 ; RV32-LABEL: name: vload_nx1i64403 ; RV32: bb.1 (%ir-block.0):404 ; RV32-NEXT: liveins: $x10405 ; RV32-NEXT: {{ $}}406 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10407 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s64>) from %ir.pa)408 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s64>)409 ; RV32-NEXT: PseudoRET implicit $v8410 ;411 ; RV64-LABEL: name: vload_nx1i64412 ; RV64: bb.1 (%ir-block.0):413 ; RV64-NEXT: liveins: $x10414 ; RV64-NEXT: {{ $}}415 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10416 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s64>) from %ir.pa)417 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s64>)418 ; RV64-NEXT: PseudoRET implicit $v8419 %va = load <vscale x 1 x i64>, ptr %pa420 ret <vscale x 1 x i64> %va421}422 423define <vscale x 2 x i64> @vload_nx2i64(ptr %pa) {424 ; RV32-LABEL: name: vload_nx2i64425 ; RV32: bb.1 (%ir-block.0):426 ; RV32-NEXT: liveins: $x10427 ; RV32-NEXT: {{ $}}428 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10429 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)430 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)431 ; RV32-NEXT: PseudoRET implicit $v8m2432 ;433 ; RV64-LABEL: name: vload_nx2i64434 ; RV64: bb.1 (%ir-block.0):435 ; RV64-NEXT: liveins: $x10436 ; RV64-NEXT: {{ $}}437 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10438 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)439 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)440 ; RV64-NEXT: PseudoRET implicit $v8m2441 %va = load <vscale x 2 x i64>, ptr %pa442 ret <vscale x 2 x i64> %va443}444 445define <vscale x 4 x i64> @vload_nx4i64(ptr %pa) {446 ; RV32-LABEL: name: vload_nx4i64447 ; RV32: bb.1 (%ir-block.0):448 ; RV32-NEXT: liveins: $x10449 ; RV32-NEXT: {{ $}}450 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10451 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s64>) from %ir.pa)452 ; RV32-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 4 x s64>)453 ; RV32-NEXT: PseudoRET implicit $v8m4454 ;455 ; RV64-LABEL: name: vload_nx4i64456 ; RV64: bb.1 (%ir-block.0):457 ; RV64-NEXT: liveins: $x10458 ; RV64-NEXT: {{ $}}459 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10460 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s64>) from %ir.pa)461 ; RV64-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 4 x s64>)462 ; RV64-NEXT: PseudoRET implicit $v8m4463 %va = load <vscale x 4 x i64>, ptr %pa464 ret <vscale x 4 x i64> %va465}466 467define <vscale x 8 x i64> @vload_nx8i64(ptr %pa) {468 ; RV32-LABEL: name: vload_nx8i64469 ; RV32: bb.1 (%ir-block.0):470 ; RV32-NEXT: liveins: $x10471 ; RV32-NEXT: {{ $}}472 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10473 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s64>) from %ir.pa)474 ; RV32-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 8 x s64>)475 ; RV32-NEXT: PseudoRET implicit $v8m8476 ;477 ; RV64-LABEL: name: vload_nx8i64478 ; RV64: bb.1 (%ir-block.0):479 ; RV64-NEXT: liveins: $x10480 ; RV64-NEXT: {{ $}}481 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10482 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s64>) from %ir.pa)483 ; RV64-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 8 x s64>)484 ; RV64-NEXT: PseudoRET implicit $v8m8485 %va = load <vscale x 8 x i64>, ptr %pa486 ret <vscale x 8 x i64> %va487}488 489define <vscale x 16 x i8> @vload_nx16i8_align1(ptr %pa) {490 ; RV32-LABEL: name: vload_nx16i8_align1491 ; RV32: bb.1 (%ir-block.0):492 ; RV32-NEXT: liveins: $x10493 ; RV32-NEXT: {{ $}}494 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10495 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)496 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)497 ; RV32-NEXT: PseudoRET implicit $v8m2498 ;499 ; RV64-LABEL: name: vload_nx16i8_align1500 ; RV64: bb.1 (%ir-block.0):501 ; RV64-NEXT: liveins: $x10502 ; RV64-NEXT: {{ $}}503 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10504 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)505 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)506 ; RV64-NEXT: PseudoRET implicit $v8m2507 %va = load <vscale x 16 x i8>, ptr %pa, align 1508 ret <vscale x 16 x i8> %va509}510 511define <vscale x 16 x i8> @vload_nx16i8_align2(ptr %pa) {512 ; RV32-LABEL: name: vload_nx16i8_align2513 ; RV32: bb.1 (%ir-block.0):514 ; RV32-NEXT: liveins: $x10515 ; RV32-NEXT: {{ $}}516 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10517 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)518 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)519 ; RV32-NEXT: PseudoRET implicit $v8m2520 ;521 ; RV64-LABEL: name: vload_nx16i8_align2522 ; RV64: bb.1 (%ir-block.0):523 ; RV64-NEXT: liveins: $x10524 ; RV64-NEXT: {{ $}}525 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10526 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)527 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)528 ; RV64-NEXT: PseudoRET implicit $v8m2529 %va = load <vscale x 16 x i8>, ptr %pa, align 2530 ret <vscale x 16 x i8> %va531}532 533define <vscale x 16 x i8> @vload_nx16i8_align16(ptr %pa) {534 ; RV32-LABEL: name: vload_nx16i8_align16535 ; RV32: bb.1 (%ir-block.0):536 ; RV32-NEXT: liveins: $x10537 ; RV32-NEXT: {{ $}}538 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10539 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)540 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)541 ; RV32-NEXT: PseudoRET implicit $v8m2542 ;543 ; RV64-LABEL: name: vload_nx16i8_align16544 ; RV64: bb.1 (%ir-block.0):545 ; RV64-NEXT: liveins: $x10546 ; RV64-NEXT: {{ $}}547 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10548 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)549 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)550 ; RV64-NEXT: PseudoRET implicit $v8m2551 %va = load <vscale x 16 x i8>, ptr %pa, align 16552 ret <vscale x 16 x i8> %va553}554 555define <vscale x 16 x i8> @vload_nx16i8_align64(ptr %pa) {556 ; RV32-LABEL: name: vload_nx16i8_align64557 ; RV32: bb.1 (%ir-block.0):558 ; RV32-NEXT: liveins: $x10559 ; RV32-NEXT: {{ $}}560 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10561 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)562 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)563 ; RV32-NEXT: PseudoRET implicit $v8m2564 ;565 ; RV64-LABEL: name: vload_nx16i8_align64566 ; RV64: bb.1 (%ir-block.0):567 ; RV64-NEXT: liveins: $x10568 ; RV64-NEXT: {{ $}}569 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10570 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)571 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)572 ; RV64-NEXT: PseudoRET implicit $v8m2573 %va = load <vscale x 16 x i8>, ptr %pa, align 64574 ret <vscale x 16 x i8> %va575}576 577define <vscale x 4 x i16> @vload_nx4i16_align1(ptr %pa) {578 ; RV32-LABEL: name: vload_nx4i16_align1579 ; RV32: bb.1 (%ir-block.0):580 ; RV32-NEXT: liveins: $x10581 ; RV32-NEXT: {{ $}}582 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10583 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 1)584 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)585 ; RV32-NEXT: PseudoRET implicit $v8586 ;587 ; RV64-LABEL: name: vload_nx4i16_align1588 ; RV64: bb.1 (%ir-block.0):589 ; RV64-NEXT: liveins: $x10590 ; RV64-NEXT: {{ $}}591 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10592 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 1)593 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)594 ; RV64-NEXT: PseudoRET implicit $v8595 %va = load <vscale x 4 x i16>, ptr %pa, align 1596 ret <vscale x 4 x i16> %va597}598 599define <vscale x 4 x i16> @vload_nx4i16_align2(ptr %pa) {600 ; RV32-LABEL: name: vload_nx4i16_align2601 ; RV32: bb.1 (%ir-block.0):602 ; RV32-NEXT: liveins: $x10603 ; RV32-NEXT: {{ $}}604 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10605 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)606 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)607 ; RV32-NEXT: PseudoRET implicit $v8608 ;609 ; RV64-LABEL: name: vload_nx4i16_align2610 ; RV64: bb.1 (%ir-block.0):611 ; RV64-NEXT: liveins: $x10612 ; RV64-NEXT: {{ $}}613 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10614 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)615 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)616 ; RV64-NEXT: PseudoRET implicit $v8617 %va = load <vscale x 4 x i16>, ptr %pa, align 2618 ret <vscale x 4 x i16> %va619}620 621define <vscale x 4 x i16> @vload_nx4i16_align4(ptr %pa) {622 ; RV32-LABEL: name: vload_nx4i16_align4623 ; RV32: bb.1 (%ir-block.0):624 ; RV32-NEXT: liveins: $x10625 ; RV32-NEXT: {{ $}}626 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10627 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)628 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)629 ; RV32-NEXT: PseudoRET implicit $v8630 ;631 ; RV64-LABEL: name: vload_nx4i16_align4632 ; RV64: bb.1 (%ir-block.0):633 ; RV64-NEXT: liveins: $x10634 ; RV64-NEXT: {{ $}}635 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10636 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)637 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)638 ; RV64-NEXT: PseudoRET implicit $v8639 %va = load <vscale x 4 x i16>, ptr %pa, align 4640 ret <vscale x 4 x i16> %va641}642define <vscale x 4 x i16> @vload_nx4i16_align8(ptr %pa) {643 ; RV32-LABEL: name: vload_nx4i16_align8644 ; RV32: bb.1 (%ir-block.0):645 ; RV32-NEXT: liveins: $x10646 ; RV32-NEXT: {{ $}}647 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10648 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)649 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)650 ; RV32-NEXT: PseudoRET implicit $v8651 ;652 ; RV64-LABEL: name: vload_nx4i16_align8653 ; RV64: bb.1 (%ir-block.0):654 ; RV64-NEXT: liveins: $x10655 ; RV64-NEXT: {{ $}}656 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10657 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)658 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)659 ; RV64-NEXT: PseudoRET implicit $v8660 %va = load <vscale x 4 x i16>, ptr %pa, align 8661 ret <vscale x 4 x i16> %va662}663 664define <vscale x 4 x i16> @vload_nx4i16_align16(ptr %pa) {665 ; RV32-LABEL: name: vload_nx4i16_align16666 ; RV32: bb.1 (%ir-block.0):667 ; RV32-NEXT: liveins: $x10668 ; RV32-NEXT: {{ $}}669 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10670 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)671 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)672 ; RV32-NEXT: PseudoRET implicit $v8673 ;674 ; RV64-LABEL: name: vload_nx4i16_align16675 ; RV64: bb.1 (%ir-block.0):676 ; RV64-NEXT: liveins: $x10677 ; RV64-NEXT: {{ $}}678 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10679 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)680 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)681 ; RV64-NEXT: PseudoRET implicit $v8682 %va = load <vscale x 4 x i16>, ptr %pa, align 16683 ret <vscale x 4 x i16> %va684}685 686define <vscale x 2 x i32> @vload_nx2i32_align2(ptr %pa) {687 ; RV32-LABEL: name: vload_nx2i32_align2688 ; RV32: bb.1 (%ir-block.0):689 ; RV32-NEXT: liveins: $x10690 ; RV32-NEXT: {{ $}}691 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10692 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 2)693 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)694 ; RV32-NEXT: PseudoRET implicit $v8695 ;696 ; RV64-LABEL: name: vload_nx2i32_align2697 ; RV64: bb.1 (%ir-block.0):698 ; RV64-NEXT: liveins: $x10699 ; RV64-NEXT: {{ $}}700 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10701 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 2)702 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)703 ; RV64-NEXT: PseudoRET implicit $v8704 %va = load <vscale x 2 x i32>, ptr %pa, align 2705 ret <vscale x 2 x i32> %va706}707 708define <vscale x 2 x i32> @vload_nx2i32_align4(ptr %pa) {709 ; RV32-LABEL: name: vload_nx2i32_align4710 ; RV32: bb.1 (%ir-block.0):711 ; RV32-NEXT: liveins: $x10712 ; RV32-NEXT: {{ $}}713 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10714 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)715 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)716 ; RV32-NEXT: PseudoRET implicit $v8717 ;718 ; RV64-LABEL: name: vload_nx2i32_align4719 ; RV64: bb.1 (%ir-block.0):720 ; RV64-NEXT: liveins: $x10721 ; RV64-NEXT: {{ $}}722 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10723 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)724 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)725 ; RV64-NEXT: PseudoRET implicit $v8726 %va = load <vscale x 2 x i32>, ptr %pa, align 4727 ret <vscale x 2 x i32> %va728}729 730define <vscale x 2 x i32> @vload_nx2i32_align8(ptr %pa) {731 ; RV32-LABEL: name: vload_nx2i32_align8732 ; RV32: bb.1 (%ir-block.0):733 ; RV32-NEXT: liveins: $x10734 ; RV32-NEXT: {{ $}}735 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10736 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)737 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)738 ; RV32-NEXT: PseudoRET implicit $v8739 ;740 ; RV64-LABEL: name: vload_nx2i32_align8741 ; RV64: bb.1 (%ir-block.0):742 ; RV64-NEXT: liveins: $x10743 ; RV64-NEXT: {{ $}}744 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10745 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)746 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)747 ; RV64-NEXT: PseudoRET implicit $v8748 %va = load <vscale x 2 x i32>, ptr %pa, align 8749 ret <vscale x 2 x i32> %va750}751 752define <vscale x 2 x i32> @vload_nx2i32_align16(ptr %pa) {753 ; RV32-LABEL: name: vload_nx2i32_align16754 ; RV32: bb.1 (%ir-block.0):755 ; RV32-NEXT: liveins: $x10756 ; RV32-NEXT: {{ $}}757 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10758 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)759 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)760 ; RV32-NEXT: PseudoRET implicit $v8761 ;762 ; RV64-LABEL: name: vload_nx2i32_align16763 ; RV64: bb.1 (%ir-block.0):764 ; RV64-NEXT: liveins: $x10765 ; RV64-NEXT: {{ $}}766 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10767 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)768 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)769 ; RV64-NEXT: PseudoRET implicit $v8770 %va = load <vscale x 2 x i32>, ptr %pa, align 16771 ret <vscale x 2 x i32> %va772}773 774define <vscale x 2 x i32> @vload_nx2i32_align256(ptr %pa) {775 ; RV32-LABEL: name: vload_nx2i32_align256776 ; RV32: bb.1 (%ir-block.0):777 ; RV32-NEXT: liveins: $x10778 ; RV32-NEXT: {{ $}}779 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10780 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)781 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)782 ; RV32-NEXT: PseudoRET implicit $v8783 ;784 ; RV64-LABEL: name: vload_nx2i32_align256785 ; RV64: bb.1 (%ir-block.0):786 ; RV64-NEXT: liveins: $x10787 ; RV64-NEXT: {{ $}}788 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10789 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)790 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)791 ; RV64-NEXT: PseudoRET implicit $v8792 %va = load <vscale x 2 x i32>, ptr %pa, align 256793 ret <vscale x 2 x i32> %va794}795define <vscale x 2 x i64> @vload_nx2i64_align4(ptr %pa) {796 ; RV32-LABEL: name: vload_nx2i64_align4797 ; RV32: bb.1 (%ir-block.0):798 ; RV32-NEXT: liveins: $x10799 ; RV32-NEXT: {{ $}}800 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10801 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 4)802 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)803 ; RV32-NEXT: PseudoRET implicit $v8m2804 ;805 ; RV64-LABEL: name: vload_nx2i64_align4806 ; RV64: bb.1 (%ir-block.0):807 ; RV64-NEXT: liveins: $x10808 ; RV64-NEXT: {{ $}}809 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10810 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 4)811 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)812 ; RV64-NEXT: PseudoRET implicit $v8m2813 %va = load <vscale x 2 x i64>, ptr %pa, align 4814 ret <vscale x 2 x i64> %va815}816 817define <vscale x 2 x i64> @vload_nx2i64_align8(ptr %pa) {818 ; RV32-LABEL: name: vload_nx2i64_align8819 ; RV32: bb.1 (%ir-block.0):820 ; RV32-NEXT: liveins: $x10821 ; RV32-NEXT: {{ $}}822 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10823 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)824 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)825 ; RV32-NEXT: PseudoRET implicit $v8m2826 ;827 ; RV64-LABEL: name: vload_nx2i64_align8828 ; RV64: bb.1 (%ir-block.0):829 ; RV64-NEXT: liveins: $x10830 ; RV64-NEXT: {{ $}}831 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10832 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)833 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)834 ; RV64-NEXT: PseudoRET implicit $v8m2835 %va = load <vscale x 2 x i64>, ptr %pa, align 8836 ret <vscale x 2 x i64> %va837}838 839define <vscale x 2 x i64> @vload_nx2i64_align16(ptr %pa) {840 ; RV32-LABEL: name: vload_nx2i64_align16841 ; RV32: bb.1 (%ir-block.0):842 ; RV32-NEXT: liveins: $x10843 ; RV32-NEXT: {{ $}}844 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10845 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)846 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)847 ; RV32-NEXT: PseudoRET implicit $v8m2848 ;849 ; RV64-LABEL: name: vload_nx2i64_align16850 ; RV64: bb.1 (%ir-block.0):851 ; RV64-NEXT: liveins: $x10852 ; RV64-NEXT: {{ $}}853 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10854 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)855 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)856 ; RV64-NEXT: PseudoRET implicit $v8m2857 %va = load <vscale x 2 x i64>, ptr %pa, align 16858 ret <vscale x 2 x i64> %va859}860 861define <vscale x 2 x i64> @vload_nx2i64_align32(ptr %pa) {862 ; RV32-LABEL: name: vload_nx2i64_align32863 ; RV32: bb.1 (%ir-block.0):864 ; RV32-NEXT: liveins: $x10865 ; RV32-NEXT: {{ $}}866 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10867 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)868 ; RV32-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)869 ; RV32-NEXT: PseudoRET implicit $v8m2870 ;871 ; RV64-LABEL: name: vload_nx2i64_align32872 ; RV64: bb.1 (%ir-block.0):873 ; RV64-NEXT: liveins: $x10874 ; RV64-NEXT: {{ $}}875 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10876 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)877 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)878 ; RV64-NEXT: PseudoRET implicit $v8m2879 %va = load <vscale x 2 x i64>, ptr %pa, align 32880 ret <vscale x 2 x i64> %va881}882 883define <vscale x 1 x ptr> @vload_nx1ptr(ptr %pa) {884 ; RV32-LABEL: name: vload_nx1ptr885 ; RV32: bb.1 (%ir-block.0):886 ; RV32-NEXT: liveins: $x10887 ; RV32-NEXT: {{ $}}888 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10889 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>) from %ir.pa)890 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)891 ; RV32-NEXT: PseudoRET implicit $v8892 ;893 ; RV64-LABEL: name: vload_nx1ptr894 ; RV64: bb.1 (%ir-block.0):895 ; RV64-NEXT: liveins: $x10896 ; RV64-NEXT: {{ $}}897 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10898 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>) from %ir.pa)899 ; RV64-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)900 ; RV64-NEXT: PseudoRET implicit $v8901 %va = load <vscale x 1 x ptr>, ptr %pa902 ret <vscale x 1 x ptr> %va903}904 905define <vscale x 2 x ptr> @vload_nx2ptr(ptr %pa) {906 ; RV32-LABEL: name: vload_nx2ptr907 ; RV32: bb.1 (%ir-block.0):908 ; RV32-NEXT: liveins: $x10909 ; RV32-NEXT: {{ $}}910 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10911 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>) from %ir.pa)912 ; RV32-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)913 ; RV32-NEXT: PseudoRET implicit $v8914 ;915 ; RV64-LABEL: name: vload_nx2ptr916 ; RV64: bb.1 (%ir-block.0):917 ; RV64-NEXT: liveins: $x10918 ; RV64-NEXT: {{ $}}919 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10920 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>) from %ir.pa)921 ; RV64-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x p0>)922 ; RV64-NEXT: PseudoRET implicit $v8m2923 %va = load <vscale x 2x ptr>, ptr %pa924 ret <vscale x 2 x ptr> %va925}926 927define <vscale x 8 x ptr> @vload_nx8ptr(ptr %pa) {928 ; RV32-LABEL: name: vload_nx8ptr929 ; RV32: bb.1 (%ir-block.0):930 ; RV32-NEXT: liveins: $x10931 ; RV32-NEXT: {{ $}}932 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10933 ; RV32-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>) from %ir.pa)934 ; RV32-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)935 ; RV32-NEXT: PseudoRET implicit $v8m4936 ;937 ; RV64-LABEL: name: vload_nx8ptr938 ; RV64: bb.1 (%ir-block.0):939 ; RV64-NEXT: liveins: $x10940 ; RV64-NEXT: {{ $}}941 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10942 ; RV64-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>) from %ir.pa)943 ; RV64-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 8 x p0>)944 ; RV64-NEXT: PseudoRET implicit $v8m8945 %va = load <vscale x 8 x ptr>, ptr %pa946 ret <vscale x 8 x ptr> %va947}948 949