810 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=irtranslator \3; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV32 %s4; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfbfmin,+zvfhmin -global-isel -stop-after=irtranslator \5; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=RV64 %s6 7; ==========================================================================8; ============================= Scalable Types =============================9; ==========================================================================10 11define <vscale x 1 x i8> @test_ret_nxv1i8() {12 ; RV32-LABEL: name: test_ret_nxv1i813 ; RV32: bb.1.entry:14 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF15 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s8>)16 ; RV32-NEXT: PseudoRET implicit $v817 ;18 ; RV64-LABEL: name: test_ret_nxv1i819 ; RV64: bb.1.entry:20 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF21 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s8>)22 ; RV64-NEXT: PseudoRET implicit $v823entry:24 ret <vscale x 1 x i8> poison25}26 27define <vscale x 2 x i8> @test_ret_nxv2i8() {28 ; RV32-LABEL: name: test_ret_nxv2i829 ; RV32: bb.1.entry:30 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF31 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s8>)32 ; RV32-NEXT: PseudoRET implicit $v833 ;34 ; RV64-LABEL: name: test_ret_nxv2i835 ; RV64: bb.1.entry:36 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF37 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s8>)38 ; RV64-NEXT: PseudoRET implicit $v839entry:40 ret <vscale x 2 x i8> poison41}42 43define <vscale x 4 x i8> @test_ret_nxv4i8() {44 ; RV32-LABEL: name: test_ret_nxv4i845 ; RV32: bb.1.entry:46 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF47 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s8>)48 ; RV32-NEXT: PseudoRET implicit $v849 ;50 ; RV64-LABEL: name: test_ret_nxv4i851 ; RV64: bb.1.entry:52 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF53 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s8>)54 ; RV64-NEXT: PseudoRET implicit $v855entry:56 ret <vscale x 4 x i8> poison57}58 59define <vscale x 8 x i8> @test_ret_nxv8i8() {60 ; RV32-LABEL: name: test_ret_nxv8i861 ; RV32: bb.1.entry:62 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF63 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 8 x s8>)64 ; RV32-NEXT: PseudoRET implicit $v865 ;66 ; RV64-LABEL: name: test_ret_nxv8i867 ; RV64: bb.1.entry:68 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF69 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 8 x s8>)70 ; RV64-NEXT: PseudoRET implicit $v871entry:72 ret <vscale x 8 x i8> poison73}74 75define <vscale x 16 x i8> @test_ret_nxv16i8() {76 ; RV32-LABEL: name: test_ret_nxv16i877 ; RV32: bb.1.entry:78 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF79 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 16 x s8>)80 ; RV32-NEXT: PseudoRET implicit $v8m281 ;82 ; RV64-LABEL: name: test_ret_nxv16i883 ; RV64: bb.1.entry:84 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s8>) = G_IMPLICIT_DEF85 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 16 x s8>)86 ; RV64-NEXT: PseudoRET implicit $v8m287entry:88 ret <vscale x 16 x i8> poison89}90 91define <vscale x 32 x i8> @test_ret_nxv32i8() {92 ; RV32-LABEL: name: test_ret_nxv32i893 ; RV32: bb.1.entry:94 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF95 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 32 x s8>)96 ; RV32-NEXT: PseudoRET implicit $v8m497 ;98 ; RV64-LABEL: name: test_ret_nxv32i899 ; RV64: bb.1.entry:100 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s8>) = G_IMPLICIT_DEF101 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 32 x s8>)102 ; RV64-NEXT: PseudoRET implicit $v8m4103entry:104 ret <vscale x 32 x i8> poison105}106 107define <vscale x 64 x i8> @test_ret_nxv64i8() {108 ; RV32-LABEL: name: test_ret_nxv64i8109 ; RV32: bb.1.entry:110 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF111 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 64 x s8>)112 ; RV32-NEXT: PseudoRET implicit $v8m8113 ;114 ; RV64-LABEL: name: test_ret_nxv64i8115 ; RV64: bb.1.entry:116 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 64 x s8>) = G_IMPLICIT_DEF117 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 64 x s8>)118 ; RV64-NEXT: PseudoRET implicit $v8m8119entry:120 ret <vscale x 64 x i8> poison121}122 123define <vscale x 1 x i16> @test_ret_nxv1i16() {124 ; RV32-LABEL: name: test_ret_nxv1i16125 ; RV32: bb.1.entry:126 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF127 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s16>)128 ; RV32-NEXT: PseudoRET implicit $v8129 ;130 ; RV64-LABEL: name: test_ret_nxv1i16131 ; RV64: bb.1.entry:132 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF133 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s16>)134 ; RV64-NEXT: PseudoRET implicit $v8135entry:136 ret <vscale x 1 x i16> poison137}138 139define <vscale x 2 x i16> @test_ret_nxv2i16() {140 ; RV32-LABEL: name: test_ret_nxv2i16141 ; RV32: bb.1.entry:142 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF143 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s16>)144 ; RV32-NEXT: PseudoRET implicit $v8145 ;146 ; RV64-LABEL: name: test_ret_nxv2i16147 ; RV64: bb.1.entry:148 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF149 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s16>)150 ; RV64-NEXT: PseudoRET implicit $v8151entry:152 ret <vscale x 2 x i16> poison153}154 155define <vscale x 4 x i16> @test_ret_nxv4i16() {156 ; RV32-LABEL: name: test_ret_nxv4i16157 ; RV32: bb.1.entry:158 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF159 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s16>)160 ; RV32-NEXT: PseudoRET implicit $v8161 ;162 ; RV64-LABEL: name: test_ret_nxv4i16163 ; RV64: bb.1.entry:164 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF165 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s16>)166 ; RV64-NEXT: PseudoRET implicit $v8167entry:168 ret <vscale x 4 x i16> poison169}170 171define <vscale x 8 x i16> @test_ret_nxv8i16() {172 ; RV32-LABEL: name: test_ret_nxv8i16173 ; RV32: bb.1.entry:174 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF175 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 8 x s16>)176 ; RV32-NEXT: PseudoRET implicit $v8m2177 ;178 ; RV64-LABEL: name: test_ret_nxv8i16179 ; RV64: bb.1.entry:180 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF181 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 8 x s16>)182 ; RV64-NEXT: PseudoRET implicit $v8m2183entry:184 ret <vscale x 8 x i16> poison185}186 187define <vscale x 16 x i16> @test_ret_nxv16i16() {188 ; RV32-LABEL: name: test_ret_nxv16i16189 ; RV32: bb.1.entry:190 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF191 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 16 x s16>)192 ; RV32-NEXT: PseudoRET implicit $v8m4193 ;194 ; RV64-LABEL: name: test_ret_nxv16i16195 ; RV64: bb.1.entry:196 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF197 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 16 x s16>)198 ; RV64-NEXT: PseudoRET implicit $v8m4199entry:200 ret <vscale x 16 x i16> poison201}202 203define <vscale x 32 x i16> @test_ret_nxv32i16() {204 ; RV32-LABEL: name: test_ret_nxv32i16205 ; RV32: bb.1.entry:206 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF207 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 32 x s16>)208 ; RV32-NEXT: PseudoRET implicit $v8m8209 ;210 ; RV64-LABEL: name: test_ret_nxv32i16211 ; RV64: bb.1.entry:212 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF213 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 32 x s16>)214 ; RV64-NEXT: PseudoRET implicit $v8m8215entry:216 ret <vscale x 32 x i16> poison217}218 219define <vscale x 1 x i32> @test_ret_nxv1i32() {220 ; RV32-LABEL: name: test_ret_nxv1i32221 ; RV32: bb.1.entry:222 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF223 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s32>)224 ; RV32-NEXT: PseudoRET implicit $v8225 ;226 ; RV64-LABEL: name: test_ret_nxv1i32227 ; RV64: bb.1.entry:228 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF229 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s32>)230 ; RV64-NEXT: PseudoRET implicit $v8231entry:232 ret <vscale x 1 x i32> poison233}234 235define <vscale x 2 x i32> @test_ret_nxv2i32() {236 ; RV32-LABEL: name: test_ret_nxv2i32237 ; RV32: bb.1.entry:238 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF239 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s32>)240 ; RV32-NEXT: PseudoRET implicit $v8241 ;242 ; RV64-LABEL: name: test_ret_nxv2i32243 ; RV64: bb.1.entry:244 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF245 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s32>)246 ; RV64-NEXT: PseudoRET implicit $v8247entry:248 ret <vscale x 2 x i32> poison249}250 251define <vscale x 4 x i32> @test_ret_nxv4i32() {252 ; RV32-LABEL: name: test_ret_nxv4i32253 ; RV32: bb.1.entry:254 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF255 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 4 x s32>)256 ; RV32-NEXT: PseudoRET implicit $v8m2257 ;258 ; RV64-LABEL: name: test_ret_nxv4i32259 ; RV64: bb.1.entry:260 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF261 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 4 x s32>)262 ; RV64-NEXT: PseudoRET implicit $v8m2263entry:264 ret <vscale x 4 x i32> poison265}266 267define <vscale x 8 x i32> @test_ret_nxv8i32() {268 ; RV32-LABEL: name: test_ret_nxv8i32269 ; RV32: bb.1.entry:270 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF271 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 8 x s32>)272 ; RV32-NEXT: PseudoRET implicit $v8m4273 ;274 ; RV64-LABEL: name: test_ret_nxv8i32275 ; RV64: bb.1.entry:276 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF277 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 8 x s32>)278 ; RV64-NEXT: PseudoRET implicit $v8m4279entry:280 ret <vscale x 8 x i32> poison281}282 283define <vscale x 16 x i32> @test_ret_nxv16i32() {284 ; RV32-LABEL: name: test_ret_nxv16i32285 ; RV32: bb.1.entry:286 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF287 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 16 x s32>)288 ; RV32-NEXT: PseudoRET implicit $v8m8289 ;290 ; RV64-LABEL: name: test_ret_nxv16i32291 ; RV64: bb.1.entry:292 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF293 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 16 x s32>)294 ; RV64-NEXT: PseudoRET implicit $v8m8295entry:296 ret <vscale x 16 x i32> poison297}298 299define <vscale x 1 x i64> @test_ret_nxv1i64() {300 ; RV32-LABEL: name: test_ret_nxv1i64301 ; RV32: bb.1.entry:302 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF303 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s64>)304 ; RV32-NEXT: PseudoRET implicit $v8305 ;306 ; RV64-LABEL: name: test_ret_nxv1i64307 ; RV64: bb.1.entry:308 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF309 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s64>)310 ; RV64-NEXT: PseudoRET implicit $v8311entry:312 ret <vscale x 1 x i64> poison313}314 315define <vscale x 2 x i64> @test_ret_nxv2i64() {316 ; RV32-LABEL: name: test_ret_nxv2i64317 ; RV32: bb.1.entry:318 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF319 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 2 x s64>)320 ; RV32-NEXT: PseudoRET implicit $v8m2321 ;322 ; RV64-LABEL: name: test_ret_nxv2i64323 ; RV64: bb.1.entry:324 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF325 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 2 x s64>)326 ; RV64-NEXT: PseudoRET implicit $v8m2327entry:328 ret <vscale x 2 x i64> poison329}330 331define <vscale x 4 x i64> @test_ret_nxv4i64() {332 ; RV32-LABEL: name: test_ret_nxv4i64333 ; RV32: bb.1.entry:334 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF335 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 4 x s64>)336 ; RV32-NEXT: PseudoRET implicit $v8m4337 ;338 ; RV64-LABEL: name: test_ret_nxv4i64339 ; RV64: bb.1.entry:340 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF341 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 4 x s64>)342 ; RV64-NEXT: PseudoRET implicit $v8m4343entry:344 ret <vscale x 4 x i64> poison345}346 347define <vscale x 8 x i64> @test_ret_nxv8i64() {348 ; RV32-LABEL: name: test_ret_nxv8i64349 ; RV32: bb.1.entry:350 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF351 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 8 x s64>)352 ; RV32-NEXT: PseudoRET implicit $v8m8353 ;354 ; RV64-LABEL: name: test_ret_nxv8i64355 ; RV64: bb.1.entry:356 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF357 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 8 x s64>)358 ; RV64-NEXT: PseudoRET implicit $v8m8359entry:360 ret <vscale x 8 x i64> poison361}362 363define <vscale x 64 x i1> @test_ret_nxv64i1() {364 ; RV32-LABEL: name: test_ret_nxv64i1365 ; RV32: bb.1.entry:366 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF367 ; RV32-NEXT: $v0 = COPY [[DEF]](<vscale x 64 x s1>)368 ; RV32-NEXT: PseudoRET implicit $v0369 ;370 ; RV64-LABEL: name: test_ret_nxv64i1371 ; RV64: bb.1.entry:372 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF373 ; RV64-NEXT: $v0 = COPY [[DEF]](<vscale x 64 x s1>)374 ; RV64-NEXT: PseudoRET implicit $v0375entry:376 ret <vscale x 64 x i1> poison377}378 379define <vscale x 32 x i1> @test_ret_nxv32i1() {380 ; RV32-LABEL: name: test_ret_nxv32i1381 ; RV32: bb.1.entry:382 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF383 ; RV32-NEXT: $v0 = COPY [[DEF]](<vscale x 32 x s1>)384 ; RV32-NEXT: PseudoRET implicit $v0385 ;386 ; RV64-LABEL: name: test_ret_nxv32i1387 ; RV64: bb.1.entry:388 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF389 ; RV64-NEXT: $v0 = COPY [[DEF]](<vscale x 32 x s1>)390 ; RV64-NEXT: PseudoRET implicit $v0391entry:392 ret <vscale x 32 x i1> poison393}394 395define <vscale x 16 x i1> @test_ret_nxv16i1() {396 ; RV32-LABEL: name: test_ret_nxv16i1397 ; RV32: bb.1.entry:398 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF399 ; RV32-NEXT: $v0 = COPY [[DEF]](<vscale x 16 x s1>)400 ; RV32-NEXT: PseudoRET implicit $v0401 ;402 ; RV64-LABEL: name: test_ret_nxv16i1403 ; RV64: bb.1.entry:404 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF405 ; RV64-NEXT: $v0 = COPY [[DEF]](<vscale x 16 x s1>)406 ; RV64-NEXT: PseudoRET implicit $v0407entry:408 ret <vscale x 16 x i1> poison409}410 411define <vscale x 8 x i1> @test_ret_nxv8i1() {412 ; RV32-LABEL: name: test_ret_nxv8i1413 ; RV32: bb.1.entry:414 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF415 ; RV32-NEXT: $v0 = COPY [[DEF]](<vscale x 8 x s1>)416 ; RV32-NEXT: PseudoRET implicit $v0417 ;418 ; RV64-LABEL: name: test_ret_nxv8i1419 ; RV64: bb.1.entry:420 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF421 ; RV64-NEXT: $v0 = COPY [[DEF]](<vscale x 8 x s1>)422 ; RV64-NEXT: PseudoRET implicit $v0423entry:424 ret <vscale x 8 x i1> poison425}426 427define <vscale x 4 x i1> @test_ret_nxv4i1() {428 ; RV32-LABEL: name: test_ret_nxv4i1429 ; RV32: bb.1.entry:430 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF431 ; RV32-NEXT: $v0 = COPY [[DEF]](<vscale x 4 x s1>)432 ; RV32-NEXT: PseudoRET implicit $v0433 ;434 ; RV64-LABEL: name: test_ret_nxv4i1435 ; RV64: bb.1.entry:436 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF437 ; RV64-NEXT: $v0 = COPY [[DEF]](<vscale x 4 x s1>)438 ; RV64-NEXT: PseudoRET implicit $v0439entry:440 ret <vscale x 4 x i1> poison441}442 443define <vscale x 2 x i1> @test_ret_nxv2i1() {444 ; RV32-LABEL: name: test_ret_nxv2i1445 ; RV32: bb.1.entry:446 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF447 ; RV32-NEXT: $v0 = COPY [[DEF]](<vscale x 2 x s1>)448 ; RV32-NEXT: PseudoRET implicit $v0449 ;450 ; RV64-LABEL: name: test_ret_nxv2i1451 ; RV64: bb.1.entry:452 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF453 ; RV64-NEXT: $v0 = COPY [[DEF]](<vscale x 2 x s1>)454 ; RV64-NEXT: PseudoRET implicit $v0455entry:456 ret <vscale x 2 x i1> poison457}458 459define <vscale x 1 x i1> @test_ret_nxv1i1() {460 ; RV32-LABEL: name: test_ret_nxv1i1461 ; RV32: bb.1.entry:462 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF463 ; RV32-NEXT: $v0 = COPY [[DEF]](<vscale x 1 x s1>)464 ; RV32-NEXT: PseudoRET implicit $v0465 ;466 ; RV64-LABEL: name: test_ret_nxv1i1467 ; RV64: bb.1.entry:468 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF469 ; RV64-NEXT: $v0 = COPY [[DEF]](<vscale x 1 x s1>)470 ; RV64-NEXT: PseudoRET implicit $v0471entry:472 ret <vscale x 1 x i1> poison473}474 475define <vscale x 1 x float> @test_ret_nxv1f32() {476 ; RV32-LABEL: name: test_ret_nxv1f32477 ; RV32: bb.1.entry:478 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF479 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s32>)480 ; RV32-NEXT: PseudoRET implicit $v8481 ;482 ; RV64-LABEL: name: test_ret_nxv1f32483 ; RV64: bb.1.entry:484 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s32>) = G_IMPLICIT_DEF485 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s32>)486 ; RV64-NEXT: PseudoRET implicit $v8487entry:488 ret <vscale x 1 x float> poison489}490 491define <vscale x 2 x float> @test_ret_nxv2f32() {492 ; RV32-LABEL: name: test_ret_nxv2f32493 ; RV32: bb.1.entry:494 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF495 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s32>)496 ; RV32-NEXT: PseudoRET implicit $v8497 ;498 ; RV64-LABEL: name: test_ret_nxv2f32499 ; RV64: bb.1.entry:500 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF501 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s32>)502 ; RV64-NEXT: PseudoRET implicit $v8503entry:504 ret <vscale x 2 x float> poison505}506 507define <vscale x 4 x float> @test_ret_nxv4f32() {508 ; RV32-LABEL: name: test_ret_nxv4f32509 ; RV32: bb.1.entry:510 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF511 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 4 x s32>)512 ; RV32-NEXT: PseudoRET implicit $v8m2513 ;514 ; RV64-LABEL: name: test_ret_nxv4f32515 ; RV64: bb.1.entry:516 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF517 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 4 x s32>)518 ; RV64-NEXT: PseudoRET implicit $v8m2519entry:520 ret <vscale x 4 x float> poison521}522 523define <vscale x 8 x float> @test_ret_nxv8f32() {524 ; RV32-LABEL: name: test_ret_nxv8f32525 ; RV32: bb.1.entry:526 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF527 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 8 x s32>)528 ; RV32-NEXT: PseudoRET implicit $v8m4529 ;530 ; RV64-LABEL: name: test_ret_nxv8f32531 ; RV64: bb.1.entry:532 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF533 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 8 x s32>)534 ; RV64-NEXT: PseudoRET implicit $v8m4535entry:536 ret <vscale x 8 x float> poison537}538 539define <vscale x 16 x float> @test_ret_nxv16f32() {540 ; RV32-LABEL: name: test_ret_nxv16f32541 ; RV32: bb.1.entry:542 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF543 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 16 x s32>)544 ; RV32-NEXT: PseudoRET implicit $v8m8545 ;546 ; RV64-LABEL: name: test_ret_nxv16f32547 ; RV64: bb.1.entry:548 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF549 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 16 x s32>)550 ; RV64-NEXT: PseudoRET implicit $v8m8551entry:552 ret <vscale x 16 x float> poison553}554 555define <vscale x 1 x double> @test_ret_nxv1f64() {556 ; RV32-LABEL: name: test_ret_nxv1f64557 ; RV32: bb.1.entry:558 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF559 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s64>)560 ; RV32-NEXT: PseudoRET implicit $v8561 ;562 ; RV64-LABEL: name: test_ret_nxv1f64563 ; RV64: bb.1.entry:564 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF565 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s64>)566 ; RV64-NEXT: PseudoRET implicit $v8567entry:568 ret <vscale x 1 x double> poison569}570 571define <vscale x 2 x double> @test_ret_nxv2f64() {572 ; RV32-LABEL: name: test_ret_nxv2f64573 ; RV32: bb.1.entry:574 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF575 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 2 x s64>)576 ; RV32-NEXT: PseudoRET implicit $v8m2577 ;578 ; RV64-LABEL: name: test_ret_nxv2f64579 ; RV64: bb.1.entry:580 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF581 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 2 x s64>)582 ; RV64-NEXT: PseudoRET implicit $v8m2583entry:584 ret <vscale x 2 x double> poison585}586 587define <vscale x 4 x double> @test_ret_nxv4f64() {588 ; RV32-LABEL: name: test_ret_nxv4f64589 ; RV32: bb.1.entry:590 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF591 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 4 x s64>)592 ; RV32-NEXT: PseudoRET implicit $v8m4593 ;594 ; RV64-LABEL: name: test_ret_nxv4f64595 ; RV64: bb.1.entry:596 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s64>) = G_IMPLICIT_DEF597 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 4 x s64>)598 ; RV64-NEXT: PseudoRET implicit $v8m4599entry:600 ret <vscale x 4 x double> poison601}602 603define <vscale x 8 x double> @test_ret_nxv8f64() {604 ; RV32-LABEL: name: test_ret_nxv8f64605 ; RV32: bb.1.entry:606 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF607 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 8 x s64>)608 ; RV32-NEXT: PseudoRET implicit $v8m8609 ;610 ; RV64-LABEL: name: test_ret_nxv8f64611 ; RV64: bb.1.entry:612 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF613 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 8 x s64>)614 ; RV64-NEXT: PseudoRET implicit $v8m8615entry:616 ret <vscale x 8 x double> poison617}618 619define <vscale x 1 x half> @test_ret_nxv1f16() {620 ; RV32-LABEL: name: test_ret_nxv1f16621 ; RV32: bb.1.entry:622 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF623 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s16>)624 ; RV32-NEXT: PseudoRET implicit $v8625 ;626 ; RV64-LABEL: name: test_ret_nxv1f16627 ; RV64: bb.1.entry:628 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF629 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s16>)630 ; RV64-NEXT: PseudoRET implicit $v8631entry:632 ret <vscale x 1 x half> poison633}634 635define <vscale x 2 x half> @test_ret_nxv2f16() {636 ; RV32-LABEL: name: test_ret_nxv2f16637 ; RV32: bb.1.entry:638 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF639 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s16>)640 ; RV32-NEXT: PseudoRET implicit $v8641 ;642 ; RV64-LABEL: name: test_ret_nxv2f16643 ; RV64: bb.1.entry:644 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF645 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s16>)646 ; RV64-NEXT: PseudoRET implicit $v8647entry:648 ret <vscale x 2 x half> poison649}650 651define <vscale x 4 x half> @test_ret_nxv4f16() {652 ; RV32-LABEL: name: test_ret_nxv4f16653 ; RV32: bb.1.entry:654 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF655 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s16>)656 ; RV32-NEXT: PseudoRET implicit $v8657 ;658 ; RV64-LABEL: name: test_ret_nxv4f16659 ; RV64: bb.1.entry:660 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF661 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s16>)662 ; RV64-NEXT: PseudoRET implicit $v8663entry:664 ret <vscale x 4 x half> poison665}666 667define <vscale x 8 x half> @test_ret_nxv8f16() {668 ; RV32-LABEL: name: test_ret_nxv8f16669 ; RV32: bb.1.entry:670 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF671 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 8 x s16>)672 ; RV32-NEXT: PseudoRET implicit $v8m2673 ;674 ; RV64-LABEL: name: test_ret_nxv8f16675 ; RV64: bb.1.entry:676 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF677 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 8 x s16>)678 ; RV64-NEXT: PseudoRET implicit $v8m2679entry:680 ret <vscale x 8 x half> poison681}682 683define <vscale x 16 x half> @test_ret_nxv16f16() {684 ; RV32-LABEL: name: test_ret_nxv16f16685 ; RV32: bb.1.entry:686 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF687 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 16 x s16>)688 ; RV32-NEXT: PseudoRET implicit $v8m4689 ;690 ; RV64-LABEL: name: test_ret_nxv16f16691 ; RV64: bb.1.entry:692 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF693 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 16 x s16>)694 ; RV64-NEXT: PseudoRET implicit $v8m4695entry:696 ret <vscale x 16 x half> poison697}698 699define <vscale x 32 x half> @test_ret_nxv32f16() {700 ; RV32-LABEL: name: test_ret_nxv32f16701 ; RV32: bb.1.entry:702 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF703 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 32 x s16>)704 ; RV32-NEXT: PseudoRET implicit $v8m8705 ;706 ; RV64-LABEL: name: test_ret_nxv32f16707 ; RV64: bb.1.entry:708 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF709 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 32 x s16>)710 ; RV64-NEXT: PseudoRET implicit $v8m8711entry:712 ret <vscale x 32 x half> poison713}714 715define <vscale x 1 x bfloat> @test_ret_nxv1b16() {716 ; RV32-LABEL: name: test_ret_nxv1b16717 ; RV32: bb.1.entry:718 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF719 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s16>)720 ; RV32-NEXT: PseudoRET implicit $v8721 ;722 ; RV64-LABEL: name: test_ret_nxv1b16723 ; RV64: bb.1.entry:724 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF725 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 1 x s16>)726 ; RV64-NEXT: PseudoRET implicit $v8727entry:728 ret <vscale x 1 x bfloat> poison729}730 731define <vscale x 2 x bfloat> @test_ret_nxv2b16() {732 ; RV32-LABEL: name: test_ret_nxv2b16733 ; RV32: bb.1.entry:734 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF735 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s16>)736 ; RV32-NEXT: PseudoRET implicit $v8737 ;738 ; RV64-LABEL: name: test_ret_nxv2b16739 ; RV64: bb.1.entry:740 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s16>) = G_IMPLICIT_DEF741 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 2 x s16>)742 ; RV64-NEXT: PseudoRET implicit $v8743entry:744 ret <vscale x 2 x bfloat> poison745}746 747define <vscale x 4 x bfloat> @test_ret_nxv4b16() {748 ; RV32-LABEL: name: test_ret_nxv4b16749 ; RV32: bb.1.entry:750 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF751 ; RV32-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s16>)752 ; RV32-NEXT: PseudoRET implicit $v8753 ;754 ; RV64-LABEL: name: test_ret_nxv4b16755 ; RV64: bb.1.entry:756 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF757 ; RV64-NEXT: $v8 = COPY [[DEF]](<vscale x 4 x s16>)758 ; RV64-NEXT: PseudoRET implicit $v8759entry:760 ret <vscale x 4 x bfloat> poison761}762 763define <vscale x 8 x bfloat> @test_ret_nxv8b16() {764 ; RV32-LABEL: name: test_ret_nxv8b16765 ; RV32: bb.1.entry:766 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF767 ; RV32-NEXT: $v8m2 = COPY [[DEF]](<vscale x 8 x s16>)768 ; RV32-NEXT: PseudoRET implicit $v8m2769 ;770 ; RV64-LABEL: name: test_ret_nxv8b16771 ; RV64: bb.1.entry:772 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 8 x s16>) = G_IMPLICIT_DEF773 ; RV64-NEXT: $v8m2 = COPY [[DEF]](<vscale x 8 x s16>)774 ; RV64-NEXT: PseudoRET implicit $v8m2775entry:776 ret <vscale x 8 x bfloat> poison777}778 779define <vscale x 16 x bfloat> @test_ret_nxv16b16() {780 ; RV32-LABEL: name: test_ret_nxv16b16781 ; RV32: bb.1.entry:782 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF783 ; RV32-NEXT: $v8m4 = COPY [[DEF]](<vscale x 16 x s16>)784 ; RV32-NEXT: PseudoRET implicit $v8m4785 ;786 ; RV64-LABEL: name: test_ret_nxv16b16787 ; RV64: bb.1.entry:788 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s16>) = G_IMPLICIT_DEF789 ; RV64-NEXT: $v8m4 = COPY [[DEF]](<vscale x 16 x s16>)790 ; RV64-NEXT: PseudoRET implicit $v8m4791entry:792 ret <vscale x 16 x bfloat> poison793}794 795define <vscale x 32 x bfloat> @test_ret_nxv32b16() {796 ; RV32-LABEL: name: test_ret_nxv32b16797 ; RV32: bb.1.entry:798 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF799 ; RV32-NEXT: $v8m8 = COPY [[DEF]](<vscale x 32 x s16>)800 ; RV32-NEXT: PseudoRET implicit $v8m8801 ;802 ; RV64-LABEL: name: test_ret_nxv32b16803 ; RV64: bb.1.entry:804 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s16>) = G_IMPLICIT_DEF805 ; RV64-NEXT: $v8m8 = COPY [[DEF]](<vscale x 32 x s16>)806 ; RV64-NEXT: PseudoRET implicit $v8m8807entry:808 ret <vscale x 32 x bfloat> poison809}810