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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \3# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I4# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \5# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB6 7---8name: abds_i89body: |10 bb.0.entry:11 liveins: $x10, $x1112 ; RV32I-LABEL: name: abds_i813 ; RV32I: liveins: $x10, $x1114 ; RV32I-NEXT: {{ $}}15 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1016 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1117 ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 818 ; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 819 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]20 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]21 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]22 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]23 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)24 ; RV32I-NEXT: PseudoRET implicit $x1025 ;26 ; RV32ZBB-LABEL: name: abds_i827 ; RV32ZBB: liveins: $x10, $x1128 ; RV32ZBB-NEXT: {{ $}}29 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1030 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1131 ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 832 ; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 833 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]]34 ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]]35 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]36 ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)37 ; RV32ZBB-NEXT: PseudoRET implicit $x1038 %1:_(s32) = COPY $x1039 %2:_(s32) = COPY $x1140 %3:_(s32) = G_ASSERT_SEXT %1, 841 %4:_(s32) = G_ASSERT_SEXT %2, 842 %5:_(s8) = G_TRUNC %3(s32)43 %6:_(s8) = G_TRUNC %4(s32)44 %7:_(s8) = G_ABDS %5, %645 %8:_(s32) = G_ANYEXT %7(s8)46 $x10 = COPY %8(s32)47 PseudoRET implicit $x1048...49---50name: abds_i1651body: |52 bb.0.entry:53 liveins: $x10, $x1154 ; RV32I-LABEL: name: abds_i1655 ; RV32I: liveins: $x10, $x1156 ; RV32I-NEXT: {{ $}}57 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1058 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1159 ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 1660 ; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 1661 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT]], [[ASSERT_SEXT1]]62 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_SEXT1]], [[ASSERT_SEXT]]63 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASSERT_SEXT]](s32), [[ASSERT_SEXT1]]64 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]65 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)66 ; RV32I-NEXT: PseudoRET implicit $x1067 ;68 ; RV32ZBB-LABEL: name: abds_i1669 ; RV32ZBB: liveins: $x10, $x1170 ; RV32ZBB-NEXT: {{ $}}71 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1072 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1173 ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 1674 ; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 1675 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[ASSERT_SEXT1]]76 ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[ASSERT_SEXT]], [[ASSERT_SEXT1]]77 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]78 ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)79 ; RV32ZBB-NEXT: PseudoRET implicit $x1080 %1:_(s32) = COPY $x1081 %2:_(s32) = COPY $x1182 %3:_(s32) = G_ASSERT_SEXT %1, 1683 %4:_(s32) = G_ASSERT_SEXT %2, 1684 %5:_(s16) = G_TRUNC %3(s32)85 %6:_(s16) = G_TRUNC %4(s32)86 %7:_(s16) = G_ABDS %5, %687 %8:_(s32) = G_ANYEXT %7(s16)88 $x10 = COPY %8(s32)89 PseudoRET implicit $x1090...91---92name: abds_i3293body: |94 bb.0.entry:95 liveins: $x10, $x1196 ; RV32I-LABEL: name: abds_i3297 ; RV32I: liveins: $x10, $x1198 ; RV32I-NEXT: {{ $}}99 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10100 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11101 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]102 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]103 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY]](s32), [[COPY1]]104 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]105 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)106 ; RV32I-NEXT: PseudoRET implicit $x10107 ;108 ; RV32ZBB-LABEL: name: abds_i32109 ; RV32ZBB: liveins: $x10, $x11110 ; RV32ZBB-NEXT: {{ $}}111 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10112 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11113 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[COPY1]]114 ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[COPY]], [[COPY1]]115 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]116 ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)117 ; RV32ZBB-NEXT: PseudoRET implicit $x10118 %1:_(s32) = COPY $x10119 %2:_(s32) = COPY $x11120 %3:_(s32) = G_ABDS %1, %2121 $x10 = COPY %3(s32)122 PseudoRET implicit $x10123...124---125name: abds_i64126body: |127 bb.0.entry:128 ; CHECK-LABEL: name: abds_i64129 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10130 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11131 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10132 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11133 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]]134 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]135 ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]136 ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]137 ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]138 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]]139 ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]140 ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]]141 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]142 ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[COPY1]](s32), [[COPY3]]143 ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]144 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]]145 ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]]146 ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]]147 ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)148 ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)149 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11150 %0:_(s32) = COPY $x10151 %1:_(s32) = COPY $x11152 %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)153 %3:_(s32) = COPY $x10154 %4:_(s32) = COPY $x11155 %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)156 %6:_(s64) = G_ABDS %2, %5157 %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)158 $x10 = COPY %7(s32)159 $x11 = COPY %8(s32)160 PseudoRET implicit $x10, implicit $x11161...162---163name: abdu_i8164body: |165 bb.0.entry:166 liveins: $x10, $x11167 ; RV32I-LABEL: name: abdu_i8168 ; RV32I: liveins: $x10, $x11169 ; RV32I-NEXT: {{ $}}170 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10171 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11172 ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8173 ; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8174 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]175 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]176 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]177 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]178 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)179 ; RV32I-NEXT: PseudoRET implicit $x10180 ;181 ; RV32ZBB-LABEL: name: abdu_i8182 ; RV32ZBB: liveins: $x10, $x11183 ; RV32ZBB-NEXT: {{ $}}184 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10185 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11186 ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8187 ; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 8188 ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]189 ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]190 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]191 ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)192 ; RV32ZBB-NEXT: PseudoRET implicit $x10193 %1:_(s32) = COPY $x10194 %2:_(s32) = COPY $x11195 %3:_(s32) = G_ASSERT_ZEXT %1, 8196 %4:_(s32) = G_ASSERT_ZEXT %2, 8197 %5:_(s8) = G_TRUNC %3(s32)198 %6:_(s8) = G_TRUNC %4(s32)199 %7:_(s8) = G_ABDU %5, %6200 %8:_(s32) = G_ANYEXT %7(s8)201 $x10 = COPY %8(s32)202 PseudoRET implicit $x10203...204---205name: abdu_i16206body: |207 bb.0.entry:208 liveins: $x10, $x11209 ; RV32I-LABEL: name: abdu_i16210 ; RV32I: liveins: $x10, $x11211 ; RV32I-NEXT: {{ $}}212 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10213 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11214 ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16215 ; RV32I-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16216 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]217 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[ASSERT_ZEXT1]], [[ASSERT_ZEXT]]218 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[ASSERT_ZEXT]](s32), [[ASSERT_ZEXT1]]219 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]220 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)221 ; RV32I-NEXT: PseudoRET implicit $x10222 ;223 ; RV32ZBB-LABEL: name: abdu_i16224 ; RV32ZBB: liveins: $x10, $x11225 ; RV32ZBB-NEXT: {{ $}}226 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10227 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11228 ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16229 ; RV32ZBB-NEXT: [[ASSERT_ZEXT1:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY1]], 16230 ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]231 ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[ASSERT_ZEXT]], [[ASSERT_ZEXT1]]232 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]233 ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)234 ; RV32ZBB-NEXT: PseudoRET implicit $x10235 %1:_(s32) = COPY $x10236 %2:_(s32) = COPY $x11237 %3:_(s32) = G_ASSERT_ZEXT %1, 16238 %4:_(s32) = G_ASSERT_ZEXT %2, 16239 %5:_(s16) = G_TRUNC %3(s32)240 %6:_(s16) = G_TRUNC %4(s32)241 %7:_(s16) = G_ABDU %5, %6242 %8:_(s32) = G_ANYEXT %7(s16)243 $x10 = COPY %8(s32)244 PseudoRET implicit $x10245...246---247name: abdu_i32248body: |249 bb.0.entry:250 liveins: $x10, $x11251 ; RV32I-LABEL: name: abdu_i32252 ; RV32I: liveins: $x10, $x11253 ; RV32I-NEXT: {{ $}}254 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10255 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11256 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]257 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY]]258 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY1]]259 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SUB]], [[SUB1]]260 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)261 ; RV32I-NEXT: PseudoRET implicit $x10262 ;263 ; RV32ZBB-LABEL: name: abdu_i32264 ; RV32ZBB: liveins: $x10, $x11265 ; RV32ZBB-NEXT: {{ $}}266 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10267 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11268 ; RV32ZBB-NEXT: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]269 ; RV32ZBB-NEXT: [[UMIN:%[0-9]+]]:_(s32) = G_UMIN [[COPY]], [[COPY1]]270 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[UMAX]], [[UMIN]]271 ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)272 ; RV32ZBB-NEXT: PseudoRET implicit $x10273 %1:_(s32) = COPY $x10274 %2:_(s32) = COPY $x11275 %3:_(s32) = G_ABDU %1, %2276 $x10 = COPY %3(s32)277 PseudoRET implicit $x10278...279---280name: abdu_i64281body: |282 bb.0.entry:283 ; CHECK-LABEL: name: abdu_i64284 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10285 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11286 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10287 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11288 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY2]]289 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY2]]290 ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[COPY3]]291 ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP]]292 ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY]]293 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[COPY]]294 ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[COPY3]], [[COPY1]]295 ; CHECK-NEXT: [[SUB5:%[0-9]+]]:_(s32) = G_SUB [[SUB4]], [[ICMP1]]296 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY]](s32), [[COPY2]]297 ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY3]]298 ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]299 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP4]](s32), [[ICMP2]], [[ICMP3]]300 ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB]], [[SUB3]]301 ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[SUB2]], [[SUB5]]302 ; CHECK-NEXT: $x10 = COPY [[SELECT1]](s32)303 ; CHECK-NEXT: $x11 = COPY [[SELECT2]](s32)304 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11305 %0:_(s32) = COPY $x10306 %1:_(s32) = COPY $x11307 %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)308 %3:_(s32) = COPY $x10309 %4:_(s32) = COPY $x11310 %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)311 %6:_(s64) = G_ABDU %2, %5312 %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)313 $x10 = COPY %7(s32)314 $x11 = COPY %8(s32)315 PseudoRET implicit $x10, implicit $x11316...317