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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \3# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I4# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o -\5# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB6 7---8name: abs_i89body: |10 bb.0.entry:11 ; RV32I-LABEL: name: abs_i812 ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x1013 ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 814 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 715 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2416 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C1]](s32)17 ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)18 ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)19 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]]20 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]21 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25522 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C2]]23 ; RV32I-NEXT: $x10 = COPY [[AND]](s32)24 ; RV32I-NEXT: PseudoRET implicit $x1025 ;26 ; RV32ZBB-LABEL: name: abs_i827 ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x1028 ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 829 ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASSERT_ZEXT]], 830 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 031 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SEXT_INREG]]32 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SUB]]33 ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25534 ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMAX]], [[C1]]35 ; RV32ZBB-NEXT: $x10 = COPY [[AND]](s32)36 ; RV32ZBB-NEXT: PseudoRET implicit $x1037 %1:_(s32) = COPY $x1038 %2:_(s32) = G_ASSERT_ZEXT %1, 839 %0:_(s8) = G_TRUNC %2(s32)40 %3:_(s8) = G_ABS %041 %4:_(s32) = G_ZEXT %3(s8)42 $x10 = COPY %4(s32)43 PseudoRET implicit $x1044...45---46name: abs_i1647body: |48 bb.0.entry:49 ; RV32I-LABEL: name: abs_i1650 ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x1051 ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 1652 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1553 ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ASSERT_SEXT]], [[C]](s32)54 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_SEXT]], [[ASHR]]55 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]56 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1657 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[XOR]], [[C1]](s32)58 ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)59 ; RV32I-NEXT: $x10 = COPY [[ASHR1]](s32)60 ; RV32I-NEXT: PseudoRET implicit $x1061 ;62 ; RV32ZBB-LABEL: name: abs_i1663 ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x1064 ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 1665 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 066 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ASSERT_SEXT]]67 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[SUB]]68 ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 1669 ; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s32)70 ; RV32ZBB-NEXT: PseudoRET implicit $x1071 %1:_(s32) = COPY $x1072 %2:_(s32) = G_ASSERT_SEXT %1, 1673 %0:_(s16) = G_TRUNC %2(s32)74 %3:_(s16) = G_ABS %075 %4:_(s32) = G_SEXT %3(s16)76 $x10 = COPY %4(s32)77 PseudoRET implicit $x1078...79---80name: abs_i3281body: |82 bb.0.entry:83 ; RV32I-LABEL: name: abs_i3284 ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x1085 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3186 ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)87 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]88 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]89 ; RV32I-NEXT: $x10 = COPY [[XOR]](s32)90 ; RV32I-NEXT: PseudoRET implicit $x1091 ;92 ; RV32ZBB-LABEL: name: abs_i3293 ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x1094 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 095 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY]]96 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[SUB]]97 ; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32)98 ; RV32ZBB-NEXT: PseudoRET implicit $x1099 %0:_(s32) = COPY $x10100 %1:_(s32) = G_ABS %0101 $x10 = COPY %1(s32)102 PseudoRET implicit $x10103...104---105name: abs_i64106body: |107 bb.0.entry:108 ; CHECK-LABEL: name: abs_i64109 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11111 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31112 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32)113 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]114 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[ASHR]]115 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)116 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR]]117 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]118 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)119 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[ASHR]]120 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[ASHR]]121 ; CHECK-NEXT: $x10 = COPY [[XOR]](s32)122 ; CHECK-NEXT: $x11 = COPY [[XOR1]](s32)123 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11124 %1:_(s32) = COPY $x10125 %2:_(s32) = COPY $x11126 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)127 %3:_(s64) = G_ABS %0128 %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)129 $x10 = COPY %4(s32)130 $x11 = COPY %5(s32)131 PseudoRET implicit $x10, implicit $x11132...133