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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 32# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \3# RUN: | FileCheck %s --check-prefix=RV32I4# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \5# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB6# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \7# RUN: | FileCheck %s --check-prefix=RV32ZBB_OR_RV32ZBKB8 9---10name: bswap_i1611body: |12 bb.0:13 liveins: $x1014 ; RV32I-LABEL: name: bswap_i1615 ; RV32I: liveins: $x1016 ; RV32I-NEXT: {{ $}}17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1018 ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 1619 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 820 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32)21 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ASSERT_ZEXT]], [[C]](s32)22 ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]23 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553524 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[OR]], [[C1]]25 ; RV32I-NEXT: $x10 = COPY [[AND]](s32)26 ; RV32I-NEXT: PseudoRET implicit $x1027 ;28 ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i1629 ; RV32ZBB_OR_RV32ZBKB: liveins: $x1030 ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}31 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1032 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 1633 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[ASSERT_ZEXT]]34 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1635 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BSWAP]], [[C]](s32)36 ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[LSHR]](s32)37 ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x1038 %0:_(s32) = COPY $x1039 %1:_(s32) = G_ASSERT_ZEXT %0, 1640 %2:_(s16) = G_TRUNC %1(s32)41 %3:_(s16) = G_BSWAP %242 %4:_(s32) = G_ZEXT %3(s16)43 $x10 = COPY %4(s32)44 PseudoRET implicit $x1045...46---47name: bswap_i3248body: |49 bb.0:50 liveins: $x1051 ; RV32I-LABEL: name: bswap_i3252 ; RV32I: liveins: $x1053 ; RV32I-NEXT: {{ $}}54 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1055 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2456 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)57 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)58 ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]59 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6528060 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 861 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]62 ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)63 ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]64 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)65 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]66 ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]67 ; RV32I-NEXT: $x10 = COPY [[OR2]](s32)68 ; RV32I-NEXT: PseudoRET implicit $x1069 ;70 ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i3271 ; RV32ZBB_OR_RV32ZBKB: liveins: $x1072 ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}73 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1074 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]75 ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)76 ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x1077 %0:_(s32) = COPY $x1078 %1:_(s32) = G_BSWAP %079 $x10 = COPY %1(s32)80 PseudoRET implicit $x1081...82---83name: bswap_i6484body: |85 bb.0:86 liveins: $x10, $x1187 ; RV32I-LABEL: name: bswap_i6488 ; RV32I: liveins: $x10, $x1189 ; RV32I-NEXT: {{ $}}90 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1091 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1192 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2493 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32)94 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)95 ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]96 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6528097 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 898 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]99 ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32)100 ; RV32I-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]101 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)102 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]]103 ; RV32I-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[AND1]]104 ; RV32I-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C]](s32)105 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)106 ; RV32I-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL2]]107 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]108 ; RV32I-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[C2]](s32)109 ; RV32I-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR3]], [[SHL3]]110 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)111 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR3]], [[C1]]112 ; RV32I-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[OR4]], [[AND3]]113 ; RV32I-NEXT: $x10 = COPY [[OR2]](s32)114 ; RV32I-NEXT: $x11 = COPY [[OR5]](s32)115 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11116 ;117 ; RV32ZBB_OR_RV32ZBKB-LABEL: name: bswap_i64118 ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11119 ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}120 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10121 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11122 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP:%[0-9]+]]:_(s32) = G_BSWAP [[COPY1]]123 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[BSWAP1:%[0-9]+]]:_(s32) = G_BSWAP [[COPY]]124 ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[BSWAP]](s32)125 ; RV32ZBB_OR_RV32ZBKB-NEXT: $x11 = COPY [[BSWAP1]](s32)126 ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10, implicit $x11127 %0:_(s32) = COPY $x10128 %1:_(s32) = COPY $x11129 %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)130 %3:_(s64) = G_BSWAP %2131 %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)132 $x10 = COPY %4(s32)133 $x11 = COPY %5(s32)134 PseudoRET implicit $x10, implicit $x11135...136