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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \3# RUN: | FileCheck %s --check-prefix=RV32I4# RUN: llc -mattr=+m -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \5# RUN: | FileCheck %s --check-prefix=RV32ZBB6 7---8name: ctpop_i89body: |10 bb.1:11 liveins: $x1012 13 ; RV32I-LABEL: name: ctpop_i814 ; RV32I: liveins: $x1015 ; RV32I-NEXT: {{ $}}16 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1017 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 118 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25519 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]20 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)21 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8522 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]23 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND1]]24 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 225 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]26 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)27 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5128 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]29 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]]30 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]]31 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 432 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C5]](s32)33 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]34 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1535 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]36 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 037 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C]]38 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)39 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)40 ; RV32I-NEXT: PseudoRET implicit $x1041 ;42 ; RV32ZBB-LABEL: name: ctpop_i843 ; RV32ZBB: liveins: $x1044 ; RV32ZBB-NEXT: {{ $}}45 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1046 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25547 ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]48 ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)49 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)50 ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)51 ; RV32ZBB-NEXT: PseudoRET implicit $x1052 %1:_(s32) = COPY $x1053 %0:_(s8) = G_TRUNC %1(s32)54 %2:_(s8) = G_CTPOP %0(s8)55 %3:_(s32) = G_ANYEXT %2(s8)56 $x10 = COPY %3(s32)57 PseudoRET implicit $x1058 59...60---61name: ctpop_i1662body: |63 bb.1:64 liveins: $x1065 66 ; RV32I-LABEL: name: ctpop_i1667 ; RV32I: liveins: $x1068 ; RV32I-NEXT: {{ $}}69 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1070 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 171 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553572 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]73 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C]](s32)74 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2184575 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]76 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND1]]77 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 278 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]79 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[C3]](s32)80 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 1310781 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]82 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]]83 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND3]], [[AND4]]84 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 485 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C5]](s32)86 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]87 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 385588 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]89 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 25790 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 891 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C7]]92 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]93 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32)94 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)95 ; RV32I-NEXT: PseudoRET implicit $x1096 ;97 ; RV32ZBB-LABEL: name: ctpop_i1698 ; RV32ZBB: liveins: $x1099 ; RV32ZBB-NEXT: {{ $}}100 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10101 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535102 ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]103 ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[AND]](s32)104 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTPOP]](s32)105 ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)106 ; RV32ZBB-NEXT: PseudoRET implicit $x10107 %1:_(s32) = COPY $x10108 %0:_(s16) = G_TRUNC %1(s32)109 %2:_(s16) = G_CTPOP %0(s16)110 %3:_(s32) = G_ANYEXT %2(s16)111 $x10 = COPY %3(s32)112 PseudoRET implicit $x10113 114...115---116name: ctpop_i32117body: |118 bb.1:119 liveins: $x10120 121 ; RV32I-LABEL: name: ctpop_i32122 ; RV32I: liveins: $x10123 ; RV32I-NEXT: {{ $}}124 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10125 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1126 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)127 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765128 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]129 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]130 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2131 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)132 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459133 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]134 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]135 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]136 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4137 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)138 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]139 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135140 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]141 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009142 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24143 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]144 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)145 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)146 ; RV32I-NEXT: PseudoRET implicit $x10147 ;148 ; RV32ZBB-LABEL: name: ctpop_i32149 ; RV32ZBB: liveins: $x10150 ; RV32ZBB-NEXT: {{ $}}151 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10152 ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)153 ; RV32ZBB-NEXT: $x10 = COPY [[CTPOP]](s32)154 ; RV32ZBB-NEXT: PseudoRET implicit $x10155 %0:_(s32) = COPY $x10156 %1:_(s32) = G_CTPOP %0(s32)157 $x10 = COPY %1(s32)158 PseudoRET implicit $x10159 160...161---162name: ctpop_i64163body: |164 bb.1:165 liveins: $x10, $x11166 167 ; RV32I-LABEL: name: ctpop_i64168 ; RV32I: liveins: $x10, $x11169 ; RV32I-NEXT: {{ $}}170 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10171 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11172 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1173 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)174 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765175 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]176 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[AND]]177 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2178 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C2]](s32)179 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459180 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C3]]181 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C3]]182 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND1]], [[AND2]]183 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4184 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD]], [[C4]](s32)185 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD]]186 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135187 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]188 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009189 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24190 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]191 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)192 ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C]](s32)193 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C1]]194 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY1]], [[AND4]]195 ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C2]](s32)196 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C3]]197 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C3]]198 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[AND6]]199 ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD2]], [[C4]](s32)200 ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD2]]201 ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[ADD3]], [[C5]]202 ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND7]], [[C6]]203 ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C7]](s32)204 ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[LSHR7]], [[LSHR3]]205 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0206 ; RV32I-NEXT: $x10 = COPY [[ADD4]](s32)207 ; RV32I-NEXT: $x11 = COPY [[C8]](s32)208 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11209 ;210 ; RV32ZBB-LABEL: name: ctpop_i64211 ; RV32ZBB: liveins: $x10, $x11212 ; RV32ZBB-NEXT: {{ $}}213 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10214 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11215 ; RV32ZBB-NEXT: [[CTPOP:%[0-9]+]]:_(s32) = G_CTPOP [[COPY]](s32)216 ; RV32ZBB-NEXT: [[CTPOP1:%[0-9]+]]:_(s32) = G_CTPOP [[COPY1]](s32)217 ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTPOP1]], [[CTPOP]]218 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0219 ; RV32ZBB-NEXT: $x10 = COPY [[ADD]](s32)220 ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32)221 ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11222 %1:_(s32) = COPY $x10223 %2:_(s32) = COPY $x11224 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)225 %3:_(s64) = G_CTPOP %0(s64)226 %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)227 $x10 = COPY %4(s32)228 $x11 = COPY %5(s32)229 PseudoRET implicit $x10, implicit $x11230 231...232