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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mattr=+m -mtriple=riscv32 -run-pass=legalizer %s -o - \3# RUN: | FileCheck %s --check-prefix=RV32I4# RUN: llc -mattr=+m -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \5# RUN: | FileCheck %s --check-prefix=RV32ZBB6 7---8name: cttz_i89body: |10 bb.1:11 liveins: $x1012 13 ; RV32I-LABEL: name: cttz_i814 ; RV32I: liveins: $x1015 ; RV32I-NEXT: {{ $}}16 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1017 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -118 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]19 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]20 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]21 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 122 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25523 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]24 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)25 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8526 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]27 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]]28 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 229 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]30 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32)31 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5132 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]33 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]34 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]35 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 436 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32)37 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]38 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 1539 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]40 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 041 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C1]]42 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)43 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)44 ; RV32I-NEXT: PseudoRET implicit $x1045 ;46 ; RV32ZBB-LABEL: name: cttz_i847 ; RV32ZBB: liveins: $x1048 ; RV32ZBB-NEXT: {{ $}}49 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1050 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 25651 ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]52 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)53 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)54 ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)55 ; RV32ZBB-NEXT: PseudoRET implicit $x1056 %1:_(s32) = COPY $x1057 %0:_(s8) = G_TRUNC %1(s32)58 %2:_(s8) = G_CTTZ %0(s8)59 %3:_(s32) = G_ANYEXT %2(s8)60 $x10 = COPY %3(s32)61 PseudoRET implicit $x1062 63...64---65name: cttz_i1666body: |67 bb.1:68 liveins: $x1069 70 ; RV32I-LABEL: name: cttz_i1671 ; RV32I: liveins: $x1072 ; RV32I-NEXT: {{ $}}73 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1074 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -175 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]76 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]77 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]78 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 179 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553580 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]81 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)82 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2184583 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]84 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]]85 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 286 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]87 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32)88 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1310789 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]90 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]91 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]92 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 493 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32)94 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]95 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 385596 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]97 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 25798 ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 899 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C8]]100 ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C2]]101 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C9]](s32)102 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)103 ; RV32I-NEXT: PseudoRET implicit $x10104 ;105 ; RV32ZBB-LABEL: name: cttz_i16106 ; RV32ZBB: liveins: $x10107 ; RV32ZBB-NEXT: {{ $}}108 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10109 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536110 ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]111 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)112 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)113 ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)114 ; RV32ZBB-NEXT: PseudoRET implicit $x10115 %1:_(s32) = COPY $x10116 %0:_(s16) = G_TRUNC %1(s32)117 %2:_(s16) = G_CTTZ %0(s16)118 %3:_(s32) = G_ANYEXT %2(s16)119 $x10 = COPY %3(s32)120 PseudoRET implicit $x10121 122...123---124name: cttz_i32125body: |126 bb.1:127 liveins: $x10128 129 ; RV32I-LABEL: name: cttz_i32130 ; RV32I: liveins: $x10131 ; RV32I-NEXT: {{ $}}132 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10133 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1134 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]135 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]136 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]137 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1138 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)139 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765140 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]141 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]142 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2143 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C3]](s32)144 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459145 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]146 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]]147 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]148 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4149 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C5]](s32)150 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]151 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135152 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C6]]153 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009154 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24155 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C7]]156 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)157 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)158 ; RV32I-NEXT: PseudoRET implicit $x10159 ;160 ; RV32ZBB-LABEL: name: cttz_i32161 ; RV32ZBB: liveins: $x10162 ; RV32ZBB-NEXT: {{ $}}163 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10164 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32)165 ; RV32ZBB-NEXT: $x10 = COPY [[CTTZ]](s32)166 ; RV32ZBB-NEXT: PseudoRET implicit $x10167 %0:_(s32) = COPY $x10168 %1:_(s32) = G_CTTZ %0(s32)169 $x10 = COPY %1(s32)170 PseudoRET implicit $x10171 172...173---174name: cttz_i64175body: |176 bb.1:177 liveins: $x10, $x11178 179 ; RV32I-LABEL: name: cttz_i64180 ; RV32I: liveins: $x10, $x11181 ; RV32I-NEXT: {{ $}}182 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10183 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11184 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0185 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]186 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1187 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]188 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]189 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]190 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1191 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s32)192 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765193 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]194 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]195 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2196 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C4]](s32)197 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459198 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]199 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]200 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]201 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4202 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32)203 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]204 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135205 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]206 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009207 ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24208 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C8]]209 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32)210 ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32211 ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[C10]]212 ; RV32I-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]213 ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]214 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD4]]215 ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C2]](s32)216 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]217 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND5]], [[AND6]]218 ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C4]](s32)219 ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C5]]220 ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C5]]221 ; RV32I-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]]222 ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD5]], [[C6]](s32)223 ; RV32I-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD5]]224 ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD6]], [[C7]]225 ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]226 ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C9]](s32)227 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD3]], [[LSHR7]]228 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)229 ; RV32I-NEXT: $x11 = COPY [[C]](s32)230 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11231 ;232 ; RV32ZBB-LABEL: name: cttz_i64233 ; RV32ZBB: liveins: $x10, $x11234 ; RV32ZBB-NEXT: {{ $}}235 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10236 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11237 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0238 ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]239 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY1]](s32)240 ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32241 ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTTZ]], [[C1]]242 ; RV32ZBB-NEXT: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32)243 ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTTZ1]]244 ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32)245 ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32)246 ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11247 %1:_(s32) = COPY $x10248 %2:_(s32) = COPY $x11249 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)250 %3:_(s64) = G_CTTZ %0(s64)251 %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)252 $x10 = COPY %4(s32)253 $x11 = COPY %5(s32)254 PseudoRET implicit $x10, implicit $x11255 256...257---258name: cttz_zero_undef_i8259body: |260 bb.1:261 liveins: $x10262 263 ; RV32I-LABEL: name: cttz_zero_undef_i8264 ; RV32I: liveins: $x10265 ; RV32I-NEXT: {{ $}}266 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10267 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1268 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]269 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]270 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]271 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1272 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255273 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]274 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)275 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 85276 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]277 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]]278 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2279 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]280 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32)281 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 51282 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]283 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]284 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]285 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4286 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32)287 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]288 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 15289 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]290 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 0291 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C1]]292 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)293 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)294 ; RV32I-NEXT: PseudoRET implicit $x10295 ;296 ; RV32ZBB-LABEL: name: cttz_zero_undef_i8297 ; RV32ZBB: liveins: $x10298 ; RV32ZBB-NEXT: {{ $}}299 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10300 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256301 ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]302 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)303 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)304 ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)305 ; RV32ZBB-NEXT: PseudoRET implicit $x10306 %1:_(s32) = COPY $x10307 %0:_(s8) = G_TRUNC %1(s32)308 %2:_(s8) = G_CTTZ_ZERO_UNDEF %0(s8)309 %3:_(s32) = G_ANYEXT %2(s8)310 $x10 = COPY %3(s32)311 PseudoRET implicit $x10312 313...314---315name: cttz_zero_undef_i16316body: |317 bb.1:318 liveins: $x10319 320 ; RV32I-LABEL: name: cttz_zero_undef_i16321 ; RV32I: liveins: $x10322 ; RV32I-NEXT: {{ $}}323 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10324 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1325 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]326 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]327 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]328 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1329 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535330 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]331 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[C1]](s32)332 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 21845333 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]334 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND2]]335 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2336 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C2]]337 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C4]](s32)338 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 13107339 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]340 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]341 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND4]], [[AND5]]342 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4343 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32)344 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]345 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855346 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]347 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257348 ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 8349 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND6]], [[C8]]350 ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C2]]351 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[C9]](s32)352 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)353 ; RV32I-NEXT: PseudoRET implicit $x10354 ;355 ; RV32ZBB-LABEL: name: cttz_zero_undef_i16356 ; RV32ZBB: liveins: $x10357 ; RV32ZBB-NEXT: {{ $}}358 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10359 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536360 ; RV32ZBB-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]361 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32)362 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32)363 ; RV32ZBB-NEXT: $x10 = COPY [[COPY1]](s32)364 ; RV32ZBB-NEXT: PseudoRET implicit $x10365 %1:_(s32) = COPY $x10366 %0:_(s16) = G_TRUNC %1(s32)367 %2:_(s16) = G_CTTZ_ZERO_UNDEF %0(s16)368 %3:_(s32) = G_ANYEXT %2(s16)369 $x10 = COPY %3(s32)370 PseudoRET implicit $x10371 372...373---374name: cttz_zero_undef_i32375body: |376 bb.1:377 liveins: $x10378 379 ; RV32I-LABEL: name: cttz_zero_undef_i32380 ; RV32I: liveins: $x10381 ; RV32I-NEXT: {{ $}}382 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10383 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1384 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C]]385 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C]]386 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]387 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1388 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C1]](s32)389 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765390 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C2]]391 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]392 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2393 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C3]](s32)394 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459395 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]396 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C4]]397 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]398 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4399 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C5]](s32)400 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]401 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135402 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C6]]403 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009404 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 24405 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C7]]406 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C8]](s32)407 ; RV32I-NEXT: $x10 = COPY [[LSHR3]](s32)408 ; RV32I-NEXT: PseudoRET implicit $x10409 ;410 ; RV32ZBB-LABEL: name: cttz_zero_undef_i32411 ; RV32ZBB: liveins: $x10412 ; RV32ZBB-NEXT: {{ $}}413 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10414 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32)415 ; RV32ZBB-NEXT: $x10 = COPY [[CTTZ]](s32)416 ; RV32ZBB-NEXT: PseudoRET implicit $x10417 %0:_(s32) = COPY $x10418 %1:_(s32) = G_CTTZ_ZERO_UNDEF %0(s32)419 $x10 = COPY %1(s32)420 PseudoRET implicit $x10421 422...423---424name: cttz_zero_undef_i64425body: |426 bb.1:427 liveins: $x10, $x11428 429 ; RV32I-LABEL: name: cttz_zero_undef_i64430 ; RV32I: liveins: $x10, $x11431 ; RV32I-NEXT: {{ $}}432 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10433 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11434 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0435 ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]436 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1437 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C1]]438 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[C1]]439 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[ADD]]440 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1441 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[C2]](s32)442 ; RV32I-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1431655765443 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C3]]444 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]445 ; RV32I-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2446 ; RV32I-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SUB]], [[C4]](s32)447 ; RV32I-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 858993459448 ; RV32I-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C5]]449 ; RV32I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C5]]450 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[AND2]], [[AND3]]451 ; RV32I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4452 ; RV32I-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[ADD1]], [[C6]](s32)453 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[LSHR2]], [[ADD1]]454 ; RV32I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 252645135455 ; RV32I-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[ADD2]], [[C7]]456 ; RV32I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009457 ; RV32I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24458 ; RV32I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND4]], [[C8]]459 ; RV32I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32)460 ; RV32I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32461 ; RV32I-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[C10]]462 ; RV32I-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[C1]]463 ; RV32I-NEXT: [[ADD4:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C1]]464 ; RV32I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[XOR1]], [[ADD4]]465 ; RV32I-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[C2]](s32)466 ; RV32I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C3]]467 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND5]], [[AND6]]468 ; RV32I-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[SUB1]], [[C4]](s32)469 ; RV32I-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C5]]470 ; RV32I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SUB1]], [[C5]]471 ; RV32I-NEXT: [[ADD5:%[0-9]+]]:_(s32) = G_ADD [[AND7]], [[AND8]]472 ; RV32I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[ADD5]], [[C6]](s32)473 ; RV32I-NEXT: [[ADD6:%[0-9]+]]:_(s32) = G_ADD [[LSHR6]], [[ADD5]]474 ; RV32I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD6]], [[C7]]475 ; RV32I-NEXT: [[MUL1:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]476 ; RV32I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[MUL1]], [[C9]](s32)477 ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD3]], [[LSHR7]]478 ; RV32I-NEXT: $x10 = COPY [[SELECT]](s32)479 ; RV32I-NEXT: $x11 = COPY [[C]](s32)480 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11481 ;482 ; RV32ZBB-LABEL: name: cttz_zero_undef_i64483 ; RV32ZBB: liveins: $x10, $x11484 ; RV32ZBB-NEXT: {{ $}}485 ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10486 ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11487 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0488 ; RV32ZBB-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]489 ; RV32ZBB-NEXT: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY1]](s32)490 ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32491 ; RV32ZBB-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[CTTZ]], [[C1]]492 ; RV32ZBB-NEXT: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32)493 ; RV32ZBB-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ADD]], [[CTTZ1]]494 ; RV32ZBB-NEXT: $x10 = COPY [[SELECT]](s32)495 ; RV32ZBB-NEXT: $x11 = COPY [[C]](s32)496 ; RV32ZBB-NEXT: PseudoRET implicit $x10, implicit $x11497 %1:_(s32) = COPY $x10498 %2:_(s32) = COPY $x11499 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)500 %3:_(s64) = G_CTTZ_ZERO_UNDEF %0(s64)501 %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)502 $x10 = COPY %4(s32)503 $x11 = COPY %5(s32)504 PseudoRET implicit $x10, implicit $x11505 506...507