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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \3# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I4# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o - \5# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB_OR_RV32ZBKB6# RUN: llc -mtriple=riscv32 -mattr=+zbkb -run-pass=legalizer %s -o - \7# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB_OR_RV32ZBKB8 9---10name: rotl_i811body: |12 bb.1:13 liveins: $x10, $x1114 15 ; CHECK-LABEL: name: rotl_i816 ; CHECK: liveins: $x10, $x1117 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1019 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1120 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 021 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 722 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]23 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]24 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 25525 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]26 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)27 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]28 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]29 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)30 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]31 ; CHECK-NEXT: $x10 = COPY [[OR]](s32)32 ; CHECK-NEXT: PseudoRET implicit $x1033 %2:_(s32) = COPY $x1034 %0:_(s8) = G_TRUNC %2(s32)35 %3:_(s32) = COPY $x1136 %1:_(s8) = G_TRUNC %3(s32)37 %4:_(s8) = G_ROTL %0, %1(s8)38 %5:_(s32) = G_ANYEXT %4(s8)39 $x10 = COPY %5(s32)40 PseudoRET implicit $x1041 42...43---44name: rotl_i1645body: |46 bb.1:47 liveins: $x10, $x1148 49 ; CHECK-LABEL: name: rotl_i1650 ; CHECK: liveins: $x10, $x1151 ; CHECK-NEXT: {{ $}}52 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1053 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1154 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 055 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1556 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]57 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]58 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 6553559 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]60 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)61 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]62 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]63 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[AND2]](s32)64 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]65 ; CHECK-NEXT: $x10 = COPY [[OR]](s32)66 ; CHECK-NEXT: PseudoRET implicit $x1067 %2:_(s32) = COPY $x1068 %0:_(s16) = G_TRUNC %2(s32)69 %3:_(s32) = COPY $x1170 %1:_(s16) = G_TRUNC %3(s32)71 %4:_(s16) = G_ROTL %0, %1(s16)72 %5:_(s32) = G_ANYEXT %4(s16)73 $x10 = COPY %5(s32)74 PseudoRET implicit $x1075 76...77---78name: rotl_i3279body: |80 bb.1:81 liveins: $x10, $x1182 83 ; RV32I-LABEL: name: rotl_i3284 ; RV32I: liveins: $x10, $x1185 ; RV32I-NEXT: {{ $}}86 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x1087 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x1188 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 089 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3190 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]91 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]92 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)93 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]94 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND1]](s32)95 ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[LSHR]]96 ; RV32I-NEXT: $x10 = COPY [[OR]](s32)97 ; RV32I-NEXT: PseudoRET implicit $x1098 ;99 ; RV32ZBB_OR_RV32ZBKB-LABEL: name: rotl_i32100 ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11101 ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}102 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10103 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11104 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[COPY]], [[COPY1]](s32)105 ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[ROTL]](s32)106 ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10107 %0:_(s32) = COPY $x10108 %1:_(s32) = COPY $x11109 %2:_(s32) = G_ROTL %0, %1(s32)110 $x10 = COPY %2(s32)111 PseudoRET implicit $x10112 113...114---115name: rotl_i64116body: |117 bb.1:118 liveins: $x10, $x11, $x12, $x13119 120 ; CHECK-LABEL: name: rotl_i64121 ; CHECK: liveins: $x10, $x11, $x12, $x13122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10124 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11125 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12126 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0127 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63128 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]129 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]130 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32131 ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[C2]]132 ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND]]133 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[C2]]134 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C]]135 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND]](s32)136 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB2]](s32)137 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[AND]](s32)138 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL1]]139 ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB1]](s32)140 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[SHL]], [[C]]141 ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[SHL2]]142 ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY1]], [[SELECT1]]143 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]144 ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[C2]]145 ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND1]]146 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[C2]]147 ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[C]]148 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND1]](s32)149 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND1]](s32)150 ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB4]](s32)151 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[SHL3]]152 ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB3]](s32)153 ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR1]], [[LSHR3]]154 ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[COPY]], [[SELECT3]]155 ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[LSHR1]], [[C]]156 ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[SELECT4]]157 ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT2]], [[SELECT5]]158 ; CHECK-NEXT: $x10 = COPY [[OR2]](s32)159 ; CHECK-NEXT: $x11 = COPY [[OR3]](s32)160 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11161 %2:_(s32) = COPY $x10162 %3:_(s32) = COPY $x11163 %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)164 %4:_(s32) = COPY $x12165 %5:_(s32) = COPY $x13166 %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)167 %6:_(s64) = G_ROTL %0, %1(s64)168 %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)169 $x10 = COPY %7(s32)170 $x11 = COPY %8(s32)171 PseudoRET implicit $x10, implicit $x11172 173...174---175name: rotr_i8176body: |177 bb.1:178 liveins: $x10, $x11179 180 ; CHECK-LABEL: name: rotr_i8181 ; CHECK: liveins: $x10, $x11182 ; CHECK-NEXT: {{ $}}183 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10184 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11185 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0186 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 7187 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]188 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]189 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255190 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]191 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]192 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)193 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]194 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32)195 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]196 ; CHECK-NEXT: $x10 = COPY [[OR]](s32)197 ; CHECK-NEXT: PseudoRET implicit $x10198 %2:_(s32) = COPY $x10199 %0:_(s8) = G_TRUNC %2(s32)200 %3:_(s32) = COPY $x11201 %1:_(s8) = G_TRUNC %3(s32)202 %4:_(s8) = G_ROTR %0, %1(s8)203 %5:_(s32) = G_ANYEXT %4(s8)204 $x10 = COPY %5(s32)205 PseudoRET implicit $x10206 207...208---209name: rotr_i16210body: |211 bb.1:212 liveins: $x10, $x11213 214 ; CHECK-LABEL: name: rotr_i16215 ; CHECK: liveins: $x10, $x11216 ; CHECK-NEXT: {{ $}}217 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10218 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11219 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0220 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 15221 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]222 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]223 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535224 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[AND]], [[C2]]225 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C2]]226 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[AND1]](s32)227 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]228 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND3]](s32)229 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]230 ; CHECK-NEXT: $x10 = COPY [[OR]](s32)231 ; CHECK-NEXT: PseudoRET implicit $x10232 %2:_(s32) = COPY $x10233 %0:_(s16) = G_TRUNC %2(s32)234 %3:_(s32) = COPY $x11235 %1:_(s16) = G_TRUNC %3(s32)236 %4:_(s16) = G_ROTR %0, %1(s16)237 %5:_(s32) = G_ANYEXT %4(s16)238 $x10 = COPY %5(s32)239 PseudoRET implicit $x10240 241...242---243name: rotr_i32244body: |245 bb.1:246 liveins: $x10, $x11247 248 ; RV32I-LABEL: name: rotr_i32249 ; RV32I: liveins: $x10, $x11250 ; RV32I-NEXT: {{ $}}251 ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10252 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11253 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0254 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31255 ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY1]]256 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]257 ; RV32I-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND]](s32)258 ; RV32I-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]259 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)260 ; RV32I-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]]261 ; RV32I-NEXT: $x10 = COPY [[OR]](s32)262 ; RV32I-NEXT: PseudoRET implicit $x10263 ;264 ; RV32ZBB_OR_RV32ZBKB-LABEL: name: rotr_i32265 ; RV32ZBB_OR_RV32ZBKB: liveins: $x10, $x11266 ; RV32ZBB_OR_RV32ZBKB-NEXT: {{ $}}267 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10268 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11269 ; RV32ZBB_OR_RV32ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[COPY]], [[COPY1]](s32)270 ; RV32ZBB_OR_RV32ZBKB-NEXT: $x10 = COPY [[ROTR]](s32)271 ; RV32ZBB_OR_RV32ZBKB-NEXT: PseudoRET implicit $x10272 %0:_(s32) = COPY $x10273 %1:_(s32) = COPY $x11274 %2:_(s32) = G_ROTR %0, %1(s32)275 $x10 = COPY %2(s32)276 PseudoRET implicit $x10277 278...279---280name: rotr_i64281body: |282 bb.1:283 liveins: $x10, $x11, $x12, $x13284 285 ; CHECK-LABEL: name: rotr_i64286 ; CHECK: liveins: $x10, $x11, $x12, $x13287 ; CHECK-NEXT: {{ $}}288 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10289 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11290 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12291 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0292 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 63293 ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY2]]294 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]295 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32296 ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[C2]]297 ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND]]298 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND]](s32), [[C2]]299 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND]](s32), [[C]]300 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[AND]](s32)301 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[AND]](s32)302 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[SUB2]](s32)303 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL]]304 ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[SUB1]](s32)305 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[OR]], [[LSHR2]]306 ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY]], [[SELECT]]307 ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[LSHR]], [[C]]308 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C1]]309 ; CHECK-NEXT: [[SUB3:%[0-9]+]]:_(s32) = G_SUB [[AND1]], [[C2]]310 ; CHECK-NEXT: [[SUB4:%[0-9]+]]:_(s32) = G_SUB [[C2]], [[AND1]]311 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[AND1]](s32), [[C2]]312 ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[AND1]](s32), [[C]]313 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[AND1]](s32)314 ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[SUB4]](s32)315 ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[AND1]](s32)316 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL2]]317 ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[SUB3]](s32)318 ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[SHL1]], [[C]]319 ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[OR1]], [[SHL3]]320 ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s32), [[COPY1]], [[SELECT4]]321 ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT1]], [[SELECT3]]322 ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[SELECT2]], [[SELECT5]]323 ; CHECK-NEXT: $x10 = COPY [[OR2]](s32)324 ; CHECK-NEXT: $x11 = COPY [[OR3]](s32)325 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11326 %2:_(s32) = COPY $x10327 %3:_(s32) = COPY $x11328 %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)329 %4:_(s32) = COPY $x12330 %5:_(s32) = COPY $x13331 %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)332 %6:_(s64) = G_ROTR %0, %1(s64)333 %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)334 $x10 = COPY %7(s32)335 $x11 = COPY %8(s32)336 PseudoRET implicit $x10, implicit $x11337 338...339