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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+zve32x -run-pass=legalizer %s -o - | FileCheck %s3# RUN: llc -mtriple=riscv64 -mattr=+zve32x -run-pass=legalizer %s -o - | FileCheck %s4---5name: test_nxv2i86body: |7 bb.0.entry:8 9 ; CHECK-LABEL: name: test_nxv2i810 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v811 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v912 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 2 x s8>) = G_ADD [[COPY]], [[COPY1]]13 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s8>)14 ; CHECK-NEXT: PseudoRET implicit $v815 %0:_(<vscale x 2 x s8>) = COPY $v816 %1:_(<vscale x 2 x s8>) = COPY $v917 %2:_(<vscale x 2 x s8>) = G_ADD %0, %118 $v8 = COPY %2(<vscale x 2 x s8>)19 PseudoRET implicit $v820 21...22---23name: test_nxv4i824body: |25 bb.0.entry:26 27 ; CHECK-LABEL: name: test_nxv4i828 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v829 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v930 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 4 x s8>) = G_ADD [[COPY]], [[COPY1]]31 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s8>)32 ; CHECK-NEXT: PseudoRET implicit $v833 %0:_(<vscale x 4 x s8>) = COPY $v834 %1:_(<vscale x 4 x s8>) = COPY $v935 %2:_(<vscale x 4 x s8>) = G_ADD %0, %136 $v8 = COPY %2(<vscale x 4 x s8>)37 PseudoRET implicit $v838 39...40---41name: test_nxv8i842body: |43 bb.0.entry:44 45 ; CHECK-LABEL: name: test_nxv8i846 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v847 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v948 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_ADD [[COPY]], [[COPY1]]49 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 8 x s8>)50 ; CHECK-NEXT: PseudoRET implicit $v851 %0:_(<vscale x 8 x s8>) = COPY $v852 %1:_(<vscale x 8 x s8>) = COPY $v953 %2:_(<vscale x 8 x s8>) = G_ADD %0, %154 $v8 = COPY %2(<vscale x 8 x s8>)55 PseudoRET implicit $v856 57...58---59name: test_nxv16i860body: |61 bb.0.entry:62 63 ; CHECK-LABEL: name: test_nxv16i864 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m265 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v10m266 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_ADD [[COPY]], [[COPY1]]67 ; CHECK-NEXT: $v8m2 = COPY [[ADD]](<vscale x 16 x s8>)68 ; CHECK-NEXT: PseudoRET implicit $v8m269 %0:_(<vscale x 16 x s8>) = COPY $v8m270 %1:_(<vscale x 16 x s8>) = COPY $v10m271 %2:_(<vscale x 16 x s8>) = G_ADD %0, %172 $v8m2 = COPY %2(<vscale x 16 x s8>)73 PseudoRET implicit $v8m274 75...76---77name: test_nxv32i878body: |79 bb.0.entry:80 81 ; CHECK-LABEL: name: test_nxv32i882 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m483 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v12m484 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 32 x s8>) = G_ADD [[COPY]], [[COPY1]]85 ; CHECK-NEXT: $v8m4 = COPY [[ADD]](<vscale x 32 x s8>)86 ; CHECK-NEXT: PseudoRET implicit $v8m487 %0:_(<vscale x 32 x s8>) = COPY $v8m488 %1:_(<vscale x 32 x s8>) = COPY $v12m489 %2:_(<vscale x 32 x s8>) = G_ADD %0, %190 $v8m4 = COPY %2(<vscale x 32 x s8>)91 PseudoRET implicit $v8m492 93...94---95name: test_nxv64i896body: |97 bb.0.entry:98 99 ; CHECK-LABEL: name: test_nxv64i8100 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8101 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v16m8102 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 64 x s8>) = G_ADD [[COPY]], [[COPY1]]103 ; CHECK-NEXT: $v8m8 = COPY [[ADD]](<vscale x 64 x s8>)104 ; CHECK-NEXT: PseudoRET implicit $v8m8105 %0:_(<vscale x 64 x s8>) = COPY $v8m8106 %1:_(<vscale x 64 x s8>) = COPY $v16m8107 %2:_(<vscale x 64 x s8>) = G_ADD %0, %1108 $v8m8 = COPY %2(<vscale x 64 x s8>)109 PseudoRET implicit $v8m8110 111...112---113name: test_nxv2i16114body: |115 bb.0.entry:116 117 ; CHECK-LABEL: name: test_nxv2i16118 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8119 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v9120 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 2 x s16>) = G_ADD [[COPY]], [[COPY1]]121 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s16>)122 ; CHECK-NEXT: PseudoRET implicit $v8123 %0:_(<vscale x 2 x s16>) = COPY $v8124 %1:_(<vscale x 2 x s16>) = COPY $v9125 %2:_(<vscale x 2 x s16>) = G_ADD %0, %1126 $v8 = COPY %2(<vscale x 2 x s16>)127 PseudoRET implicit $v8128 129...130---131name: test_nxv4i16132body: |133 bb.0.entry:134 135 ; CHECK-LABEL: name: test_nxv4i16136 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8137 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v9138 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_ADD [[COPY]], [[COPY1]]139 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s16>)140 ; CHECK-NEXT: PseudoRET implicit $v8141 %0:_(<vscale x 4 x s16>) = COPY $v8142 %1:_(<vscale x 4 x s16>) = COPY $v9143 %2:_(<vscale x 4 x s16>) = G_ADD %0, %1144 $v8 = COPY %2(<vscale x 4 x s16>)145 PseudoRET implicit $v8146 147...148---149name: test_nxv8i16150body: |151 bb.0.entry:152 153 ; CHECK-LABEL: name: test_nxv8i16154 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2155 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v10m2156 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 8 x s16>) = G_ADD [[COPY]], [[COPY1]]157 ; CHECK-NEXT: $v8m2 = COPY [[ADD]](<vscale x 8 x s16>)158 ; CHECK-NEXT: PseudoRET implicit $v8m2159 %0:_(<vscale x 8 x s16>) = COPY $v8m2160 %1:_(<vscale x 8 x s16>) = COPY $v10m2161 %2:_(<vscale x 8 x s16>) = G_ADD %0, %1162 $v8m2 = COPY %2(<vscale x 8 x s16>)163 PseudoRET implicit $v8m2164 165...166---167name: test_nxv16i16168body: |169 bb.0.entry:170 171 ; CHECK-LABEL: name: test_nxv16i16172 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4173 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v12m4174 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 16 x s16>) = G_ADD [[COPY]], [[COPY1]]175 ; CHECK-NEXT: $v8m4 = COPY [[ADD]](<vscale x 16 x s16>)176 ; CHECK-NEXT: PseudoRET implicit $v8m4177 %0:_(<vscale x 16 x s16>) = COPY $v8m4178 %1:_(<vscale x 16 x s16>) = COPY $v12m4179 %2:_(<vscale x 16 x s16>) = G_ADD %0, %1180 $v8m4 = COPY %2(<vscale x 16 x s16>)181 PseudoRET implicit $v8m4182 183...184---185name: test_nxv32i16186body: |187 bb.0.entry:188 189 ; CHECK-LABEL: name: test_nxv32i16190 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8191 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v16m8192 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 32 x s16>) = G_ADD [[COPY]], [[COPY1]]193 ; CHECK-NEXT: $v8m8 = COPY [[ADD]](<vscale x 32 x s16>)194 ; CHECK-NEXT: PseudoRET implicit $v8m8195 %0:_(<vscale x 32 x s16>) = COPY $v8m8196 %1:_(<vscale x 32 x s16>) = COPY $v16m8197 %2:_(<vscale x 32 x s16>) = G_ADD %0, %1198 $v8m8 = COPY %2(<vscale x 32 x s16>)199 PseudoRET implicit $v8m8200 201...202---203name: test_nxv2i32204body: |205 bb.0.entry:206 207 ; CHECK-LABEL: name: test_nxv2i32208 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8209 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v9210 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_ADD [[COPY]], [[COPY1]]211 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s32>)212 ; CHECK-NEXT: PseudoRET implicit $v8213 %0:_(<vscale x 2 x s32>) = COPY $v8214 %1:_(<vscale x 2 x s32>) = COPY $v9215 %2:_(<vscale x 2 x s32>) = G_ADD %0, %1216 $v8 = COPY %2(<vscale x 2 x s32>)217 PseudoRET implicit $v8218 219...220---221name: test_nxv4i32222body: |223 bb.0.entry:224 225 ; CHECK-LABEL: name: test_nxv4i32226 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2227 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v10m2228 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 4 x s32>) = G_ADD [[COPY]], [[COPY1]]229 ; CHECK-NEXT: $v8m2 = COPY [[ADD]](<vscale x 4 x s32>)230 ; CHECK-NEXT: PseudoRET implicit $v8m2231 %0:_(<vscale x 4 x s32>) = COPY $v8m2232 %1:_(<vscale x 4 x s32>) = COPY $v10m2233 %2:_(<vscale x 4 x s32>) = G_ADD %0, %1234 $v8m2 = COPY %2(<vscale x 4 x s32>)235 PseudoRET implicit $v8m2236 237...238---239name: test_nxv8i32240body: |241 bb.0.entry:242 243 ; CHECK-LABEL: name: test_nxv8i32244 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4245 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v12m4246 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 8 x s32>) = G_ADD [[COPY]], [[COPY1]]247 ; CHECK-NEXT: $v8m4 = COPY [[ADD]](<vscale x 8 x s32>)248 ; CHECK-NEXT: PseudoRET implicit $v8m4249 %0:_(<vscale x 8 x s32>) = COPY $v8m4250 %1:_(<vscale x 8 x s32>) = COPY $v12m4251 %2:_(<vscale x 8 x s32>) = G_ADD %0, %1252 $v8m4 = COPY %2(<vscale x 8 x s32>)253 PseudoRET implicit $v8m4254 255...256---257name: test_nxv16i32258body: |259 bb.0.entry:260 261 ; CHECK-LABEL: name: test_nxv16i32262 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8263 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v16m8264 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<vscale x 16 x s32>) = G_ADD [[COPY]], [[COPY1]]265 ; CHECK-NEXT: $v8m8 = COPY [[ADD]](<vscale x 16 x s32>)266 ; CHECK-NEXT: PseudoRET implicit $v8m8267 %0:_(<vscale x 16 x s32>) = COPY $v8m8268 %1:_(<vscale x 16 x s32>) = COPY $v16m8269 %2:_(<vscale x 16 x s32>) = G_ADD %0, %1270 $v8m8 = COPY %2(<vscale x 16 x s32>)271 PseudoRET implicit $v8m8272 273...274 275