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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV323# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,RV644 5# Special handling for i1-element vectors with non-zero index6---7name: extract_subvector_nxv2i1_nxv4i18legalized: false9tracksRegLiveness: true10body: |11 bb.0.entry:12 ; RV32-LABEL: name: extract_subvector_nxv2i1_nxv4i113 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF14 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 015 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32)16 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 117 ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32)18 ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]19 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB20 ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 221 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C2]](s32)22 ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -123 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C3]](s32)24 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF25 ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]], 326 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 4 x s8>), 027 ; RV32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 028 ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C4]](s32)29 ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](<vscale x 2 x s8>), [[SPLAT_VECTOR2]]30 ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>)31 ; RV32-NEXT: PseudoRET implicit $v832 ;33 ; RV64-LABEL: name: extract_subvector_nxv2i1_nxv4i134 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF35 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 036 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s64)37 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 138 ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s64)39 ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[DEF]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]40 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB41 ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 242 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C2]](s64)43 ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -144 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C3]](s64)45 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF46 ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]], 347 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 4 x s8>), 048 ; RV64-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 049 ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C4]](s64)50 ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](<vscale x 2 x s8>), [[SPLAT_VECTOR2]]51 ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>)52 ; RV64-NEXT: PseudoRET implicit $v853 %0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF54 %1:_(<vscale x 2 x s1>) = G_EXTRACT_SUBVECTOR %0(<vscale x 4 x s1>), 255 $v8 = COPY %1(<vscale x 2 x s1>)56 PseudoRET implicit $v857...58---59name: extract_subvector_nxv2i1_nxv8i160legalized: false61tracksRegLiveness: true62body: |63 bb.0.entry:64 ; RV32-LABEL: name: extract_subvector_nxv2i1_nxv8i165 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF66 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 067 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32)68 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 169 ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32)70 ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]71 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB72 ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 273 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C2]](s32)74 ; RV32-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -175 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C3]](s32)76 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF77 ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]], 378 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 8 x s8>), 079 ; RV32-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 080 ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C4]](s32)81 ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](<vscale x 2 x s8>), [[SPLAT_VECTOR2]]82 ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>)83 ; RV32-NEXT: PseudoRET implicit $v884 ;85 ; RV64-LABEL: name: extract_subvector_nxv2i1_nxv8i186 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF87 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 088 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s64)89 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 190 ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s64)91 ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[DEF]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]92 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB93 ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 294 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C2]](s64)95 ; RV64-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 -196 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C3]](s64)97 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF98 ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[SELECT]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 2 x s1>), [[C3]], 399 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 8 x s8>), 0100 ; RV64-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 0101 ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C4]](s64)102 ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 2 x s1>) = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](<vscale x 2 x s8>), [[SPLAT_VECTOR2]]103 ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 2 x s1>)104 ; RV64-NEXT: PseudoRET implicit $v8105 %0:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF106 %1:_(<vscale x 2 x s1>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s1>), 2107 $v8 = COPY %1(<vscale x 2 x s1>)108 PseudoRET implicit $v8109...110---111name: extract_subvector_nxv4i1_nxv64i1112legalized: false113tracksRegLiveness: true114body: |115 bb.0.entry:116 ; RV32-LABEL: name: extract_subvector_nxv4i1_nxv64i1117 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF118 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0119 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s32)120 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1121 ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s32)122 ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]123 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_EXTRACT_SUBVECTOR [[SELECT]](<vscale x 64 x s8>), 16124 ; RV32-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0125 ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C2]](s32)126 ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](<vscale x 4 x s8>), [[SPLAT_VECTOR2]]127 ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>)128 ; RV32-NEXT: PseudoRET implicit $v8129 ;130 ; RV64-LABEL: name: extract_subvector_nxv4i1_nxv64i1131 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF132 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0133 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s64)134 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1135 ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C1]](s64)136 ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 64 x s8>) = G_SELECT [[DEF]](<vscale x 64 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]137 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_EXTRACT_SUBVECTOR [[SELECT]](<vscale x 64 x s8>), 16138 ; RV64-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0139 ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C2]](s64)140 ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[EXTRACT_SUBVECTOR]](<vscale x 4 x s8>), [[SPLAT_VECTOR2]]141 ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>)142 ; RV64-NEXT: PseudoRET implicit $v8143 %0:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF144 %1:_(<vscale x 4 x s1>) = G_EXTRACT_SUBVECTOR %0(<vscale x 64 x s1>), 16145 $v8 = COPY %1(<vscale x 4 x s1>)146 PseudoRET implicit $v8147...148---149name: extract_subvector_nxv32i1_nxv64i1150legalized: false151tracksRegLiveness: true152body: |153 bb.0.entry:154 ; RV32-LABEL: name: extract_subvector_nxv32i1_nxv64i1155 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF156 ; RV32-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 8 x s8>) = G_BITCAST [[DEF]](<vscale x 64 x s1>)157 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB158 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1159 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)160 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1161 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s32)162 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF163 ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[BITCAST]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 4 x s1>), [[C1]], 3164 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 8 x s8>), 0165 ; RV32-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_BITCAST [[EXTRACT_SUBVECTOR]](<vscale x 4 x s8>)166 ; RV32-NEXT: $v8 = COPY [[BITCAST1]](<vscale x 32 x s1>)167 ; RV32-NEXT: PseudoRET implicit $v8168 ;169 ; RV64-LABEL: name: extract_subvector_nxv32i1_nxv64i1170 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF171 ; RV64-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 8 x s8>) = G_BITCAST [[DEF]](<vscale x 64 x s1>)172 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB173 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1174 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)175 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1176 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C1]](s64)177 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF178 ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEDOWN_VL [[DEF1]], [[BITCAST]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 4 x s1>), [[C1]], 3179 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 8 x s8>), 0180 ; RV64-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_BITCAST [[EXTRACT_SUBVECTOR]](<vscale x 4 x s8>)181 ; RV64-NEXT: $v8 = COPY [[BITCAST1]](<vscale x 32 x s1>)182 ; RV64-NEXT: PseudoRET implicit $v8183 %0:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF184 %1:_(<vscale x 32 x s1>) = G_EXTRACT_SUBVECTOR %0(<vscale x 64 x s1>), 32185 $v8 = COPY %1(<vscale x 32 x s1>)186 PseudoRET implicit $v8187...188 189# i1-element vectors with zero index190---191name: extract_subvector_nxv1i1_nxv4i1_zero192legalized: false193tracksRegLiveness: true194body: |195 bb.0.entry:196 ; CHECK-LABEL: name: extract_subvector_nxv1i1_nxv4i1_zero197 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF198 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s1>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s1>), 0199 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s1>)200 ; CHECK-NEXT: PseudoRET implicit $v8201 %0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF202 %1:_(<vscale x 1 x s1>) = G_EXTRACT_SUBVECTOR %0(<vscale x 4 x s1>), 0203 $v8 = COPY %1(<vscale x 1 x s1>)204 PseudoRET implicit $v8205...206---207name: extract_subvector_nxv4i1_nxv8i1_zero208legalized: false209tracksRegLiveness: true210body: |211 bb.0.entry:212 ; CHECK-LABEL: name: extract_subvector_nxv4i1_nxv8i1_zero213 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF214 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s1>), 0215 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 4 x s1>)216 ; CHECK-NEXT: PseudoRET implicit $v8217 %0:_(<vscale x 8 x s1>) = G_IMPLICIT_DEF218 %1:_(<vscale x 4 x s1>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s1>), 0219 $v8 = COPY %1(<vscale x 4 x s1>)220 PseudoRET implicit $v8221...222---223name: extract_subvector_nxv32i1_nxv64i1_zero224legalized: false225tracksRegLiveness: true226body: |227 bb.0.entry:228 ; CHECK-LABEL: name: extract_subvector_nxv32i1_nxv64i1_zero229 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF230 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 8 x s8>) = G_BITCAST [[DEF]](<vscale x 64 x s1>)231 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_EXTRACT_SUBVECTOR [[BITCAST]](<vscale x 8 x s8>), 0232 ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 32 x s1>) = G_BITCAST [[EXTRACT_SUBVECTOR]](<vscale x 4 x s8>)233 ; CHECK-NEXT: $v8 = COPY [[BITCAST1]](<vscale x 32 x s1>)234 ; CHECK-NEXT: PseudoRET implicit $v8235 %0:_(<vscale x 64 x s1>) = G_IMPLICIT_DEF236 %1:_(<vscale x 32 x s1>) = G_EXTRACT_SUBVECTOR %0(<vscale x 64 x s1>), 0237 $v8 = COPY %1(<vscale x 32 x s1>)238 PseudoRET implicit $v8239...240 241# Extract with zero index242---243name: extract_subvector_nxv1i8_nxv2i8_zero244legalized: false245tracksRegLiveness: true246body: |247 bb.0.entry:248 ; CHECK-LABEL: name: extract_subvector_nxv1i8_nxv2i8_zero249 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF250 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 2 x s8>), 0251 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s8>)252 ; CHECK-NEXT: PseudoRET implicit $v8253 %0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF254 %1:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR %0(<vscale x 2 x s8>), 0255 $v8 = COPY %1(<vscale x 1 x s8>)256 PseudoRET implicit $v8257...258---259name: extract_subvector_nxv2i16_nxv4i16_zero260legalized: false261tracksRegLiveness: true262body: |263 bb.0.entry:264 ; CHECK-LABEL: name: extract_subvector_nxv2i16_nxv4i16_zero265 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF266 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 4 x s16>), 0267 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 2 x s16>)268 ; CHECK-NEXT: PseudoRET implicit $v8269 %0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF270 %1:_(<vscale x 2 x s16>) = G_EXTRACT_SUBVECTOR %0(<vscale x 4 x s16>), 0271 $v8 = COPY %1(<vscale x 2 x s16>)272 PseudoRET implicit $v8273...274---275name: extract_subvector_nxv4i32_nxv8i32_zero276legalized: false277tracksRegLiveness: true278body: |279 bb.0.entry:280 ; CHECK-LABEL: name: extract_subvector_nxv4i32_nxv8i32_zero281 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF282 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 0283 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 4 x s32>)284 ; CHECK-NEXT: PseudoRET implicit $v8285 %0:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF286 %1:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s32>), 0287 $v8 = COPY %1(<vscale x 4 x s32>)288 PseudoRET implicit $v8289...290---291name: extract_subvector_nxv4i8_nxv8i64_zero292legalized: false293tracksRegLiveness: true294body: |295 bb.0.entry:296 ; CHECK-LABEL: name: extract_subvector_nxv4i8_nxv8i64_zero297 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF298 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 0299 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 4 x s64>)300 ; CHECK-NEXT: PseudoRET implicit $v8301 %0:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF302 %1:_(<vscale x 4 x s64>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s64>), 0303 $v8 = COPY %1(<vscale x 4 x s64>)304 PseudoRET implicit $v8305...306 307# Extract with non-zero index308---309name: extract_subvector_nxv1i8_nxv2i8310legalized: false311tracksRegLiveness: true312body: |313 bb.0.entry:314 ; RV32-LABEL: name: extract_subvector_nxv1i8_nxv2i8315 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF316 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB317 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3318 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)319 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1320 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)321 ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3322 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s8>), 0323 ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s8>)324 ; RV32-NEXT: PseudoRET implicit $v8325 ;326 ; RV64-LABEL: name: extract_subvector_nxv1i8_nxv2i8327 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF328 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB329 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3330 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)331 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1332 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)333 ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3334 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s8>), 0335 ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s8>)336 ; RV64-NEXT: PseudoRET implicit $v8337 %0:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF338 %1:_(<vscale x 1 x s8>) = G_EXTRACT_SUBVECTOR %0(<vscale x 2 x s8>), 1339 $v8 = COPY %1(<vscale x 1 x s8>)340 PseudoRET implicit $v8341...342---343name: extract_subvector_nxv1i16_nxv4i16344legalized: false345tracksRegLiveness: true346body: |347 bb.0.entry:348 ; RV32-LABEL: name: extract_subvector_nxv1i16_nxv4i16349 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF350 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB351 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2352 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)353 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1354 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)355 ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3356 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 4 x s16>), 0357 ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s16>)358 ; RV32-NEXT: PseudoRET implicit $v8359 ;360 ; RV64-LABEL: name: extract_subvector_nxv1i16_nxv4i16361 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF362 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB363 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2364 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)365 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1366 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)367 ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEDOWN_VL [[DEF]], [[DEF]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3368 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 4 x s16>), 0369 ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 1 x s16>)370 ; RV64-NEXT: PseudoRET implicit $v8371 %0:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF372 %1:_(<vscale x 1 x s16>) = G_EXTRACT_SUBVECTOR %0(<vscale x 4 x s16>), 2373 $v8 = COPY %1(<vscale x 1 x s16>)374 PseudoRET implicit $v8375...376---377name: extract_subvector_nxv4i32_nxv8i32378legalized: false379tracksRegLiveness: true380body: |381 bb.0.entry:382 ; CHECK-LABEL: name: extract_subvector_nxv4i32_nxv8i32383 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF384 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s32>), 4385 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 4 x s32>)386 ; CHECK-NEXT: PseudoRET implicit $v8387 %0:_(<vscale x 8 x s32>) = G_IMPLICIT_DEF388 %1:_(<vscale x 4 x s32>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s32>), 4389 $v8 = COPY %1(<vscale x 4 x s32>)390 PseudoRET implicit $v8391...392---393name: extract_subvector_nxv2i64_nxv8i64394legalized: false395tracksRegLiveness: true396body: |397 bb.0.entry:398 ; CHECK-LABEL: name: extract_subvector_nxv2i64_nxv8i64399 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF400 ; CHECK-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 8 x s64>), 2401 ; CHECK-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR]](<vscale x 2 x s64>)402 ; CHECK-NEXT: PseudoRET implicit $v8403 %0:_(<vscale x 8 x s64>) = G_IMPLICIT_DEF404 %1:_(<vscale x 2 x s64>) = G_EXTRACT_SUBVECTOR %0(<vscale x 8 x s64>), 2405 $v8 = COPY %1(<vscale x 2 x s64>)406 PseudoRET implicit $v8407...408---409name: extract_subvector_subregidx_zero410legalized: false411tracksRegLiveness: true412body: |413 bb.0.entry:414 ; RV32-LABEL: name: extract_subvector_subregidx_zero415 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF416 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0417 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB418 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3419 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)420 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1421 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)422 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF423 ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3424 ; RV32-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s32>), 0425 ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]](<vscale x 1 x s32>)426 ; RV32-NEXT: PseudoRET implicit $v8427 ;428 ; RV64-LABEL: name: extract_subvector_subregidx_zero429 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF430 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 0431 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB432 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3433 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)434 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1435 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)436 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF437 ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3438 ; RV64-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s32>), 0439 ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]](<vscale x 1 x s32>)440 ; RV64-NEXT: PseudoRET implicit $v8441 %0:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF442 %1:_(<vscale x 1 x s32>) = G_EXTRACT_SUBVECTOR %0(<vscale x 16 x s32>), 1443 $v8 = COPY %1(<vscale x 1 x s32>)444 PseudoRET implicit $v8445...446---447name: extract_subvector_subregidx448legalized: false449tracksRegLiveness: true450body: |451 bb.0.entry:452 ; RV32-LABEL: name: extract_subvector_subregidx453 ; RV32: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF454 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 2455 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB456 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3457 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C]](s32)458 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1459 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s32)460 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF461 ; RV32-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s32), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3462 ; RV32-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s32>), 0463 ; RV32-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]](<vscale x 1 x s32>)464 ; RV32-NEXT: PseudoRET implicit $v8465 ;466 ; RV64-LABEL: name: extract_subvector_subregidx467 ; RV64: [[DEF:%[0-9]+]]:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF468 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_EXTRACT_SUBVECTOR [[DEF]](<vscale x 16 x s32>), 2469 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB470 ; RV64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3471 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C]](s64)472 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1473 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 1 x s1>) = G_VMSET_VL [[C1]](s64)474 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s32>) = G_IMPLICIT_DEF475 ; RV64-NEXT: [[VSLIDEDOWN_VL:%[0-9]+]]:_(<vscale x 2 x s32>) = G_VSLIDEDOWN_VL [[DEF1]], [[EXTRACT_SUBVECTOR]], [[LSHR]](s64), [[VMSET_VL]](<vscale x 1 x s1>), [[C1]], 3476 ; RV64-NEXT: [[EXTRACT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 1 x s32>) = G_EXTRACT_SUBVECTOR [[VSLIDEDOWN_VL]](<vscale x 2 x s32>), 0477 ; RV64-NEXT: $v8 = COPY [[EXTRACT_SUBVECTOR1]](<vscale x 1 x s32>)478 ; RV64-NEXT: PseudoRET implicit $v8479 %0:_(<vscale x 16 x s32>) = G_IMPLICIT_DEF480 %1:_(<vscale x 1 x s32>) = G_EXTRACT_SUBVECTOR %0(<vscale x 16 x s32>), 3481 $v8 = COPY %1(<vscale x 1 x s32>)482 PseudoRET implicit $v8483...484 485