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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,RV323# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,RV644 5 6# BigVec=G_IMPLICIT_DEF when index is non-zero7---8name: insert_subvector_nxv2i1_nxv4i1_undef_nonzero9legalized: false10tracksRegLiveness: true11body: |12 bb.0.entry:13 ; CHECK-LABEL: name: insert_subvector_nxv2i1_nxv4i1_undef_nonzero14 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF15 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF16 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_SUBVECTOR [[DEF]], [[DEF1]](<vscale x 2 x s1>), 217 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s1>)18 ; CHECK-NEXT: PseudoRET implicit $v819 %0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF20 %1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF21 %2:_(<vscale x 4 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 4 x s1>), %1, 222 $v8 = COPY %2(<vscale x 4 x s1>)23 PseudoRET implicit $v824...25 26# BigVec=G_IMPLICIT_DEF when index is zero27---28name: insert_subvector_nxv2i1_nxv4i1_undef_zero29legalized: false30tracksRegLiveness: true31body: |32 bb.0.entry:33 ; CHECK-LABEL: name: insert_subvector_nxv2i1_nxv4i1_undef_zero34 ; CHECK: [[DEF:%[0-9]+]]:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF35 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF36 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_SUBVECTOR [[DEF]], [[DEF1]](<vscale x 2 x s1>), 037 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s1>)38 ; CHECK-NEXT: PseudoRET implicit $v839 %0:_(<vscale x 4 x s1>) = G_IMPLICIT_DEF40 %1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF41 %2:_(<vscale x 4 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 4 x s1>), %1, 042 $v8 = COPY %2(<vscale x 4 x s1>)43 PseudoRET implicit $v844...45 46 47# Special handling for i1-element vectors with non-zero index48---49name: insert_subvector_nxv2i1_nxv4i150legalized: false51tracksRegLiveness: true52body: |53 bb.0.entry:54 liveins: $v855 ; RV32-LABEL: name: insert_subvector_nxv2i1_nxv4i156 ; RV32: liveins: $v857 ; RV32-NEXT: {{ $}}58 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v859 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF60 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 061 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s64)62 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 163 ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s64)64 ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]65 ; RV32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 066 ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C2]](s64)67 ; RV32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 168 ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C3]](s64)69 ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]]70 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF71 ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](<vscale x 2 x s8>), 072 ; RV32-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -173 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C4]](s64)74 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB75 ; RV32-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 276 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C5]](s64)77 ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB78 ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB1]], [[C5]](s64)79 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]]80 ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s64), 181 ; RV32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 082 ; RV32-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C6]](s64)83 ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[VSLIDEUP_VL]](<vscale x 4 x s8>), [[SPLAT_VECTOR4]]84 ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>)85 ; RV32-NEXT: PseudoRET implicit $v886 ;87 ; RV64-LABEL: name: insert_subvector_nxv2i1_nxv4i188 ; RV64: liveins: $v889 ; RV64-NEXT: {{ $}}90 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v891 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF92 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 093 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32)94 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 195 ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C1]](s32)96 ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SELECT [[COPY]](<vscale x 4 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]97 ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 098 ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C2]](s32)99 ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1100 ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C3]](s32)101 ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]]102 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_IMPLICIT_DEF103 ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](<vscale x 2 x s8>), 0104 ; RV64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1105 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C4]](s32)106 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB107 ; RV64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2108 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C5]](s32)109 ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB110 ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB1]], [[C5]](s32)111 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]]112 ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s8>) = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s32), 1113 ; RV64-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0114 ; RV64-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C6]](s32)115 ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 4 x s1>) = G_ICMP intpred(ne), [[VSLIDEUP_VL]](<vscale x 4 x s8>), [[SPLAT_VECTOR4]]116 ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 4 x s1>)117 ; RV64-NEXT: PseudoRET implicit $v8118 %0:_(<vscale x 4 x s1>) = COPY $v8119 %1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF120 %2:_(<vscale x 4 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 4 x s1>), %1, 2121 $v8 = COPY %2(<vscale x 4 x s1>)122 PseudoRET implicit $v8123...124---125name: insert_subvector_nxv4i1_nxv8i1126legalized: false127tracksRegLiveness: true128body: |129 bb.0.entry:130 liveins: $v8131 ; RV32-LABEL: name: insert_subvector_nxv4i1_nxv8i1132 ; RV32: liveins: $v8133 ; RV32-NEXT: {{ $}}134 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8135 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF136 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0137 ; RV32-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s64)138 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1139 ; RV32-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s64)140 ; RV32-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]141 ; RV32-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0142 ; RV32-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C2]](s64)143 ; RV32-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 1144 ; RV32-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C3]](s64)145 ; RV32-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]]146 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF147 ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](<vscale x 2 x s8>), 0148 ; RV32-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1149 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C4]](s64)150 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB151 ; RV32-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2152 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C5]](s64)153 ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB154 ; RV32-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 1155 ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB1]], [[C6]](s64)156 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]]157 ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s64), 0158 ; RV32-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 0159 ; RV32-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C7]](s64)160 ; RV32-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(ne), [[VSLIDEUP_VL]](<vscale x 8 x s8>), [[SPLAT_VECTOR4]]161 ; RV32-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>)162 ; RV32-NEXT: PseudoRET implicit $v8163 ;164 ; RV64-LABEL: name: insert_subvector_nxv4i1_nxv8i1165 ; RV64: liveins: $v8166 ; RV64-NEXT: {{ $}}167 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8168 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF169 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0170 ; RV64-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32)171 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1172 ; RV64-NEXT: [[SPLAT_VECTOR1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C1]](s32)173 ; RV64-NEXT: [[SELECT:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SELECT [[COPY]](<vscale x 8 x s1>), [[SPLAT_VECTOR1]], [[SPLAT_VECTOR]]174 ; RV64-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0175 ; RV64-NEXT: [[SPLAT_VECTOR2:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C2]](s32)176 ; RV64-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1177 ; RV64-NEXT: [[SPLAT_VECTOR3:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C3]](s32)178 ; RV64-NEXT: [[SELECT1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_SELECT [[DEF]](<vscale x 2 x s1>), [[SPLAT_VECTOR3]], [[SPLAT_VECTOR2]]179 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF180 ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[SELECT1]](<vscale x 2 x s8>), 0181 ; RV64-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1182 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C4]](s32)183 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB184 ; RV64-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 2185 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C5]](s32)186 ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB187 ; RV64-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1188 ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB1]], [[C6]](s32)189 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]]190 ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEUP_VL [[SELECT]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s32), 0191 ; RV64-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0192 ; RV64-NEXT: [[SPLAT_VECTOR4:%[0-9]+]]:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C7]](s32)193 ; RV64-NEXT: [[ICMP:%[0-9]+]]:_(<vscale x 8 x s1>) = G_ICMP intpred(ne), [[VSLIDEUP_VL]](<vscale x 8 x s8>), [[SPLAT_VECTOR4]]194 ; RV64-NEXT: $v8 = COPY [[ICMP]](<vscale x 8 x s1>)195 ; RV64-NEXT: PseudoRET implicit $v8196 %0:_(<vscale x 8 x s1>) = COPY $v8197 %1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF198 %2:_(<vscale x 8 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s1>), %1, 4199 $v8 = COPY %2(<vscale x 8 x s1>)200 PseudoRET implicit $v8201...202---203name: insert_subvector_nxv32i1_nxv64i1204legalized: false205tracksRegLiveness: true206body: |207 bb.0.entry:208 liveins: $v8209 ; RV32-LABEL: name: insert_subvector_nxv32i1_nxv64i1210 ; RV32: liveins: $v8211 ; RV32-NEXT: {{ $}}212 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8213 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF214 ; RV32-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 8 x s8>) = G_BITCAST [[COPY]](<vscale x 64 x s1>)215 ; RV32-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_BITCAST [[DEF]](<vscale x 32 x s1>)216 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF217 ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[BITCAST1]](<vscale x 4 x s8>), 0218 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1219 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s64)220 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB221 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1222 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C1]](s64)223 ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB224 ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB1]], [[C1]](s64)225 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]]226 ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEUP_VL [[BITCAST]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s64), 1227 ; RV32-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 64 x s1>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 8 x s8>)228 ; RV32-NEXT: $v8 = COPY [[BITCAST2]](<vscale x 64 x s1>)229 ; RV32-NEXT: PseudoRET implicit $v8230 ;231 ; RV64-LABEL: name: insert_subvector_nxv32i1_nxv64i1232 ; RV64: liveins: $v8233 ; RV64-NEXT: {{ $}}234 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8235 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF236 ; RV64-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 8 x s8>) = G_BITCAST [[COPY]](<vscale x 64 x s1>)237 ; RV64-NEXT: [[BITCAST1:%[0-9]+]]:_(<vscale x 4 x s8>) = G_BITCAST [[DEF]](<vscale x 32 x s1>)238 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 8 x s8>) = G_IMPLICIT_DEF239 ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[BITCAST1]](<vscale x 4 x s8>), 0240 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1241 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)242 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB243 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1244 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C1]](s32)245 ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB246 ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB1]], [[C1]](s32)247 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]]248 ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 8 x s8>) = G_VSLIDEUP_VL [[BITCAST]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](<vscale x 8 x s1>), [[ADD]](s32), 1249 ; RV64-NEXT: [[BITCAST2:%[0-9]+]]:_(<vscale x 64 x s1>) = G_BITCAST [[VSLIDEUP_VL]](<vscale x 8 x s8>)250 ; RV64-NEXT: $v8 = COPY [[BITCAST2]](<vscale x 64 x s1>)251 ; RV64-NEXT: PseudoRET implicit $v8252 %0:_(<vscale x 64 x s1>) = COPY $v8253 %1:_(<vscale x 32 x s1>) = G_IMPLICIT_DEF254 %2:_(<vscale x 64 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 64 x s1>), %1, 32255 $v8 = COPY %2(<vscale x 64 x s1>)256 PseudoRET implicit $v8257...258 259# i1-element vectors with zero index260---261name: insert_subvector_nxv2i1_nxv4i1_zero262legalized: false263tracksRegLiveness: true264body: |265 bb.0.entry:266 liveins: $v8267 ; CHECK-LABEL: name: insert_subvector_nxv2i1_nxv4i1_zero268 ; CHECK: liveins: $v8269 ; CHECK-NEXT: {{ $}}270 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s1>) = COPY $v8271 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF272 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s1>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 1 x s1>), 0273 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s1>)274 ; CHECK-NEXT: PseudoRET implicit $v8275 %0:_(<vscale x 4 x s1>) = COPY $v8276 %1:_(<vscale x 1 x s1>) = G_IMPLICIT_DEF277 %2:_(<vscale x 4 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 4 x s1>), %1, 0278 $v8 = COPY %2(<vscale x 4 x s1>)279 PseudoRET implicit $v8280...281---282name: insert_subvector_nxv4i1_nxv8i1_zero283legalized: false284tracksRegLiveness: true285body: |286 bb.0.entry:287 liveins: $v8288 ; CHECK-LABEL: name: insert_subvector_nxv4i1_nxv8i1_zero289 ; CHECK: liveins: $v8290 ; CHECK-NEXT: {{ $}}291 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s1>) = COPY $v8292 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF293 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s1>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 2 x s1>), 0294 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s1>)295 ; CHECK-NEXT: PseudoRET implicit $v8296 %0:_(<vscale x 8 x s1>) = COPY $v8297 %1:_(<vscale x 2 x s1>) = G_IMPLICIT_DEF298 %2:_(<vscale x 8 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s1>), %1, 0299 $v8 = COPY %2(<vscale x 8 x s1>)300 PseudoRET implicit $v8301...302---303name: insert_subvector_nxv32i1_nxv64i1_zero304legalized: false305tracksRegLiveness: true306body: |307 bb.0.entry:308 liveins: $v8309 ; CHECK-LABEL: name: insert_subvector_nxv32i1_nxv64i1_zero310 ; CHECK: liveins: $v8311 ; CHECK-NEXT: {{ $}}312 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 64 x s1>) = COPY $v8313 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF314 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 64 x s1>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 16 x s1>), 0315 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 64 x s1>)316 ; CHECK-NEXT: PseudoRET implicit $v8317 %0:_(<vscale x 64 x s1>) = COPY $v8318 %1:_(<vscale x 16 x s1>) = G_IMPLICIT_DEF319 %2:_(<vscale x 64 x s1>) = G_INSERT_SUBVECTOR %0(<vscale x 64 x s1>), %1, 0320 $v8 = COPY %2(<vscale x 64 x s1>)321 PseudoRET implicit $v8322...323 324# Insert with zero index325---326name: insert_subvector_nxv1i8_nxv2i8_zero327legalized: false328tracksRegLiveness: true329body: |330 bb.0.entry:331 liveins: $v8332 ; CHECK-LABEL: name: insert_subvector_nxv1i8_nxv2i8_zero333 ; CHECK: liveins: $v8334 ; CHECK-NEXT: {{ $}}335 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8336 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF337 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 1 x s8>), 0338 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 2 x s8>)339 ; CHECK-NEXT: PseudoRET implicit $v8340 %0:_(<vscale x 2 x s8>) = COPY $v8341 %1:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF342 %2:_(<vscale x 2 x s8>) = G_INSERT_SUBVECTOR %0(<vscale x 2 x s8>), %1, 0343 $v8 = COPY %2(<vscale x 2 x s8>)344 PseudoRET implicit $v8345...346---347name: insert_subvector_nxv2i16_nxv4i16_zero348legalized: false349tracksRegLiveness: true350body: |351 bb.0.entry:352 liveins: $v8353 ; CHECK-LABEL: name: insert_subvector_nxv2i16_nxv4i16_zero354 ; CHECK: liveins: $v8355 ; CHECK-NEXT: {{ $}}356 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8357 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF358 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 1 x s16>), 0359 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 4 x s16>)360 ; CHECK-NEXT: PseudoRET implicit $v8361 %0:_(<vscale x 4 x s16>) = COPY $v8362 %1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF363 %2:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR %0(<vscale x 4 x s16>), %1, 0364 $v8 = COPY %2(<vscale x 4 x s16>)365 PseudoRET implicit $v8366...367---368name: insert_subvector_nxv4i32_nxv8i32_zero369legalized: false370tracksRegLiveness: true371body: |372 bb.0.entry:373 liveins: $v8m4374 ; CHECK-LABEL: name: insert_subvector_nxv4i32_nxv8i32_zero375 ; CHECK: liveins: $v8m4376 ; CHECK-NEXT: {{ $}}377 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4378 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF379 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 4 x s32>), 0380 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)381 ; CHECK-NEXT: PseudoRET implicit $v8382 %0:_(<vscale x 8 x s32>) = COPY $v8m4383 %1:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF384 %2:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s32>), %1, 0385 $v8 = COPY %2(<vscale x 8 x s32>)386 PseudoRET implicit $v8387...388---389name: insert_subvector_nxv2i64_nxv8i64_zero390legalized: false391tracksRegLiveness: true392body: |393 bb.0.entry:394 liveins: $v8m8395 ; CHECK-LABEL: name: insert_subvector_nxv2i64_nxv8i64_zero396 ; CHECK: liveins: $v8m8397 ; CHECK-NEXT: {{ $}}398 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8399 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF400 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 2 x s64>), 0401 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)402 ; CHECK-NEXT: PseudoRET implicit $v8403 %0:_(<vscale x 8 x s64>) = COPY $v8m8404 %1:_(<vscale x 2 x s64>) = G_IMPLICIT_DEF405 %2:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s64>), %1, 0406 $v8 = COPY %2(<vscale x 8 x s64>)407 PseudoRET implicit $v8408...409 410# Insert with non-zero index411---412name: insert_subvector_nxv1i8_nxv2i8413legalized: false414tracksRegLiveness: true415body: |416 bb.0.entry:417 liveins: $v8418 ; RV32-LABEL: name: insert_subvector_nxv1i8_nxv2i8419 ; RV32: liveins: $v8420 ; RV32-NEXT: {{ $}}421 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8422 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF423 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF424 ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s8>), 0425 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1426 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s64)427 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB428 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3429 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C1]](s64)430 ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB431 ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB1]], [[C1]](s64)432 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]]433 ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](<vscale x 2 x s1>), [[ADD]](s64), 1434 ; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s8>)435 ; RV32-NEXT: PseudoRET implicit $v8436 ;437 ; RV64-LABEL: name: insert_subvector_nxv1i8_nxv2i8438 ; RV64: liveins: $v8439 ; RV64-NEXT: {{ $}}440 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v8441 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF442 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 2 x s8>) = G_IMPLICIT_DEF443 ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s8>), 0444 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1445 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 2 x s1>) = G_VMSET_VL [[C]](s32)446 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB447 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3448 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C1]](s32)449 ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB450 ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB1]], [[C1]](s32)451 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]]452 ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 2 x s8>) = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](<vscale x 2 x s1>), [[ADD]](s32), 1453 ; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 2 x s8>)454 ; RV64-NEXT: PseudoRET implicit $v8455 %0:_(<vscale x 2 x s8>) = COPY $v8456 %1:_(<vscale x 1 x s8>) = G_IMPLICIT_DEF457 %2:_(<vscale x 2 x s8>) = G_INSERT_SUBVECTOR %0(<vscale x 2 x s8>), %1, 1458 $v8 = COPY %2(<vscale x 2 x s8>)459 PseudoRET implicit $v8460...461---462name: insert_subvector_nxv2i16_nxv4i16463legalized: false464tracksRegLiveness: true465body: |466 bb.0.entry:467 liveins: $v8468 ; RV32-LABEL: name: insert_subvector_nxv2i16_nxv4i16469 ; RV32: liveins: $v8470 ; RV32-NEXT: {{ $}}471 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8472 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF473 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF474 ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s16>), 0475 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1476 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s64)477 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB478 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3479 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C1]](s64)480 ; RV32-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s64) = G_READ_VLENB481 ; RV32-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB1]], [[C1]](s64)482 ; RV32-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LSHR1]], [[LSHR]]483 ; RV32-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s64), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s64), 0484 ; RV32-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 4 x s16>)485 ; RV32-NEXT: PseudoRET implicit $v8486 ;487 ; RV64-LABEL: name: insert_subvector_nxv2i16_nxv4i16488 ; RV64: liveins: $v8489 ; RV64-NEXT: {{ $}}490 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8491 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF492 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF493 ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s16>), 0494 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1495 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 4 x s1>) = G_VMSET_VL [[C]](s32)496 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB497 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3498 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C1]](s32)499 ; RV64-NEXT: [[READ_VLENB1:%[0-9]+]]:_(s32) = G_READ_VLENB500 ; RV64-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB1]], [[C1]](s32)501 ; RV64-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LSHR1]], [[LSHR]]502 ; RV64-NEXT: [[VSLIDEUP_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VSLIDEUP_VL [[COPY]], [[INSERT_SUBVECTOR]], [[LSHR1]](s32), [[VMSET_VL]](<vscale x 4 x s1>), [[ADD]](s32), 0503 ; RV64-NEXT: $v8 = COPY [[VSLIDEUP_VL]](<vscale x 4 x s16>)504 ; RV64-NEXT: PseudoRET implicit $v8505 %0:_(<vscale x 4 x s16>) = COPY $v8506 %1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF507 %2:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR %0(<vscale x 4 x s16>), %1, 1508 $v8 = COPY %2(<vscale x 4 x s16>)509 PseudoRET implicit $v8510...511---512name: insert_subvector_nxv8i16_nxv1i16513legalized: false514tracksRegLiveness: true515body: |516 bb.0.entry:517 liveins: $v8m8518 ; RV32-LABEL: name: insert_subvector_nxv8i16_nxv1i16519 ; RV32: liveins: $v8m8520 ; RV32-NEXT: {{ $}}521 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8522 ; RV32-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF523 ; RV32-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 8 x s16>), 4524 ; RV32-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF525 ; RV32-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s16>), 0526 ; RV32-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1527 ; RV32-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s64)528 ; RV32-NEXT: [[READ_VLENB:%[0-9]+]]:_(s64) = G_READ_VLENB529 ; RV32-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3530 ; RV32-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[READ_VLENB]], [[C1]](s64)531 ; RV32-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]], [[LSHR]](s64)532 ; RV32-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](<vscale x 4 x s16>), 4533 ; RV32-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]](<vscale x 8 x s16>)534 ; RV32-NEXT: PseudoRET implicit $v8535 ;536 ; RV64-LABEL: name: insert_subvector_nxv8i16_nxv1i16537 ; RV64: liveins: $v8m8538 ; RV64-NEXT: {{ $}}539 ; RV64-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8540 ; RV64-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF541 ; RV64-NEXT: [[EXTRACT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_EXTRACT_SUBVECTOR [[COPY]](<vscale x 8 x s16>), 4542 ; RV64-NEXT: [[DEF1:%[0-9]+]]:_(<vscale x 4 x s16>) = G_IMPLICIT_DEF543 ; RV64-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_INSERT_SUBVECTOR [[DEF1]], [[DEF]](<vscale x 1 x s16>), 0544 ; RV64-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1545 ; RV64-NEXT: [[VMSET_VL:%[0-9]+]]:_(<vscale x 8 x s1>) = G_VMSET_VL [[C]](s32)546 ; RV64-NEXT: [[READ_VLENB:%[0-9]+]]:_(s32) = G_READ_VLENB547 ; RV64-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3548 ; RV64-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[READ_VLENB]], [[C1]](s32)549 ; RV64-NEXT: [[VMV_V_V_VL:%[0-9]+]]:_(<vscale x 4 x s16>) = G_VMV_V_V_VL [[EXTRACT_SUBVECTOR]], [[INSERT_SUBVECTOR]], [[LSHR]](s32)550 ; RV64-NEXT: [[INSERT_SUBVECTOR1:%[0-9]+]]:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR [[COPY]], [[VMV_V_V_VL]](<vscale x 4 x s16>), 4551 ; RV64-NEXT: $v8 = COPY [[INSERT_SUBVECTOR1]](<vscale x 8 x s16>)552 ; RV64-NEXT: PseudoRET implicit $v8553 %0:_(<vscale x 8 x s16>) = COPY $v8554 %1:_(<vscale x 1 x s16>) = G_IMPLICIT_DEF555 %2:_(<vscale x 8 x s16>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s16>), %1, 4556 $v8 = COPY %2(<vscale x 8 x s16>)557 PseudoRET implicit $v8558...559---560name: insert_subvector_nxv4i32_nxv8i32561legalized: false562tracksRegLiveness: true563body: |564 bb.0.entry:565 liveins: $v8m4566 ; CHECK-LABEL: name: insert_subvector_nxv4i32_nxv8i32567 ; CHECK: liveins: $v8m4568 ; CHECK-NEXT: {{ $}}569 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4570 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF571 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 4 x s32>), 4572 ; CHECK-NEXT: $v8m4 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s32>)573 ; CHECK-NEXT: PseudoRET implicit $v8m4574 %0:_(<vscale x 8 x s32>) = COPY $v8m4575 %1:_(<vscale x 4 x s32>) = G_IMPLICIT_DEF576 %2:_(<vscale x 8 x s32>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s32>), %1, 4577 $v8m4 = COPY %2(<vscale x 8 x s32>)578 PseudoRET implicit $v8m4579...580---581name: insert_subvector_nxv2i64_nxv8i64582legalized: false583tracksRegLiveness: true584body: |585 bb.0.entry:586 liveins: $v8m8587 ; CHECK-LABEL: name: insert_subvector_nxv2i64_nxv8i64588 ; CHECK: liveins: $v8m8589 ; CHECK-NEXT: {{ $}}590 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8591 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF592 ; CHECK-NEXT: [[INSERT_SUBVECTOR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR [[COPY]], [[DEF]](<vscale x 1 x s64>), 4593 ; CHECK-NEXT: $v8 = COPY [[INSERT_SUBVECTOR]](<vscale x 8 x s64>)594 ; CHECK-NEXT: PseudoRET implicit $v8595 %0:_(<vscale x 8 x s64>) = COPY $v8m8596 %1:_(<vscale x 1 x s64>) = G_IMPLICIT_DEF597 %2:_(<vscale x 8 x s64>) = G_INSERT_SUBVECTOR %0(<vscale x 8 x s64>), %1, 4598 $v8 = COPY %2(<vscale x 8 x s64>)599 PseudoRET implicit $v8600...601