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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s3# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s4--- |5 6 define <vscale x 1 x i8> @vload_nxv1i8(ptr %pa) #0 {7 %va = load <vscale x 1 x i8>, ptr %pa, align 18 ret <vscale x 1 x i8> %va9 }10 11 define <vscale x 2 x i8> @vload_nxv2i8(ptr %pa) #0 {12 %va = load <vscale x 2 x i8>, ptr %pa, align 213 ret <vscale x 2 x i8> %va14 }15 16 define <vscale x 4 x i8> @vload_nxv4i8(ptr %pa) #0 {17 %va = load <vscale x 4 x i8>, ptr %pa, align 418 ret <vscale x 4 x i8> %va19 }20 21 define <vscale x 8 x i8> @vload_nxv8i8(ptr %pa) #0 {22 %va = load <vscale x 8 x i8>, ptr %pa, align 823 ret <vscale x 8 x i8> %va24 }25 26 define <vscale x 16 x i8> @vload_nxv16i8(ptr %pa) #0 {27 %va = load <vscale x 16 x i8>, ptr %pa, align 1628 ret <vscale x 16 x i8> %va29 }30 31 define <vscale x 32 x i8> @vload_nxv32i8(ptr %pa) #0 {32 %va = load <vscale x 32 x i8>, ptr %pa, align 3233 ret <vscale x 32 x i8> %va34 }35 36 define <vscale x 64 x i8> @vload_nxv64i8(ptr %pa) #0 {37 %va = load <vscale x 64 x i8>, ptr %pa, align 6438 ret <vscale x 64 x i8> %va39 }40 41 define <vscale x 1 x i16> @vload_nxv1i16(ptr %pa) #0 {42 %va = load <vscale x 1 x i16>, ptr %pa, align 243 ret <vscale x 1 x i16> %va44 }45 46 define <vscale x 2 x i16> @vload_nxv2i16(ptr %pa) #0 {47 %va = load <vscale x 2 x i16>, ptr %pa, align 448 ret <vscale x 2 x i16> %va49 }50 51 define <vscale x 4 x i16> @vload_nxv4i16(ptr %pa) #0 {52 %va = load <vscale x 4 x i16>, ptr %pa, align 853 ret <vscale x 4 x i16> %va54 }55 56 define <vscale x 8 x i16> @vload_nxv8i16(ptr %pa) #0 {57 %va = load <vscale x 8 x i16>, ptr %pa, align 1658 ret <vscale x 8 x i16> %va59 }60 61 define <vscale x 16 x i16> @vload_nxv16i16(ptr %pa) #0 {62 %va = load <vscale x 16 x i16>, ptr %pa, align 3263 ret <vscale x 16 x i16> %va64 }65 66 define <vscale x 32 x i16> @vload_nxv32i16(ptr %pa) #0 {67 %va = load <vscale x 32 x i16>, ptr %pa, align 6468 ret <vscale x 32 x i16> %va69 }70 71 define <vscale x 1 x i32> @vload_nxv1i32(ptr %pa) #0 {72 %va = load <vscale x 1 x i32>, ptr %pa, align 473 ret <vscale x 1 x i32> %va74 }75 76 define <vscale x 2 x i32> @vload_nxv2i32(ptr %pa) #0 {77 %va = load <vscale x 2 x i32>, ptr %pa, align 878 ret <vscale x 2 x i32> %va79 }80 81 define <vscale x 4 x i32> @vload_nxv4i32(ptr %pa) #0 {82 %va = load <vscale x 4 x i32>, ptr %pa, align 1683 ret <vscale x 4 x i32> %va84 }85 86 define <vscale x 8 x i32> @vload_nxv8i32(ptr %pa) #0 {87 %va = load <vscale x 8 x i32>, ptr %pa, align 3288 ret <vscale x 8 x i32> %va89 }90 91 define <vscale x 16 x i32> @vload_nxv16i32(ptr %pa) #0 {92 %va = load <vscale x 16 x i32>, ptr %pa, align 6493 ret <vscale x 16 x i32> %va94 }95 96 define <vscale x 1 x i64> @vload_nxv1i64(ptr %pa) #0 {97 %va = load <vscale x 1 x i64>, ptr %pa, align 898 ret <vscale x 1 x i64> %va99 }100 101 define <vscale x 2 x i64> @vload_nxv2i64(ptr %pa) #0 {102 %va = load <vscale x 2 x i64>, ptr %pa, align 16103 ret <vscale x 2 x i64> %va104 }105 106 define <vscale x 4 x i64> @vload_nxv4i64(ptr %pa) #0 {107 %va = load <vscale x 4 x i64>, ptr %pa, align 32108 ret <vscale x 4 x i64> %va109 }110 111 define <vscale x 8 x i64> @vload_nxv8i64(ptr %pa) #0 {112 %va = load <vscale x 8 x i64>, ptr %pa, align 64113 ret <vscale x 8 x i64> %va114 }115 116 define <vscale x 16 x i8> @vload_nxv16i8_align1(ptr %pa) #0 {117 %va = load <vscale x 16 x i8>, ptr %pa, align 1118 ret <vscale x 16 x i8> %va119 }120 121 define <vscale x 16 x i8> @vload_nxv16i8_align2(ptr %pa) #0 {122 %va = load <vscale x 16 x i8>, ptr %pa, align 2123 ret <vscale x 16 x i8> %va124 }125 126 define <vscale x 16 x i8> @vload_nxv16i8_align16(ptr %pa) #0 {127 %va = load <vscale x 16 x i8>, ptr %pa, align 16128 ret <vscale x 16 x i8> %va129 }130 131 define <vscale x 16 x i8> @vload_nxv16i8_align64(ptr %pa) #0 {132 %va = load <vscale x 16 x i8>, ptr %pa, align 64133 ret <vscale x 16 x i8> %va134 }135 136 define <vscale x 4 x i16> @vload_nxv4i16_align1(ptr %pa) #0 {137 %va = load <vscale x 4 x i16>, ptr %pa, align 1138 ret <vscale x 4 x i16> %va139 }140 141 define <vscale x 4 x i16> @vload_nxv4i16_align2(ptr %pa) #0 {142 %va = load <vscale x 4 x i16>, ptr %pa, align 2143 ret <vscale x 4 x i16> %va144 }145 146 define <vscale x 4 x i16> @vload_nxv4i16_align4(ptr %pa) #0 {147 %va = load <vscale x 4 x i16>, ptr %pa, align 4148 ret <vscale x 4 x i16> %va149 }150 151 define <vscale x 4 x i16> @vload_nxv4i16_align8(ptr %pa) #0 {152 %va = load <vscale x 4 x i16>, ptr %pa, align 8153 ret <vscale x 4 x i16> %va154 }155 156 define <vscale x 4 x i16> @vload_nxv4i16_align16(ptr %pa) #0 {157 %va = load <vscale x 4 x i16>, ptr %pa, align 16158 ret <vscale x 4 x i16> %va159 }160 161 define <vscale x 2 x i32> @vload_nxv2i32_align2(ptr %pa) #0 {162 %va = load <vscale x 2 x i32>, ptr %pa, align 2163 ret <vscale x 2 x i32> %va164 }165 166 define <vscale x 2 x i32> @vload_nxv2i32_align4(ptr %pa) #0 {167 %va = load <vscale x 2 x i32>, ptr %pa, align 4168 ret <vscale x 2 x i32> %va169 }170 171 define <vscale x 2 x i32> @vload_nxv2i32_align8(ptr %pa) #0 {172 %va = load <vscale x 2 x i32>, ptr %pa, align 8173 ret <vscale x 2 x i32> %va174 }175 176 define <vscale x 2 x i32> @vload_nxv2i32_align16(ptr %pa) #0 {177 %va = load <vscale x 2 x i32>, ptr %pa, align 16178 ret <vscale x 2 x i32> %va179 }180 181 define <vscale x 2 x i32> @vload_nxv2i32_align256(ptr %pa) #0 {182 %va = load <vscale x 2 x i32>, ptr %pa, align 256183 ret <vscale x 2 x i32> %va184 }185 186 define <vscale x 2 x i64> @vload_nxv2i64_align4(ptr %pa) #0 {187 %va = load <vscale x 2 x i64>, ptr %pa, align 4188 ret <vscale x 2 x i64> %va189 }190 191 define <vscale x 2 x i64> @vload_nxv2i64_align8(ptr %pa) #0 {192 %va = load <vscale x 2 x i64>, ptr %pa, align 8193 ret <vscale x 2 x i64> %va194 }195 196 define <vscale x 2 x i64> @vload_nxv2i64_align16(ptr %pa) #0 {197 %va = load <vscale x 2 x i64>, ptr %pa, align 16198 ret <vscale x 2 x i64> %va199 }200 201 define <vscale x 2 x i64> @vload_nxv2i64_align32(ptr %pa) #0 {202 %va = load <vscale x 2 x i64>, ptr %pa, align 32203 ret <vscale x 2 x i64> %va204 }205 206 attributes #0 = { "target-features"="+v" }207 208...209---210name: vload_nxv1i8211body: |212 bb.1 (%ir-block.0):213 liveins: $x10214 215 ; CHECK-LABEL: name: vload_nxv1i8216 ; CHECK: liveins: $x10217 ; CHECK-NEXT: {{ $}}218 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10219 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s8>) from %ir.pa)220 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s8>)221 ; CHECK-NEXT: PseudoRET implicit $v8222 %0:_(p0) = COPY $x10223 %1:_(<vscale x 1 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s8>) from %ir.pa)224 $v8 = COPY %1(<vscale x 1 x s8>)225 PseudoRET implicit $v8226 227...228---229name: vload_nxv2i8230body: |231 bb.1 (%ir-block.0):232 liveins: $x10233 234 ; CHECK-LABEL: name: vload_nxv2i8235 ; CHECK: liveins: $x10236 ; CHECK-NEXT: {{ $}}237 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10238 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s8>) from %ir.pa)239 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s8>)240 ; CHECK-NEXT: PseudoRET implicit $v8241 %0:_(p0) = COPY $x10242 %1:_(<vscale x 2 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s8>) from %ir.pa)243 $v8 = COPY %1(<vscale x 2 x s8>)244 PseudoRET implicit $v8245 246...247---248name: vload_nxv4i8249body: |250 bb.1 (%ir-block.0):251 liveins: $x10252 253 ; CHECK-LABEL: name: vload_nxv4i8254 ; CHECK: liveins: $x10255 ; CHECK-NEXT: {{ $}}256 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10257 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s8>) from %ir.pa)258 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s8>)259 ; CHECK-NEXT: PseudoRET implicit $v8260 %0:_(p0) = COPY $x10261 %1:_(<vscale x 4 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s8>) from %ir.pa)262 $v8 = COPY %1(<vscale x 4 x s8>)263 PseudoRET implicit $v8264 265...266---267name: vload_nxv8i8268body: |269 bb.1 (%ir-block.0):270 liveins: $x10271 272 ; CHECK-LABEL: name: vload_nxv8i8273 ; CHECK: liveins: $x10274 ; CHECK-NEXT: {{ $}}275 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10276 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa)277 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 8 x s8>)278 ; CHECK-NEXT: PseudoRET implicit $v8279 %0:_(p0) = COPY $x10280 %1:_(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa)281 $v8 = COPY %1(<vscale x 8 x s8>)282 PseudoRET implicit $v8283 284...285---286name: vload_nxv16i8287body: |288 bb.1 (%ir-block.0):289 liveins: $x10290 291 ; CHECK-LABEL: name: vload_nxv16i8292 ; CHECK: liveins: $x10293 ; CHECK-NEXT: {{ $}}294 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10295 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)296 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)297 ; CHECK-NEXT: PseudoRET implicit $v8m2298 %0:_(p0) = COPY $x10299 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)300 $v8m2 = COPY %1(<vscale x 16 x s8>)301 PseudoRET implicit $v8m2302 303...304---305name: vload_nxv32i8306body: |307 bb.1 (%ir-block.0):308 liveins: $x10309 310 ; CHECK-LABEL: name: vload_nxv32i8311 ; CHECK: liveins: $x10312 ; CHECK-NEXT: {{ $}}313 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10314 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s8>) from %ir.pa)315 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 32 x s8>)316 ; CHECK-NEXT: PseudoRET implicit $v8m4317 %0:_(p0) = COPY $x10318 %1:_(<vscale x 32 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s8>) from %ir.pa)319 $v8m4 = COPY %1(<vscale x 32 x s8>)320 PseudoRET implicit $v8m4321 322...323---324name: vload_nxv64i8325body: |326 bb.1 (%ir-block.0):327 liveins: $x10328 329 ; CHECK-LABEL: name: vload_nxv64i8330 ; CHECK: liveins: $x10331 ; CHECK-NEXT: {{ $}}332 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10333 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 64 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 64 x s8>) from %ir.pa)334 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 64 x s8>)335 ; CHECK-NEXT: PseudoRET implicit $v8m8336 %0:_(p0) = COPY $x10337 %1:_(<vscale x 64 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 64 x s8>) from %ir.pa)338 $v8m8 = COPY %1(<vscale x 64 x s8>)339 PseudoRET implicit $v8m8340 341...342---343name: vload_nxv1i16344body: |345 bb.1 (%ir-block.0):346 liveins: $x10347 348 ; CHECK-LABEL: name: vload_nxv1i16349 ; CHECK: liveins: $x10350 ; CHECK-NEXT: {{ $}}351 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10352 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s16>) from %ir.pa)353 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s16>)354 ; CHECK-NEXT: PseudoRET implicit $v8355 %0:_(p0) = COPY $x10356 %1:_(<vscale x 1 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s16>) from %ir.pa)357 $v8 = COPY %1(<vscale x 1 x s16>)358 PseudoRET implicit $v8359 360...361---362name: vload_nxv2i16363body: |364 bb.1 (%ir-block.0):365 liveins: $x10366 367 ; CHECK-LABEL: name: vload_nxv2i16368 ; CHECK: liveins: $x10369 ; CHECK-NEXT: {{ $}}370 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10371 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s16>) from %ir.pa)372 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s16>)373 ; CHECK-NEXT: PseudoRET implicit $v8374 %0:_(p0) = COPY $x10375 %1:_(<vscale x 2 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s16>) from %ir.pa)376 $v8 = COPY %1(<vscale x 2 x s16>)377 PseudoRET implicit $v8378 379...380---381name: vload_nxv4i16382body: |383 bb.1 (%ir-block.0):384 liveins: $x10385 386 ; CHECK-LABEL: name: vload_nxv4i16387 ; CHECK: liveins: $x10388 ; CHECK-NEXT: {{ $}}389 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10390 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)391 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)392 ; CHECK-NEXT: PseudoRET implicit $v8393 %0:_(p0) = COPY $x10394 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)395 $v8 = COPY %1(<vscale x 4 x s16>)396 PseudoRET implicit $v8397 398...399---400name: vload_nxv8i16401body: |402 bb.1 (%ir-block.0):403 liveins: $x10404 405 ; CHECK-LABEL: name: vload_nxv8i16406 ; CHECK: liveins: $x10407 ; CHECK-NEXT: {{ $}}408 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10409 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s16>) from %ir.pa)410 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 8 x s16>)411 ; CHECK-NEXT: PseudoRET implicit $v8m2412 %0:_(p0) = COPY $x10413 %1:_(<vscale x 8 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s16>) from %ir.pa)414 $v8m2 = COPY %1(<vscale x 8 x s16>)415 PseudoRET implicit $v8m2416 417...418---419name: vload_nxv16i16420body: |421 bb.1 (%ir-block.0):422 liveins: $x10423 424 ; CHECK-LABEL: name: vload_nxv16i16425 ; CHECK: liveins: $x10426 ; CHECK-NEXT: {{ $}}427 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10428 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s16>) from %ir.pa)429 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x s16>)430 ; CHECK-NEXT: PseudoRET implicit $v8m4431 %0:_(p0) = COPY $x10432 %1:_(<vscale x 16 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s16>) from %ir.pa)433 $v8m4 = COPY %1(<vscale x 16 x s16>)434 PseudoRET implicit $v8m4435 436...437---438name: vload_nxv32i16439body: |440 bb.1 (%ir-block.0):441 liveins: $x10442 443 ; CHECK-LABEL: name: vload_nxv32i16444 ; CHECK: liveins: $x10445 ; CHECK-NEXT: {{ $}}446 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10447 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 32 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s16>) from %ir.pa)448 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 32 x s16>)449 ; CHECK-NEXT: PseudoRET implicit $v8m8450 %0:_(p0) = COPY $x10451 %1:_(<vscale x 32 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s16>) from %ir.pa)452 $v8m8 = COPY %1(<vscale x 32 x s16>)453 PseudoRET implicit $v8m8454 455...456---457name: vload_nxv1i32458body: |459 bb.1 (%ir-block.0):460 liveins: $x10461 462 ; CHECK-LABEL: name: vload_nxv1i32463 ; CHECK: liveins: $x10464 ; CHECK-NEXT: {{ $}}465 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10466 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s32>) from %ir.pa)467 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s32>)468 ; CHECK-NEXT: PseudoRET implicit $v8469 %0:_(p0) = COPY $x10470 %1:_(<vscale x 1 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s32>) from %ir.pa)471 $v8 = COPY %1(<vscale x 1 x s32>)472 PseudoRET implicit $v8473 474...475---476name: vload_nxv2i32477body: |478 bb.1 (%ir-block.0):479 liveins: $x10480 481 ; CHECK-LABEL: name: vload_nxv2i32482 ; CHECK: liveins: $x10483 ; CHECK-NEXT: {{ $}}484 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10485 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)486 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)487 ; CHECK-NEXT: PseudoRET implicit $v8488 %0:_(p0) = COPY $x10489 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)490 $v8 = COPY %1(<vscale x 2 x s32>)491 PseudoRET implicit $v8492 493...494---495name: vload_nxv4i32496body: |497 bb.1 (%ir-block.0):498 liveins: $x10499 500 ; CHECK-LABEL: name: vload_nxv4i32501 ; CHECK: liveins: $x10502 ; CHECK-NEXT: {{ $}}503 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10504 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s32>) from %ir.pa)505 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 4 x s32>)506 ; CHECK-NEXT: PseudoRET implicit $v8m2507 %0:_(p0) = COPY $x10508 %1:_(<vscale x 4 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s32>) from %ir.pa)509 $v8m2 = COPY %1(<vscale x 4 x s32>)510 PseudoRET implicit $v8m2511 512...513---514name: vload_nxv8i32515body: |516 bb.1 (%ir-block.0):517 liveins: $x10518 519 ; CHECK-LABEL: name: vload_nxv8i32520 ; CHECK: liveins: $x10521 ; CHECK-NEXT: {{ $}}522 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10523 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s32>) from %ir.pa)524 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x s32>)525 ; CHECK-NEXT: PseudoRET implicit $v8m4526 %0:_(p0) = COPY $x10527 %1:_(<vscale x 8 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s32>) from %ir.pa)528 $v8m4 = COPY %1(<vscale x 8 x s32>)529 PseudoRET implicit $v8m4530 531...532---533name: vload_nxv16i32534body: |535 bb.1 (%ir-block.0):536 liveins: $x10537 538 ; CHECK-LABEL: name: vload_nxv16i32539 ; CHECK: liveins: $x10540 ; CHECK-NEXT: {{ $}}541 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10542 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s32>) from %ir.pa)543 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 16 x s32>)544 ; CHECK-NEXT: PseudoRET implicit $v8m8545 %0:_(p0) = COPY $x10546 %1:_(<vscale x 16 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s32>) from %ir.pa)547 $v8m8 = COPY %1(<vscale x 16 x s32>)548 PseudoRET implicit $v8m8549 550...551---552name: vload_nxv1i64553body: |554 bb.1 (%ir-block.0):555 liveins: $x10556 557 ; CHECK-LABEL: name: vload_nxv1i64558 ; CHECK: liveins: $x10559 ; CHECK-NEXT: {{ $}}560 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10561 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s64>) from %ir.pa)562 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s64>)563 ; CHECK-NEXT: PseudoRET implicit $v8564 %0:_(p0) = COPY $x10565 %1:_(<vscale x 1 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s64>) from %ir.pa)566 $v8 = COPY %1(<vscale x 1 x s64>)567 PseudoRET implicit $v8568 569...570---571name: vload_nxv2i64572body: |573 bb.1 (%ir-block.0):574 liveins: $x10575 576 ; CHECK-LABEL: name: vload_nxv2i64577 ; CHECK: liveins: $x10578 ; CHECK-NEXT: {{ $}}579 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10580 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)581 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)582 ; CHECK-NEXT: PseudoRET implicit $v8m2583 %0:_(p0) = COPY $x10584 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)585 $v8m2 = COPY %1(<vscale x 2 x s64>)586 PseudoRET implicit $v8m2587 588...589---590name: vload_nxv4i64591body: |592 bb.1 (%ir-block.0):593 liveins: $x10594 595 ; CHECK-LABEL: name: vload_nxv4i64596 ; CHECK: liveins: $x10597 ; CHECK-NEXT: {{ $}}598 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10599 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s64>) from %ir.pa)600 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 4 x s64>)601 ; CHECK-NEXT: PseudoRET implicit $v8m4602 %0:_(p0) = COPY $x10603 %1:_(<vscale x 4 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s64>) from %ir.pa)604 $v8m4 = COPY %1(<vscale x 4 x s64>)605 PseudoRET implicit $v8m4606 607...608---609name: vload_nxv8i64610body: |611 bb.1 (%ir-block.0):612 liveins: $x10613 614 ; CHECK-LABEL: name: vload_nxv8i64615 ; CHECK: liveins: $x10616 ; CHECK-NEXT: {{ $}}617 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10618 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s64>) from %ir.pa)619 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 8 x s64>)620 ; CHECK-NEXT: PseudoRET implicit $v8m8621 %0:_(p0) = COPY $x10622 %1:_(<vscale x 8 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s64>) from %ir.pa)623 $v8m8 = COPY %1(<vscale x 8 x s64>)624 PseudoRET implicit $v8m8625 626...627---628name: vload_nxv16i8_align1629body: |630 bb.1 (%ir-block.0):631 liveins: $x10632 633 ; CHECK-LABEL: name: vload_nxv16i8_align1634 ; CHECK: liveins: $x10635 ; CHECK-NEXT: {{ $}}636 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10637 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)638 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)639 ; CHECK-NEXT: PseudoRET implicit $v8m2640 %0:_(p0) = COPY $x10641 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)642 $v8m2 = COPY %1(<vscale x 16 x s8>)643 PseudoRET implicit $v8m2644 645...646---647name: vload_nxv16i8_align2648body: |649 bb.1 (%ir-block.0):650 liveins: $x10651 652 ; CHECK-LABEL: name: vload_nxv16i8_align2653 ; CHECK: liveins: $x10654 ; CHECK-NEXT: {{ $}}655 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10656 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)657 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)658 ; CHECK-NEXT: PseudoRET implicit $v8m2659 %0:_(p0) = COPY $x10660 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)661 $v8m2 = COPY %1(<vscale x 16 x s8>)662 PseudoRET implicit $v8m2663 664...665---666name: vload_nxv16i8_align16667body: |668 bb.1 (%ir-block.0):669 liveins: $x10670 671 ; CHECK-LABEL: name: vload_nxv16i8_align16672 ; CHECK: liveins: $x10673 ; CHECK-NEXT: {{ $}}674 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10675 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)676 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)677 ; CHECK-NEXT: PseudoRET implicit $v8m2678 %0:_(p0) = COPY $x10679 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)680 $v8m2 = COPY %1(<vscale x 16 x s8>)681 PseudoRET implicit $v8m2682 683...684---685name: vload_nxv16i8_align64686body: |687 bb.1 (%ir-block.0):688 liveins: $x10689 690 ; CHECK-LABEL: name: vload_nxv16i8_align64691 ; CHECK: liveins: $x10692 ; CHECK-NEXT: {{ $}}693 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10694 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)695 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)696 ; CHECK-NEXT: PseudoRET implicit $v8m2697 %0:_(p0) = COPY $x10698 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)699 $v8m2 = COPY %1(<vscale x 16 x s8>)700 PseudoRET implicit $v8m2701 702...703---704name: vload_nxv4i16_align1705body: |706 bb.1 (%ir-block.0):707 liveins: $x10708 709 ; CHECK-LABEL: name: vload_nxv4i16_align1710 ; CHECK: liveins: $x10711 ; CHECK-NEXT: {{ $}}712 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10713 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 1)714 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 4 x s16>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)715 ; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 4 x s16>)716 ; CHECK-NEXT: PseudoRET implicit $v8717 %0:_(p0) = COPY $x10718 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 1)719 $v8 = COPY %1(<vscale x 4 x s16>)720 PseudoRET implicit $v8721 722...723---724name: vload_nxv4i16_align2725body: |726 bb.1 (%ir-block.0):727 liveins: $x10728 729 ; CHECK-LABEL: name: vload_nxv4i16_align2730 ; CHECK: liveins: $x10731 ; CHECK-NEXT: {{ $}}732 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10733 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)734 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)735 ; CHECK-NEXT: PseudoRET implicit $v8736 %0:_(p0) = COPY $x10737 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)738 $v8 = COPY %1(<vscale x 4 x s16>)739 PseudoRET implicit $v8740 741...742---743name: vload_nxv4i16_align4744body: |745 bb.1 (%ir-block.0):746 liveins: $x10747 748 ; CHECK-LABEL: name: vload_nxv4i16_align4749 ; CHECK: liveins: $x10750 ; CHECK-NEXT: {{ $}}751 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10752 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)753 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)754 ; CHECK-NEXT: PseudoRET implicit $v8755 %0:_(p0) = COPY $x10756 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)757 $v8 = COPY %1(<vscale x 4 x s16>)758 PseudoRET implicit $v8759 760...761---762name: vload_nxv4i16_align8763body: |764 bb.1 (%ir-block.0):765 liveins: $x10766 767 ; CHECK-LABEL: name: vload_nxv4i16_align8768 ; CHECK: liveins: $x10769 ; CHECK-NEXT: {{ $}}770 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10771 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)772 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)773 ; CHECK-NEXT: PseudoRET implicit $v8774 %0:_(p0) = COPY $x10775 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)776 $v8 = COPY %1(<vscale x 4 x s16>)777 PseudoRET implicit $v8778 779...780---781name: vload_nxv4i16_align16782body: |783 bb.1 (%ir-block.0):784 liveins: $x10785 786 ; CHECK-LABEL: name: vload_nxv4i16_align16787 ; CHECK: liveins: $x10788 ; CHECK-NEXT: {{ $}}789 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10790 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)791 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)792 ; CHECK-NEXT: PseudoRET implicit $v8793 %0:_(p0) = COPY $x10794 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)795 $v8 = COPY %1(<vscale x 4 x s16>)796 PseudoRET implicit $v8797 798...799---800name: vload_nxv2i32_align2801body: |802 bb.1 (%ir-block.0):803 liveins: $x10804 805 ; CHECK-LABEL: name: vload_nxv2i32_align2806 ; CHECK: liveins: $x10807 ; CHECK-NEXT: {{ $}}808 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10809 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 2)810 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s32>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)811 ; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 2 x s32>)812 ; CHECK-NEXT: PseudoRET implicit $v8813 %0:_(p0) = COPY $x10814 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 2)815 $v8 = COPY %1(<vscale x 2 x s32>)816 PseudoRET implicit $v8817 818...819---820name: vload_nxv2i32_align4821body: |822 bb.1 (%ir-block.0):823 liveins: $x10824 825 ; CHECK-LABEL: name: vload_nxv2i32_align4826 ; CHECK: liveins: $x10827 ; CHECK-NEXT: {{ $}}828 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10829 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)830 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)831 ; CHECK-NEXT: PseudoRET implicit $v8832 %0:_(p0) = COPY $x10833 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)834 $v8 = COPY %1(<vscale x 2 x s32>)835 PseudoRET implicit $v8836 837...838---839name: vload_nxv2i32_align8840body: |841 bb.1 (%ir-block.0):842 liveins: $x10843 844 ; CHECK-LABEL: name: vload_nxv2i32_align8845 ; CHECK: liveins: $x10846 ; CHECK-NEXT: {{ $}}847 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10848 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)849 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)850 ; CHECK-NEXT: PseudoRET implicit $v8851 %0:_(p0) = COPY $x10852 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)853 $v8 = COPY %1(<vscale x 2 x s32>)854 PseudoRET implicit $v8855 856...857---858name: vload_nxv2i32_align16859body: |860 bb.1 (%ir-block.0):861 liveins: $x10862 863 ; CHECK-LABEL: name: vload_nxv2i32_align16864 ; CHECK: liveins: $x10865 ; CHECK-NEXT: {{ $}}866 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10867 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)868 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)869 ; CHECK-NEXT: PseudoRET implicit $v8870 %0:_(p0) = COPY $x10871 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)872 $v8 = COPY %1(<vscale x 2 x s32>)873 PseudoRET implicit $v8874 875...876---877name: vload_nxv2i32_align256878body: |879 bb.1 (%ir-block.0):880 liveins: $x10881 882 ; CHECK-LABEL: name: vload_nxv2i32_align256883 ; CHECK: liveins: $x10884 ; CHECK-NEXT: {{ $}}885 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10886 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)887 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)888 ; CHECK-NEXT: PseudoRET implicit $v8889 %0:_(p0) = COPY $x10890 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)891 $v8 = COPY %1(<vscale x 2 x s32>)892 PseudoRET implicit $v8893 894...895---896name: vload_nxv2i64_align4897body: |898 bb.1 (%ir-block.0):899 liveins: $x10900 901 ; CHECK-LABEL: name: vload_nxv2i64_align4902 ; CHECK: liveins: $x10903 ; CHECK-NEXT: {{ $}}904 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10905 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 4)906 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<vscale x 2 x s64>) = G_BITCAST [[LOAD]](<vscale x 16 x s8>)907 ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]](<vscale x 2 x s64>)908 ; CHECK-NEXT: PseudoRET implicit $v8m2909 %0:_(p0) = COPY $x10910 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 4)911 $v8m2 = COPY %1(<vscale x 2 x s64>)912 PseudoRET implicit $v8m2913 914...915---916name: vload_nxv2i64_align8917body: |918 bb.1 (%ir-block.0):919 liveins: $x10920 921 ; CHECK-LABEL: name: vload_nxv2i64_align8922 ; CHECK: liveins: $x10923 ; CHECK-NEXT: {{ $}}924 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10925 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)926 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)927 ; CHECK-NEXT: PseudoRET implicit $v8m2928 %0:_(p0) = COPY $x10929 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)930 $v8m2 = COPY %1(<vscale x 2 x s64>)931 PseudoRET implicit $v8m2932 933...934---935name: vload_nxv2i64_align16936body: |937 bb.1 (%ir-block.0):938 liveins: $x10939 940 ; CHECK-LABEL: name: vload_nxv2i64_align16941 ; CHECK: liveins: $x10942 ; CHECK-NEXT: {{ $}}943 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10944 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)945 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)946 ; CHECK-NEXT: PseudoRET implicit $v8m2947 %0:_(p0) = COPY $x10948 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)949 $v8m2 = COPY %1(<vscale x 2 x s64>)950 PseudoRET implicit $v8m2951 952...953---954name: vload_nxv2i64_align32955body: |956 bb.1 (%ir-block.0):957 liveins: $x10958 959 ; CHECK-LABEL: name: vload_nxv2i64_align32960 ; CHECK: liveins: $x10961 ; CHECK-NEXT: {{ $}}962 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10963 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)964 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)965 ; CHECK-NEXT: PseudoRET implicit $v8m2966 %0:_(p0) = COPY $x10967 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)968 $v8m2 = COPY %1(<vscale x 2 x s64>)969 PseudoRET implicit $v8m2970 971...972