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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s3# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s4---5name: test_nxv1i86body: |7 bb.0.entry:8 9 ; CHECK-LABEL: name: test_nxv1i810 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v811 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s8>) = COPY $v912 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s8>) = G_OR [[COPY]], [[COPY1]]13 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s8>)14 ; CHECK-NEXT: PseudoRET implicit $v815 %0:_(<vscale x 1 x s8>) = COPY $v816 %1:_(<vscale x 1 x s8>) = COPY $v917 %2:_(<vscale x 1 x s8>) = G_OR %0, %118 $v8 = COPY %2(<vscale x 1 x s8>)19 PseudoRET implicit $v820 21...22---23name: test_nxv2i824body: |25 bb.0.entry:26 27 ; CHECK-LABEL: name: test_nxv2i828 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v829 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s8>) = COPY $v930 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s8>) = G_OR [[COPY]], [[COPY1]]31 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 2 x s8>)32 ; CHECK-NEXT: PseudoRET implicit $v833 %0:_(<vscale x 2 x s8>) = COPY $v834 %1:_(<vscale x 2 x s8>) = COPY $v935 %2:_(<vscale x 2 x s8>) = G_OR %0, %136 $v8 = COPY %2(<vscale x 2 x s8>)37 PseudoRET implicit $v838 39...40---41name: test_nxv4i842body: |43 bb.0.entry:44 45 ; CHECK-LABEL: name: test_nxv4i846 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v847 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s8>) = COPY $v948 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s8>) = G_OR [[COPY]], [[COPY1]]49 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 4 x s8>)50 ; CHECK-NEXT: PseudoRET implicit $v851 %0:_(<vscale x 4 x s8>) = COPY $v852 %1:_(<vscale x 4 x s8>) = COPY $v953 %2:_(<vscale x 4 x s8>) = G_OR %0, %154 $v8 = COPY %2(<vscale x 4 x s8>)55 PseudoRET implicit $v856 57...58---59name: test_nxv8i860body: |61 bb.0.entry:62 63 ; CHECK-LABEL: name: test_nxv8i864 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v865 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s8>) = COPY $v966 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s8>) = G_OR [[COPY]], [[COPY1]]67 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 8 x s8>)68 ; CHECK-NEXT: PseudoRET implicit $v869 %0:_(<vscale x 8 x s8>) = COPY $v870 %1:_(<vscale x 8 x s8>) = COPY $v971 %2:_(<vscale x 8 x s8>) = G_OR %0, %172 $v8 = COPY %2(<vscale x 8 x s8>)73 PseudoRET implicit $v874 75...76---77name: test_nxv16i878body: |79 bb.0.entry:80 81 ; CHECK-LABEL: name: test_nxv16i882 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v8m283 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s8>) = COPY $v10m284 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 16 x s8>) = G_OR [[COPY]], [[COPY1]]85 ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 16 x s8>)86 ; CHECK-NEXT: PseudoRET implicit $v8m287 %0:_(<vscale x 16 x s8>) = COPY $v8m288 %1:_(<vscale x 16 x s8>) = COPY $v10m289 %2:_(<vscale x 16 x s8>) = G_OR %0, %190 $v8m2 = COPY %2(<vscale x 16 x s8>)91 PseudoRET implicit $v8m292 93...94---95name: test_nxv32i896body: |97 bb.0.entry:98 99 ; CHECK-LABEL: name: test_nxv32i8100 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v8m4101 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s8>) = COPY $v12m4102 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 32 x s8>) = G_OR [[COPY]], [[COPY1]]103 ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 32 x s8>)104 ; CHECK-NEXT: PseudoRET implicit $v8m4105 %0:_(<vscale x 32 x s8>) = COPY $v8m4106 %1:_(<vscale x 32 x s8>) = COPY $v12m4107 %2:_(<vscale x 32 x s8>) = G_OR %0, %1108 $v8m4 = COPY %2(<vscale x 32 x s8>)109 PseudoRET implicit $v8m4110 111...112---113name: test_nxv64i8114body: |115 bb.0.entry:116 117 ; CHECK-LABEL: name: test_nxv64i8118 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v8m8119 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 64 x s8>) = COPY $v16m8120 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 64 x s8>) = G_OR [[COPY]], [[COPY1]]121 ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 64 x s8>)122 ; CHECK-NEXT: PseudoRET implicit $v8m8123 %0:_(<vscale x 64 x s8>) = COPY $v8m8124 %1:_(<vscale x 64 x s8>) = COPY $v16m8125 %2:_(<vscale x 64 x s8>) = G_OR %0, %1126 $v8m8 = COPY %2(<vscale x 64 x s8>)127 PseudoRET implicit $v8m8128 129...130---131name: test_nxv1i16132body: |133 bb.0.entry:134 135 ; CHECK-LABEL: name: test_nxv1i16136 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v8137 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s16>) = COPY $v9138 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s16>) = G_OR [[COPY]], [[COPY1]]139 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s16>)140 ; CHECK-NEXT: PseudoRET implicit $v8141 %0:_(<vscale x 1 x s16>) = COPY $v8142 %1:_(<vscale x 1 x s16>) = COPY $v9143 %2:_(<vscale x 1 x s16>) = G_OR %0, %1144 $v8 = COPY %2(<vscale x 1 x s16>)145 PseudoRET implicit $v8146 147...148---149name: test_nxv2i16150body: |151 bb.0.entry:152 153 ; CHECK-LABEL: name: test_nxv2i16154 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v8155 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s16>) = COPY $v9156 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s16>) = G_OR [[COPY]], [[COPY1]]157 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 2 x s16>)158 ; CHECK-NEXT: PseudoRET implicit $v8159 %0:_(<vscale x 2 x s16>) = COPY $v8160 %1:_(<vscale x 2 x s16>) = COPY $v9161 %2:_(<vscale x 2 x s16>) = G_OR %0, %1162 $v8 = COPY %2(<vscale x 2 x s16>)163 PseudoRET implicit $v8164 165...166---167name: test_nxv4i16168body: |169 bb.0.entry:170 171 ; CHECK-LABEL: name: test_nxv4i16172 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v8173 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s16>) = COPY $v9174 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s16>) = G_OR [[COPY]], [[COPY1]]175 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 4 x s16>)176 ; CHECK-NEXT: PseudoRET implicit $v8177 %0:_(<vscale x 4 x s16>) = COPY $v8178 %1:_(<vscale x 4 x s16>) = COPY $v9179 %2:_(<vscale x 4 x s16>) = G_OR %0, %1180 $v8 = COPY %2(<vscale x 4 x s16>)181 PseudoRET implicit $v8182 183...184---185name: test_nxv8i16186body: |187 bb.0.entry:188 189 ; CHECK-LABEL: name: test_nxv8i16190 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v8m2191 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s16>) = COPY $v10m2192 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s16>) = G_OR [[COPY]], [[COPY1]]193 ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 8 x s16>)194 ; CHECK-NEXT: PseudoRET implicit $v8m2195 %0:_(<vscale x 8 x s16>) = COPY $v8m2196 %1:_(<vscale x 8 x s16>) = COPY $v10m2197 %2:_(<vscale x 8 x s16>) = G_OR %0, %1198 $v8m2 = COPY %2(<vscale x 8 x s16>)199 PseudoRET implicit $v8m2200 201...202---203name: test_nxv16i16204body: |205 bb.0.entry:206 207 ; CHECK-LABEL: name: test_nxv16i16208 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v8m4209 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s16>) = COPY $v12m4210 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 16 x s16>) = G_OR [[COPY]], [[COPY1]]211 ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 16 x s16>)212 ; CHECK-NEXT: PseudoRET implicit $v8m4213 %0:_(<vscale x 16 x s16>) = COPY $v8m4214 %1:_(<vscale x 16 x s16>) = COPY $v12m4215 %2:_(<vscale x 16 x s16>) = G_OR %0, %1216 $v8m4 = COPY %2(<vscale x 16 x s16>)217 PseudoRET implicit $v8m4218 219...220---221name: test_nxv32i16222body: |223 bb.0.entry:224 225 ; CHECK-LABEL: name: test_nxv32i16226 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v8m8227 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 32 x s16>) = COPY $v16m8228 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 32 x s16>) = G_OR [[COPY]], [[COPY1]]229 ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 32 x s16>)230 ; CHECK-NEXT: PseudoRET implicit $v8m8231 %0:_(<vscale x 32 x s16>) = COPY $v8m8232 %1:_(<vscale x 32 x s16>) = COPY $v16m8233 %2:_(<vscale x 32 x s16>) = G_OR %0, %1234 $v8m8 = COPY %2(<vscale x 32 x s16>)235 PseudoRET implicit $v8m8236 237...238---239name: test_nxv1i32240body: |241 bb.0.entry:242 243 ; CHECK-LABEL: name: test_nxv1i32244 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v8245 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s32>) = COPY $v9246 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s32>) = G_OR [[COPY]], [[COPY1]]247 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s32>)248 ; CHECK-NEXT: PseudoRET implicit $v8249 %0:_(<vscale x 1 x s32>) = COPY $v8250 %1:_(<vscale x 1 x s32>) = COPY $v9251 %2:_(<vscale x 1 x s32>) = G_OR %0, %1252 $v8 = COPY %2(<vscale x 1 x s32>)253 PseudoRET implicit $v8254 255...256---257name: test_nxv2i32258body: |259 bb.0.entry:260 261 ; CHECK-LABEL: name: test_nxv2i32262 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v8263 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s32>) = COPY $v9264 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s32>) = G_OR [[COPY]], [[COPY1]]265 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 2 x s32>)266 ; CHECK-NEXT: PseudoRET implicit $v8267 %0:_(<vscale x 2 x s32>) = COPY $v8268 %1:_(<vscale x 2 x s32>) = COPY $v9269 %2:_(<vscale x 2 x s32>) = G_OR %0, %1270 $v8 = COPY %2(<vscale x 2 x s32>)271 PseudoRET implicit $v8272 273...274---275name: test_nxv4i32276body: |277 bb.0.entry:278 279 ; CHECK-LABEL: name: test_nxv4i32280 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v8m2281 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s32>) = COPY $v10m2282 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s32>) = G_OR [[COPY]], [[COPY1]]283 ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 4 x s32>)284 ; CHECK-NEXT: PseudoRET implicit $v8m2285 %0:_(<vscale x 4 x s32>) = COPY $v8m2286 %1:_(<vscale x 4 x s32>) = COPY $v10m2287 %2:_(<vscale x 4 x s32>) = G_OR %0, %1288 $v8m2 = COPY %2(<vscale x 4 x s32>)289 PseudoRET implicit $v8m2290 291...292---293name: test_nxv8i32294body: |295 bb.0.entry:296 297 ; CHECK-LABEL: name: test_nxv8i32298 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v8m4299 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s32>) = COPY $v12m4300 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s32>) = G_OR [[COPY]], [[COPY1]]301 ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 8 x s32>)302 ; CHECK-NEXT: PseudoRET implicit $v8m4303 %0:_(<vscale x 8 x s32>) = COPY $v8m4304 %1:_(<vscale x 8 x s32>) = COPY $v12m4305 %2:_(<vscale x 8 x s32>) = G_OR %0, %1306 $v8m4 = COPY %2(<vscale x 8 x s32>)307 PseudoRET implicit $v8m4308 309...310---311name: test_nxv16i32312body: |313 bb.0.entry:314 315 ; CHECK-LABEL: name: test_nxv16i32316 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v8m8317 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x s32>) = COPY $v16m8318 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 16 x s32>) = G_OR [[COPY]], [[COPY1]]319 ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 16 x s32>)320 ; CHECK-NEXT: PseudoRET implicit $v8m8321 %0:_(<vscale x 16 x s32>) = COPY $v8m8322 %1:_(<vscale x 16 x s32>) = COPY $v16m8323 %2:_(<vscale x 16 x s32>) = G_OR %0, %1324 $v8m8 = COPY %2(<vscale x 16 x s32>)325 PseudoRET implicit $v8m8326 327...328---329name: test_nxv1i64330body: |331 bb.0.entry:332 333 ; CHECK-LABEL: name: test_nxv1i64334 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v8335 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x s64>) = COPY $v9336 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 1 x s64>) = G_OR [[COPY]], [[COPY1]]337 ; CHECK-NEXT: $v8 = COPY [[OR]](<vscale x 1 x s64>)338 ; CHECK-NEXT: PseudoRET implicit $v8339 %0:_(<vscale x 1 x s64>) = COPY $v8340 %1:_(<vscale x 1 x s64>) = COPY $v9341 %2:_(<vscale x 1 x s64>) = G_OR %0, %1342 $v8 = COPY %2(<vscale x 1 x s64>)343 PseudoRET implicit $v8344 345...346---347name: test_nxv2i64348body: |349 bb.0.entry:350 351 ; CHECK-LABEL: name: test_nxv2i64352 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v8m2353 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x s64>) = COPY $v10m2354 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 2 x s64>) = G_OR [[COPY]], [[COPY1]]355 ; CHECK-NEXT: $v8m2 = COPY [[OR]](<vscale x 2 x s64>)356 ; CHECK-NEXT: PseudoRET implicit $v8m2357 %0:_(<vscale x 2 x s64>) = COPY $v8m2358 %1:_(<vscale x 2 x s64>) = COPY $v10m2359 %2:_(<vscale x 2 x s64>) = G_OR %0, %1360 $v8m2 = COPY %2(<vscale x 2 x s64>)361 PseudoRET implicit $v8m2362 363...364---365name: test_nxv4i64366body: |367 bb.0.entry:368 369 ; CHECK-LABEL: name: test_nxv4i64370 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v8m4371 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 4 x s64>) = COPY $v12m4372 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 4 x s64>) = G_OR [[COPY]], [[COPY1]]373 ; CHECK-NEXT: $v8m4 = COPY [[OR]](<vscale x 4 x s64>)374 ; CHECK-NEXT: PseudoRET implicit $v8m4375 %0:_(<vscale x 4 x s64>) = COPY $v8m4376 %1:_(<vscale x 4 x s64>) = COPY $v12m4377 %2:_(<vscale x 4 x s64>) = G_OR %0, %1378 $v8m4 = COPY %2(<vscale x 4 x s64>)379 PseudoRET implicit $v8m4380 381...382---383name: test_nxv8i64384body: |385 bb.0.entry:386 387 ; CHECK-LABEL: name: test_nxv8i64388 ; CHECK: [[COPY:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v8m8389 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x s64>) = COPY $v16m8390 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<vscale x 8 x s64>) = G_OR [[COPY]], [[COPY1]]391 ; CHECK-NEXT: $v8m8 = COPY [[OR]](<vscale x 8 x s64>)392 ; CHECK-NEXT: PseudoRET implicit $v8m8393 %0:_(<vscale x 8 x s64>) = COPY $v8m8394 %1:_(<vscale x 8 x s64>) = COPY $v16m8395 %2:_(<vscale x 8 x s64>) = G_OR %0, %1396 $v8m8 = COPY %2(<vscale x 8 x s64>)397 PseudoRET implicit $v8m8398 399...400