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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \3# RUN: -simplify-mir -verify-machineinstrs %s \4# RUN: -o - | FileCheck -check-prefix=RV32I %s5 6---7name: load_i88legalized: true9tracksRegLiveness: true10body: |11 bb.0:12 liveins: $x1013 14 ; RV32I-LABEL: name: load_i815 ; RV32I: liveins: $x1016 ; RV32I-NEXT: {{ $}}17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x1018 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8))19 ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)20 ; RV32I-NEXT: PseudoRET implicit $x1021 %0:_(p0) = COPY $x1022 %3:_(s32) = G_LOAD %0(p0) :: (load (s8))23 $x10 = COPY %3(s32)24 PseudoRET implicit $x1025 26...27---28name: load_i1629legalized: true30tracksRegLiveness: true31body: |32 bb.0:33 liveins: $x1034 35 ; RV32I-LABEL: name: load_i1636 ; RV32I: liveins: $x1037 ; RV32I-NEXT: {{ $}}38 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x1039 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16))40 ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)41 ; RV32I-NEXT: PseudoRET implicit $x1042 %0:_(p0) = COPY $x1043 %3:_(s32) = G_LOAD %0(p0) :: (load (s16))44 $x10 = COPY %3(s32)45 PseudoRET implicit $x1046 47...48---49name: load_i3250legalized: true51tracksRegLiveness: true52body: |53 bb.0:54 liveins: $x1055 56 ; RV32I-LABEL: name: load_i3257 ; RV32I: liveins: $x1058 ; RV32I-NEXT: {{ $}}59 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x1060 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))61 ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)62 ; RV32I-NEXT: PseudoRET implicit $x1063 %0:_(p0) = COPY $x1064 %3:_(s32) = G_LOAD %0(p0) :: (load (s32))65 $x10 = COPY %3(s32)66 PseudoRET implicit $x1067 68...69---70name: load_ptr71legalized: true72tracksRegLiveness: true73body: |74 bb.0:75 liveins: $x1076 77 ; RV32I-LABEL: name: load_ptr78 ; RV32I: liveins: $x1079 ; RV32I-NEXT: {{ $}}80 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x1081 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0))82 ; RV32I-NEXT: $x10 = COPY [[LOAD]](p0)83 ; RV32I-NEXT: PseudoRET implicit $x1084 %0:_(p0) = COPY $x1085 %3:_(p0) = G_LOAD %0(p0) :: (load (p0))86 $x10 = COPY %3(p0)87 PseudoRET implicit $x1088 89...90---91name: zextload_i892legalized: true93tracksRegLiveness: true94body: |95 bb.0:96 liveins: $x1097 98 ; RV32I-LABEL: name: zextload_i899 ; RV32I: liveins: $x10100 ; RV32I-NEXT: {{ $}}101 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10102 ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))103 ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)104 ; RV32I-NEXT: PseudoRET implicit $x10105 %0:_(p0) = COPY $x10106 %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))107 $x10 = COPY %1(s32)108 PseudoRET implicit $x10109 110...111---112name: zextload_i16113legalized: true114tracksRegLiveness: true115body: |116 bb.0:117 liveins: $x10118 119 ; RV32I-LABEL: name: zextload_i16120 ; RV32I: liveins: $x10121 ; RV32I-NEXT: {{ $}}122 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10123 ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))124 ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)125 ; RV32I-NEXT: PseudoRET implicit $x10126 %0:_(p0) = COPY $x10127 %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))128 $x10 = COPY %1(s32)129 PseudoRET implicit $x10130 131...132---133name: sextload_i8134legalized: true135tracksRegLiveness: true136body: |137 bb.0:138 liveins: $x10139 140 ; RV32I-LABEL: name: sextload_i8141 ; RV32I: liveins: $x10142 ; RV32I-NEXT: {{ $}}143 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10144 ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))145 ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32)146 ; RV32I-NEXT: PseudoRET implicit $x10147 %0:_(p0) = COPY $x10148 %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))149 $x10 = COPY %1(s32)150 PseudoRET implicit $x10151 152...153---154name: sextload_i16155legalized: true156tracksRegLiveness: true157body: |158 bb.0:159 liveins: $x10160 161 ; RV32I-LABEL: name: sextload_i16162 ; RV32I: liveins: $x10163 ; RV32I-NEXT: {{ $}}164 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10165 ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))166 ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32)167 ; RV32I-NEXT: PseudoRET implicit $x10168 %0:_(p0) = COPY $x10169 %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))170 $x10 = COPY %1(s32)171 PseudoRET implicit $x10172 173...174