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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \3# RUN: -simplify-mir -verify-machineinstrs %s \4# RUN: -o - | FileCheck %s5# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \6# RUN: -simplify-mir -verify-machineinstrs %s \7# RUN: -o - | FileCheck %s8---9name: vadd_vv_nxv1i810legalized: true11tracksRegLiveness: true12body: |13 bb.0.entry:14 liveins: $v8, $v915 16 ; CHECK-LABEL: name: vadd_vv_nxv1i817 ; CHECK: liveins: $v8, $v918 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v820 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s8>) = COPY $v921 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_ADD [[COPY]], [[COPY1]]22 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s8>)23 ; CHECK-NEXT: PseudoRET implicit $v824 %0:_(<vscale x 1 x s8>) = COPY $v825 %1:_(<vscale x 1 x s8>) = COPY $v926 %2:_(<vscale x 1 x s8>) = G_ADD %0, %127 $v8 = COPY %2(<vscale x 1 x s8>)28 PseudoRET implicit $v829 30...31---32name: vadd_vv_nxv2i833legalized: true34tracksRegLiveness: true35body: |36 bb.0.entry:37 liveins: $v8, $v938 39 ; CHECK-LABEL: name: vadd_vv_nxv2i840 ; CHECK: liveins: $v8, $v941 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v843 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s8>) = COPY $v944 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_ADD [[COPY]], [[COPY1]]45 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s8>)46 ; CHECK-NEXT: PseudoRET implicit $v847 %0:_(<vscale x 2 x s8>) = COPY $v848 %1:_(<vscale x 2 x s8>) = COPY $v949 %2:_(<vscale x 2 x s8>) = G_ADD %0, %150 $v8 = COPY %2(<vscale x 2 x s8>)51 PseudoRET implicit $v852 53...54---55name: vadd_vv_nxv4i856legalized: true57tracksRegLiveness: true58body: |59 bb.0.entry:60 liveins: $v8, $v961 62 ; CHECK-LABEL: name: vadd_vv_nxv4i863 ; CHECK: liveins: $v8, $v964 ; CHECK-NEXT: {{ $}}65 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v866 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s8>) = COPY $v967 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_ADD [[COPY]], [[COPY1]]68 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s8>)69 ; CHECK-NEXT: PseudoRET implicit $v870 %0:_(<vscale x 4 x s8>) = COPY $v871 %1:_(<vscale x 4 x s8>) = COPY $v972 %2:_(<vscale x 4 x s8>) = G_ADD %0, %173 $v8 = COPY %2(<vscale x 4 x s8>)74 PseudoRET implicit $v875 76...77---78name: vadd_vv_nxv8i879legalized: true80tracksRegLiveness: true81body: |82 bb.0.entry:83 liveins: $v8, $v984 85 ; CHECK-LABEL: name: vadd_vv_nxv8i886 ; CHECK: liveins: $v8, $v987 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v889 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s8>) = COPY $v990 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_ADD [[COPY]], [[COPY1]]91 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 8 x s8>)92 ; CHECK-NEXT: PseudoRET implicit $v893 %0:_(<vscale x 8 x s8>) = COPY $v894 %1:_(<vscale x 8 x s8>) = COPY $v995 %2:_(<vscale x 8 x s8>) = G_ADD %0, %196 $v8 = COPY %2(<vscale x 8 x s8>)97 PseudoRET implicit $v898 99...100---101name: vadd_vv_nxv16i8102legalized: true103tracksRegLiveness: true104body: |105 bb.0.entry:106 liveins: $v8m2, $v10m2107 108 ; CHECK-LABEL: name: vadd_vv_nxv16i8109 ; CHECK: liveins: $v8m2, $v10m2110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v8m2112 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s8>) = COPY $v10m2113 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_ADD [[COPY]], [[COPY1]]114 ; CHECK-NEXT: $v8m2 = COPY [[ADD]](<vscale x 16 x s8>)115 ; CHECK-NEXT: PseudoRET implicit $v8m2116 %0:_(<vscale x 16 x s8>) = COPY $v8m2117 %1:_(<vscale x 16 x s8>) = COPY $v10m2118 %2:_(<vscale x 16 x s8>) = G_ADD %0, %1119 $v8m2 = COPY %2(<vscale x 16 x s8>)120 PseudoRET implicit $v8m2121 122...123---124name: vadd_vv_nxv32i8125legalized: true126tracksRegLiveness: true127body: |128 bb.0.entry:129 liveins: $v8m4, $v12m4130 131 ; CHECK-LABEL: name: vadd_vv_nxv32i8132 ; CHECK: liveins: $v8m4, $v12m4133 ; CHECK-NEXT: {{ $}}134 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v8m4135 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s8>) = COPY $v12m4136 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_ADD [[COPY]], [[COPY1]]137 ; CHECK-NEXT: $v8m4 = COPY [[ADD]](<vscale x 32 x s8>)138 ; CHECK-NEXT: PseudoRET implicit $v8m4139 %0:_(<vscale x 32 x s8>) = COPY $v8m4140 %1:_(<vscale x 32 x s8>) = COPY $v12m4141 %2:_(<vscale x 32 x s8>) = G_ADD %0, %1142 $v8m4 = COPY %2(<vscale x 32 x s8>)143 PseudoRET implicit $v8m4144 145...146---147name: vadd_vv_nxv64i8148legalized: true149tracksRegLiveness: true150body: |151 bb.0.entry:152 liveins: $v8m8, $v16m8153 154 ; CHECK-LABEL: name: vadd_vv_nxv64i8155 ; CHECK: liveins: $v8m8, $v16m8156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v8m8158 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 64 x s8>) = COPY $v16m8159 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_ADD [[COPY]], [[COPY1]]160 ; CHECK-NEXT: $v8m8 = COPY [[ADD]](<vscale x 64 x s8>)161 ; CHECK-NEXT: PseudoRET implicit $v8m8162 %0:_(<vscale x 64 x s8>) = COPY $v8m8163 %1:_(<vscale x 64 x s8>) = COPY $v16m8164 %2:_(<vscale x 64 x s8>) = G_ADD %0, %1165 $v8m8 = COPY %2(<vscale x 64 x s8>)166 PseudoRET implicit $v8m8167 168...169---170name: vadd_vv_nxv1i16171legalized: true172tracksRegLiveness: true173body: |174 bb.0.entry:175 liveins: $v8, $v9176 177 ; CHECK-LABEL: name: vadd_vv_nxv1i16178 ; CHECK: liveins: $v8, $v9179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v8181 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s16>) = COPY $v9182 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_ADD [[COPY]], [[COPY1]]183 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s16>)184 ; CHECK-NEXT: PseudoRET implicit $v8185 %0:_(<vscale x 1 x s16>) = COPY $v8186 %1:_(<vscale x 1 x s16>) = COPY $v9187 %2:_(<vscale x 1 x s16>) = G_ADD %0, %1188 $v8 = COPY %2(<vscale x 1 x s16>)189 PseudoRET implicit $v8190 191...192---193name: vadd_vv_nxv2i16194legalized: true195tracksRegLiveness: true196body: |197 bb.0.entry:198 liveins: $v8, $v9199 200 ; CHECK-LABEL: name: vadd_vv_nxv2i16201 ; CHECK: liveins: $v8, $v9202 ; CHECK-NEXT: {{ $}}203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v8204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s16>) = COPY $v9205 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_ADD [[COPY]], [[COPY1]]206 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s16>)207 ; CHECK-NEXT: PseudoRET implicit $v8208 %0:_(<vscale x 2 x s16>) = COPY $v8209 %1:_(<vscale x 2 x s16>) = COPY $v9210 %2:_(<vscale x 2 x s16>) = G_ADD %0, %1211 $v8 = COPY %2(<vscale x 2 x s16>)212 PseudoRET implicit $v8213 214...215---216name: vadd_vv_nxv4i16217legalized: true218tracksRegLiveness: true219body: |220 bb.0.entry:221 liveins: $v8, $v9222 223 ; CHECK-LABEL: name: vadd_vv_nxv4i16224 ; CHECK: liveins: $v8, $v9225 ; CHECK-NEXT: {{ $}}226 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v8227 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s16>) = COPY $v9228 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_ADD [[COPY]], [[COPY1]]229 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 4 x s16>)230 ; CHECK-NEXT: PseudoRET implicit $v8231 %0:_(<vscale x 4 x s16>) = COPY $v8232 %1:_(<vscale x 4 x s16>) = COPY $v9233 %2:_(<vscale x 4 x s16>) = G_ADD %0, %1234 $v8 = COPY %2(<vscale x 4 x s16>)235 PseudoRET implicit $v8236 237...238---239name: vadd_vv_nxv8i16240legalized: true241tracksRegLiveness: true242body: |243 bb.0.entry:244 liveins: $v8m2, $v10m2245 246 ; CHECK-LABEL: name: vadd_vv_nxv8i16247 ; CHECK: liveins: $v8m2, $v10m2248 ; CHECK-NEXT: {{ $}}249 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v8m2250 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s16>) = COPY $v10m2251 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_ADD [[COPY]], [[COPY1]]252 ; CHECK-NEXT: $v8m2 = COPY [[ADD]](<vscale x 8 x s16>)253 ; CHECK-NEXT: PseudoRET implicit $v8m2254 %0:_(<vscale x 8 x s16>) = COPY $v8m2255 %1:_(<vscale x 8 x s16>) = COPY $v10m2256 %2:_(<vscale x 8 x s16>) = G_ADD %0, %1257 $v8m2 = COPY %2(<vscale x 8 x s16>)258 PseudoRET implicit $v8m2259 260...261---262name: vadd_vv_nxv16i16263legalized: true264tracksRegLiveness: true265body: |266 bb.0.entry:267 liveins: $v8m4, $v12m4268 269 ; CHECK-LABEL: name: vadd_vv_nxv16i16270 ; CHECK: liveins: $v8m4, $v12m4271 ; CHECK-NEXT: {{ $}}272 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v8m4273 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s16>) = COPY $v12m4274 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_ADD [[COPY]], [[COPY1]]275 ; CHECK-NEXT: $v8m4 = COPY [[ADD]](<vscale x 16 x s16>)276 ; CHECK-NEXT: PseudoRET implicit $v8m4277 %0:_(<vscale x 16 x s16>) = COPY $v8m4278 %1:_(<vscale x 16 x s16>) = COPY $v12m4279 %2:_(<vscale x 16 x s16>) = G_ADD %0, %1280 $v8m4 = COPY %2(<vscale x 16 x s16>)281 PseudoRET implicit $v8m4282 283...284---285name: vadd_vv_nxv32i16286legalized: true287tracksRegLiveness: true288body: |289 bb.0.entry:290 liveins: $v8m8, $v16m8291 292 ; CHECK-LABEL: name: vadd_vv_nxv32i16293 ; CHECK: liveins: $v8m8, $v16m8294 ; CHECK-NEXT: {{ $}}295 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v8m8296 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 32 x s16>) = COPY $v16m8297 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_ADD [[COPY]], [[COPY1]]298 ; CHECK-NEXT: $v8m8 = COPY [[ADD]](<vscale x 32 x s16>)299 ; CHECK-NEXT: PseudoRET implicit $v8m8300 %0:_(<vscale x 32 x s16>) = COPY $v8m8301 %1:_(<vscale x 32 x s16>) = COPY $v16m8302 %2:_(<vscale x 32 x s16>) = G_ADD %0, %1303 $v8m8 = COPY %2(<vscale x 32 x s16>)304 PseudoRET implicit $v8m8305 306...307---308name: vadd_vv_nxv1i32309legalized: true310tracksRegLiveness: true311body: |312 bb.0.entry:313 liveins: $v8, $v9314 315 ; CHECK-LABEL: name: vadd_vv_nxv1i32316 ; CHECK: liveins: $v8, $v9317 ; CHECK-NEXT: {{ $}}318 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v8319 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s32>) = COPY $v9320 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_ADD [[COPY]], [[COPY1]]321 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s32>)322 ; CHECK-NEXT: PseudoRET implicit $v8323 %0:_(<vscale x 1 x s32>) = COPY $v8324 %1:_(<vscale x 1 x s32>) = COPY $v9325 %2:_(<vscale x 1 x s32>) = G_ADD %0, %1326 $v8 = COPY %2(<vscale x 1 x s32>)327 PseudoRET implicit $v8328 329...330---331name: vadd_vv_nxv2i32332legalized: true333tracksRegLiveness: true334body: |335 bb.0.entry:336 liveins: $v8, $v9337 338 ; CHECK-LABEL: name: vadd_vv_nxv2i32339 ; CHECK: liveins: $v8, $v9340 ; CHECK-NEXT: {{ $}}341 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v8342 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s32>) = COPY $v9343 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_ADD [[COPY]], [[COPY1]]344 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 2 x s32>)345 ; CHECK-NEXT: PseudoRET implicit $v8346 %0:_(<vscale x 2 x s32>) = COPY $v8347 %1:_(<vscale x 2 x s32>) = COPY $v9348 %2:_(<vscale x 2 x s32>) = G_ADD %0, %1349 $v8 = COPY %2(<vscale x 2 x s32>)350 PseudoRET implicit $v8351 352...353---354name: vadd_vv_nxv4i32355legalized: true356tracksRegLiveness: true357body: |358 bb.0.entry:359 liveins: $v8m2, $v10m2360 361 ; CHECK-LABEL: name: vadd_vv_nxv4i32362 ; CHECK: liveins: $v8m2, $v10m2363 ; CHECK-NEXT: {{ $}}364 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v8m2365 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s32>) = COPY $v10m2366 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_ADD [[COPY]], [[COPY1]]367 ; CHECK-NEXT: $v8m2 = COPY [[ADD]](<vscale x 4 x s32>)368 ; CHECK-NEXT: PseudoRET implicit $v8m2369 %0:_(<vscale x 4 x s32>) = COPY $v8m2370 %1:_(<vscale x 4 x s32>) = COPY $v10m2371 %2:_(<vscale x 4 x s32>) = G_ADD %0, %1372 $v8m2 = COPY %2(<vscale x 4 x s32>)373 PseudoRET implicit $v8m2374 375...376---377name: vadd_vv_nxv8i32378legalized: true379tracksRegLiveness: true380body: |381 bb.0.entry:382 liveins: $v8m4, $v12m4383 384 ; CHECK-LABEL: name: vadd_vv_nxv8i32385 ; CHECK: liveins: $v8m4, $v12m4386 ; CHECK-NEXT: {{ $}}387 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v8m4388 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s32>) = COPY $v12m4389 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_ADD [[COPY]], [[COPY1]]390 ; CHECK-NEXT: $v8m4 = COPY [[ADD]](<vscale x 8 x s32>)391 ; CHECK-NEXT: PseudoRET implicit $v8m4392 %0:_(<vscale x 8 x s32>) = COPY $v8m4393 %1:_(<vscale x 8 x s32>) = COPY $v12m4394 %2:_(<vscale x 8 x s32>) = G_ADD %0, %1395 $v8m4 = COPY %2(<vscale x 8 x s32>)396 PseudoRET implicit $v8m4397 398...399---400name: vadd_vv_nxv16i32401legalized: true402tracksRegLiveness: true403body: |404 bb.0.entry:405 liveins: $v8m8, $v16m8406 407 ; CHECK-LABEL: name: vadd_vv_nxv16i32408 ; CHECK: liveins: $v8m8, $v16m8409 ; CHECK-NEXT: {{ $}}410 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v8m8411 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 16 x s32>) = COPY $v16m8412 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_ADD [[COPY]], [[COPY1]]413 ; CHECK-NEXT: $v8m8 = COPY [[ADD]](<vscale x 16 x s32>)414 ; CHECK-NEXT: PseudoRET implicit $v8m8415 %0:_(<vscale x 16 x s32>) = COPY $v8m8416 %1:_(<vscale x 16 x s32>) = COPY $v16m8417 %2:_(<vscale x 16 x s32>) = G_ADD %0, %1418 $v8m8 = COPY %2(<vscale x 16 x s32>)419 PseudoRET implicit $v8m8420 421...422---423name: vadd_vv_nxv1i64424legalized: true425tracksRegLiveness: true426body: |427 bb.0.entry:428 liveins: $v8, $v9429 430 ; CHECK-LABEL: name: vadd_vv_nxv1i64431 ; CHECK: liveins: $v8, $v9432 ; CHECK-NEXT: {{ $}}433 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v8434 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 1 x s64>) = COPY $v9435 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_ADD [[COPY]], [[COPY1]]436 ; CHECK-NEXT: $v8 = COPY [[ADD]](<vscale x 1 x s64>)437 ; CHECK-NEXT: PseudoRET implicit $v8438 %0:_(<vscale x 1 x s64>) = COPY $v8439 %1:_(<vscale x 1 x s64>) = COPY $v9440 %2:_(<vscale x 1 x s64>) = G_ADD %0, %1441 $v8 = COPY %2(<vscale x 1 x s64>)442 PseudoRET implicit $v8443 444...445---446name: vadd_vv_nxv2i64447legalized: true448tracksRegLiveness: true449body: |450 bb.0.entry:451 liveins: $v8m2, $v10m2452 453 ; CHECK-LABEL: name: vadd_vv_nxv2i64454 ; CHECK: liveins: $v8m2, $v10m2455 ; CHECK-NEXT: {{ $}}456 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v8m2457 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 2 x s64>) = COPY $v10m2458 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_ADD [[COPY]], [[COPY1]]459 ; CHECK-NEXT: $v8m2 = COPY [[ADD]](<vscale x 2 x s64>)460 ; CHECK-NEXT: PseudoRET implicit $v8m2461 %0:_(<vscale x 2 x s64>) = COPY $v8m2462 %1:_(<vscale x 2 x s64>) = COPY $v10m2463 %2:_(<vscale x 2 x s64>) = G_ADD %0, %1464 $v8m2 = COPY %2(<vscale x 2 x s64>)465 PseudoRET implicit $v8m2466 467...468---469name: vadd_vv_nxv4i64470legalized: true471tracksRegLiveness: true472body: |473 bb.0.entry:474 liveins: $v8m4, $v12m4475 476 ; CHECK-LABEL: name: vadd_vv_nxv4i64477 ; CHECK: liveins: $v8m4, $v12m4478 ; CHECK-NEXT: {{ $}}479 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v8m4480 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 4 x s64>) = COPY $v12m4481 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_ADD [[COPY]], [[COPY1]]482 ; CHECK-NEXT: $v8m4 = COPY [[ADD]](<vscale x 4 x s64>)483 ; CHECK-NEXT: PseudoRET implicit $v8m4484 %0:_(<vscale x 4 x s64>) = COPY $v8m4485 %1:_(<vscale x 4 x s64>) = COPY $v12m4486 %2:_(<vscale x 4 x s64>) = G_ADD %0, %1487 $v8m4 = COPY %2(<vscale x 4 x s64>)488 PseudoRET implicit $v8m4489 490...491---492name: vadd_vv_nxv8i64493legalized: true494tracksRegLiveness: true495body: |496 bb.0.entry:497 liveins: $v8m8, $v16m8498 499 ; CHECK-LABEL: name: vadd_vv_nxv8i64500 ; CHECK: liveins: $v8m8, $v16m8501 ; CHECK-NEXT: {{ $}}502 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v8m8503 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrb(<vscale x 8 x s64>) = COPY $v16m8504 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_ADD [[COPY]], [[COPY1]]505 ; CHECK-NEXT: $v8m8 = COPY [[ADD]](<vscale x 8 x s64>)506 ; CHECK-NEXT: PseudoRET implicit $v8m8507 %0:_(<vscale x 8 x s64>) = COPY $v8m8508 %1:_(<vscale x 8 x s64>) = COPY $v16m8509 %2:_(<vscale x 8 x s64>) = G_ADD %0, %1510 $v8m8 = COPY %2(<vscale x 8 x s64>)511 PseudoRET implicit $v8m8512 513...514