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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \3# RUN: -simplify-mir -verify-machineinstrs %s \4# RUN: -o - | FileCheck %s5# RUN: llc -mtriple=riscv64 -mattr=+m,+v -run-pass=regbankselect \6# RUN: -simplify-mir -verify-machineinstrs %s \7# RUN: -o - | FileCheck %s8--- |9 10 define <vscale x 1 x i8> @vload_nx1i8(ptr %pa) #0 {11 %va = load <vscale x 1 x i8>, ptr %pa, align 112 ret <vscale x 1 x i8> %va13 }14 15 define <vscale x 2 x i8> @vload_nx2i8(ptr %pa) #0 {16 %va = load <vscale x 2 x i8>, ptr %pa, align 217 ret <vscale x 2 x i8> %va18 }19 20 define <vscale x 4 x i8> @vload_nx4i8(ptr %pa) #0 {21 %va = load <vscale x 4 x i8>, ptr %pa, align 422 ret <vscale x 4 x i8> %va23 }24 25 define <vscale x 8 x i8> @vload_nx8i8(ptr %pa) #0 {26 %va = load <vscale x 8 x i8>, ptr %pa, align 827 ret <vscale x 8 x i8> %va28 }29 30 define <vscale x 16 x i8> @vload_nx16i8(ptr %pa) #0 {31 %va = load <vscale x 16 x i8>, ptr %pa, align 1632 ret <vscale x 16 x i8> %va33 }34 35 define <vscale x 32 x i8> @vload_nx32i8(ptr %pa) #0 {36 %va = load <vscale x 32 x i8>, ptr %pa, align 3237 ret <vscale x 32 x i8> %va38 }39 40 define <vscale x 64 x i8> @vload_nx64i8(ptr %pa) #0 {41 %va = load <vscale x 64 x i8>, ptr %pa, align 6442 ret <vscale x 64 x i8> %va43 }44 45 define <vscale x 1 x i16> @vload_nx1i16(ptr %pa) #0 {46 %va = load <vscale x 1 x i16>, ptr %pa, align 247 ret <vscale x 1 x i16> %va48 }49 50 define <vscale x 2 x i16> @vload_nx2i16(ptr %pa) #0 {51 %va = load <vscale x 2 x i16>, ptr %pa, align 452 ret <vscale x 2 x i16> %va53 }54 55 define <vscale x 4 x i16> @vload_nx4i16(ptr %pa) #0 {56 %va = load <vscale x 4 x i16>, ptr %pa, align 857 ret <vscale x 4 x i16> %va58 }59 60 define <vscale x 8 x i16> @vload_nx8i16(ptr %pa) #0 {61 %va = load <vscale x 8 x i16>, ptr %pa, align 1662 ret <vscale x 8 x i16> %va63 }64 65 define <vscale x 16 x i16> @vload_nx16i16(ptr %pa) #0 {66 %va = load <vscale x 16 x i16>, ptr %pa, align 3267 ret <vscale x 16 x i16> %va68 }69 70 define <vscale x 32 x i16> @vload_nx32i16(ptr %pa) #0 {71 %va = load <vscale x 32 x i16>, ptr %pa, align 6472 ret <vscale x 32 x i16> %va73 }74 75 define <vscale x 1 x i32> @vload_nx1i32(ptr %pa) #0 {76 %va = load <vscale x 1 x i32>, ptr %pa, align 477 ret <vscale x 1 x i32> %va78 }79 80 define <vscale x 2 x i32> @vload_nx2i32(ptr %pa) #0 {81 %va = load <vscale x 2 x i32>, ptr %pa, align 882 ret <vscale x 2 x i32> %va83 }84 85 define <vscale x 4 x i32> @vload_nx4i32(ptr %pa) #0 {86 %va = load <vscale x 4 x i32>, ptr %pa, align 1687 ret <vscale x 4 x i32> %va88 }89 90 define <vscale x 8 x i32> @vload_nx8i32(ptr %pa) #0 {91 %va = load <vscale x 8 x i32>, ptr %pa, align 3292 ret <vscale x 8 x i32> %va93 }94 95 define <vscale x 16 x i32> @vload_nx16i32(ptr %pa) #0 {96 %va = load <vscale x 16 x i32>, ptr %pa, align 6497 ret <vscale x 16 x i32> %va98 }99 100 define <vscale x 1 x i64> @vload_nx1i64(ptr %pa) #0 {101 %va = load <vscale x 1 x i64>, ptr %pa, align 8102 ret <vscale x 1 x i64> %va103 }104 105 define <vscale x 2 x i64> @vload_nx2i64(ptr %pa) #0 {106 %va = load <vscale x 2 x i64>, ptr %pa, align 16107 ret <vscale x 2 x i64> %va108 }109 110 define <vscale x 4 x i64> @vload_nx4i64(ptr %pa) #0 {111 %va = load <vscale x 4 x i64>, ptr %pa, align 32112 ret <vscale x 4 x i64> %va113 }114 115 define <vscale x 8 x i64> @vload_nx8i64(ptr %pa) #0 {116 %va = load <vscale x 8 x i64>, ptr %pa, align 64117 ret <vscale x 8 x i64> %va118 }119 120 define <vscale x 16 x i8> @vload_nx16i8_align1(ptr %pa) #0 {121 %va = load <vscale x 16 x i8>, ptr %pa, align 1122 ret <vscale x 16 x i8> %va123 }124 125 define <vscale x 16 x i8> @vload_nx16i8_align2(ptr %pa) #0 {126 %va = load <vscale x 16 x i8>, ptr %pa, align 2127 ret <vscale x 16 x i8> %va128 }129 130 define <vscale x 16 x i8> @vload_nx16i8_align16(ptr %pa) #0 {131 %va = load <vscale x 16 x i8>, ptr %pa, align 16132 ret <vscale x 16 x i8> %va133 }134 135 define <vscale x 16 x i8> @vload_nx16i8_align64(ptr %pa) #0 {136 %va = load <vscale x 16 x i8>, ptr %pa, align 64137 ret <vscale x 16 x i8> %va138 }139 140 define <vscale x 4 x i16> @vload_nx4i16_align1(ptr %pa) #0 {141 %va = load <vscale x 4 x i16>, ptr %pa, align 1142 ret <vscale x 4 x i16> %va143 }144 145 define <vscale x 4 x i16> @vload_nx4i16_align2(ptr %pa) #0 {146 %va = load <vscale x 4 x i16>, ptr %pa, align 2147 ret <vscale x 4 x i16> %va148 }149 150 define <vscale x 4 x i16> @vload_nx4i16_align4(ptr %pa) #0 {151 %va = load <vscale x 4 x i16>, ptr %pa, align 4152 ret <vscale x 4 x i16> %va153 }154 155 define <vscale x 4 x i16> @vload_nx4i16_align8(ptr %pa) #0 {156 %va = load <vscale x 4 x i16>, ptr %pa, align 8157 ret <vscale x 4 x i16> %va158 }159 160 define <vscale x 4 x i16> @vload_nx4i16_align16(ptr %pa) #0 {161 %va = load <vscale x 4 x i16>, ptr %pa, align 16162 ret <vscale x 4 x i16> %va163 }164 165 define <vscale x 2 x i32> @vload_nx2i32_align2(ptr %pa) #0 {166 %va = load <vscale x 2 x i32>, ptr %pa, align 2167 ret <vscale x 2 x i32> %va168 }169 170 define <vscale x 2 x i32> @vload_nx2i32_align4(ptr %pa) #0 {171 %va = load <vscale x 2 x i32>, ptr %pa, align 4172 ret <vscale x 2 x i32> %va173 }174 175 define <vscale x 2 x i32> @vload_nx2i32_align8(ptr %pa) #0 {176 %va = load <vscale x 2 x i32>, ptr %pa, align 8177 ret <vscale x 2 x i32> %va178 }179 180 define <vscale x 2 x i32> @vload_nx2i32_align16(ptr %pa) #0 {181 %va = load <vscale x 2 x i32>, ptr %pa, align 16182 ret <vscale x 2 x i32> %va183 }184 185 define <vscale x 2 x i32> @vload_nx2i32_align256(ptr %pa) #0 {186 %va = load <vscale x 2 x i32>, ptr %pa, align 256187 ret <vscale x 2 x i32> %va188 }189 190 define <vscale x 2 x i64> @vload_nx2i64_align4(ptr %pa) #0 {191 %va = load <vscale x 2 x i64>, ptr %pa, align 4192 ret <vscale x 2 x i64> %va193 }194 195 define <vscale x 2 x i64> @vload_nx2i64_align8(ptr %pa) #0 {196 %va = load <vscale x 2 x i64>, ptr %pa, align 8197 ret <vscale x 2 x i64> %va198 }199 200 define <vscale x 2 x i64> @vload_nx2i64_align16(ptr %pa) #0 {201 %va = load <vscale x 2 x i64>, ptr %pa, align 16202 ret <vscale x 2 x i64> %va203 }204 205 define <vscale x 2 x i64> @vload_nx2i64_align32(ptr %pa) #0 {206 %va = load <vscale x 2 x i64>, ptr %pa, align 32207 ret <vscale x 2 x i64> %va208 }209 210 define <vscale x 1 x ptr> @vload_nx1ptr(ptr %pa) #0 {211 %va = load <vscale x 1 x ptr>, ptr %pa, align 4212 ret <vscale x 1 x ptr> %va213 }214 215 define <vscale x 2 x ptr> @vload_nx2ptr(ptr %pa) #0 {216 %va = load <vscale x 2 x ptr>, ptr %pa, align 8217 ret <vscale x 2 x ptr> %va218 }219 220 define <vscale x 8 x ptr> @vload_nx8ptr(ptr %pa) #0 {221 %va = load <vscale x 8 x ptr>, ptr %pa, align 32222 ret <vscale x 8 x ptr> %va223 }224 225...226---227name: vload_nx1i8228legalized: true229tracksRegLiveness: true230body: |231 bb.1 (%ir-block.0):232 liveins: $x10233 234 ; CHECK-LABEL: name: vload_nx1i8235 ; CHECK: liveins: $x10236 ; CHECK-NEXT: {{ $}}237 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10238 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s8>) from %ir.pa)239 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s8>)240 ; CHECK-NEXT: PseudoRET implicit $v8241 %0:_(p0) = COPY $x10242 %1:_(<vscale x 1 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s8>) from %ir.pa)243 $v8 = COPY %1(<vscale x 1 x s8>)244 PseudoRET implicit $v8245 246...247---248name: vload_nx2i8249legalized: true250tracksRegLiveness: true251body: |252 bb.1 (%ir-block.0):253 liveins: $x10254 255 ; CHECK-LABEL: name: vload_nx2i8256 ; CHECK: liveins: $x10257 ; CHECK-NEXT: {{ $}}258 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10259 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s8>) from %ir.pa)260 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s8>)261 ; CHECK-NEXT: PseudoRET implicit $v8262 %0:_(p0) = COPY $x10263 %1:_(<vscale x 2 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s8>) from %ir.pa)264 $v8 = COPY %1(<vscale x 2 x s8>)265 PseudoRET implicit $v8266 267...268---269name: vload_nx4i8270legalized: true271tracksRegLiveness: true272body: |273 bb.1 (%ir-block.0):274 liveins: $x10275 276 ; CHECK-LABEL: name: vload_nx4i8277 ; CHECK: liveins: $x10278 ; CHECK-NEXT: {{ $}}279 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10280 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s8>) from %ir.pa)281 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s8>)282 ; CHECK-NEXT: PseudoRET implicit $v8283 %0:_(p0) = COPY $x10284 %1:_(<vscale x 4 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s8>) from %ir.pa)285 $v8 = COPY %1(<vscale x 4 x s8>)286 PseudoRET implicit $v8287 288...289---290name: vload_nx8i8291legalized: true292tracksRegLiveness: true293body: |294 bb.1 (%ir-block.0):295 liveins: $x10296 297 ; CHECK-LABEL: name: vload_nx8i8298 ; CHECK: liveins: $x10299 ; CHECK-NEXT: {{ $}}300 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10301 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa)302 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 8 x s8>)303 ; CHECK-NEXT: PseudoRET implicit $v8304 %0:_(p0) = COPY $x10305 %1:_(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa)306 $v8 = COPY %1(<vscale x 8 x s8>)307 PseudoRET implicit $v8308 309...310---311name: vload_nx16i8312legalized: true313tracksRegLiveness: true314body: |315 bb.1 (%ir-block.0):316 liveins: $x10317 318 ; CHECK-LABEL: name: vload_nx16i8319 ; CHECK: liveins: $x10320 ; CHECK-NEXT: {{ $}}321 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10322 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)323 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)324 ; CHECK-NEXT: PseudoRET implicit $v8m2325 %0:_(p0) = COPY $x10326 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)327 $v8m2 = COPY %1(<vscale x 16 x s8>)328 PseudoRET implicit $v8m2329 330...331---332name: vload_nx32i8333legalized: true334tracksRegLiveness: true335body: |336 bb.1 (%ir-block.0):337 liveins: $x10338 339 ; CHECK-LABEL: name: vload_nx32i8340 ; CHECK: liveins: $x10341 ; CHECK-NEXT: {{ $}}342 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10343 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s8>) from %ir.pa)344 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 32 x s8>)345 ; CHECK-NEXT: PseudoRET implicit $v8m4346 %0:_(p0) = COPY $x10347 %1:_(<vscale x 32 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s8>) from %ir.pa)348 $v8m4 = COPY %1(<vscale x 32 x s8>)349 PseudoRET implicit $v8m4350 351...352---353name: vload_nx64i8354legalized: true355tracksRegLiveness: true356body: |357 bb.1 (%ir-block.0):358 liveins: $x10359 360 ; CHECK-LABEL: name: vload_nx64i8361 ; CHECK: liveins: $x10362 ; CHECK-NEXT: {{ $}}363 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10364 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 64 x s8>) from %ir.pa)365 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 64 x s8>)366 ; CHECK-NEXT: PseudoRET implicit $v8m8367 %0:_(p0) = COPY $x10368 %1:_(<vscale x 64 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 64 x s8>) from %ir.pa)369 $v8m8 = COPY %1(<vscale x 64 x s8>)370 PseudoRET implicit $v8m8371 372...373---374name: vload_nx1i16375legalized: true376tracksRegLiveness: true377body: |378 bb.1 (%ir-block.0):379 liveins: $x10380 381 ; CHECK-LABEL: name: vload_nx1i16382 ; CHECK: liveins: $x10383 ; CHECK-NEXT: {{ $}}384 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10385 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s16>) from %ir.pa)386 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s16>)387 ; CHECK-NEXT: PseudoRET implicit $v8388 %0:_(p0) = COPY $x10389 %1:_(<vscale x 1 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s16>) from %ir.pa)390 $v8 = COPY %1(<vscale x 1 x s16>)391 PseudoRET implicit $v8392 393...394---395name: vload_nx2i16396legalized: true397tracksRegLiveness: true398body: |399 bb.1 (%ir-block.0):400 liveins: $x10401 402 ; CHECK-LABEL: name: vload_nx2i16403 ; CHECK: liveins: $x10404 ; CHECK-NEXT: {{ $}}405 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10406 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s16>) from %ir.pa)407 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s16>)408 ; CHECK-NEXT: PseudoRET implicit $v8409 %0:_(p0) = COPY $x10410 %1:_(<vscale x 2 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s16>) from %ir.pa)411 $v8 = COPY %1(<vscale x 2 x s16>)412 PseudoRET implicit $v8413 414...415---416name: vload_nx4i16417legalized: true418tracksRegLiveness: true419body: |420 bb.1 (%ir-block.0):421 liveins: $x10422 423 ; CHECK-LABEL: name: vload_nx4i16424 ; CHECK: liveins: $x10425 ; CHECK-NEXT: {{ $}}426 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10427 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)428 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)429 ; CHECK-NEXT: PseudoRET implicit $v8430 %0:_(p0) = COPY $x10431 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)432 $v8 = COPY %1(<vscale x 4 x s16>)433 PseudoRET implicit $v8434 435...436---437name: vload_nx8i16438legalized: true439tracksRegLiveness: true440body: |441 bb.1 (%ir-block.0):442 liveins: $x10443 444 ; CHECK-LABEL: name: vload_nx8i16445 ; CHECK: liveins: $x10446 ; CHECK-NEXT: {{ $}}447 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10448 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s16>) from %ir.pa)449 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 8 x s16>)450 ; CHECK-NEXT: PseudoRET implicit $v8m2451 %0:_(p0) = COPY $x10452 %1:_(<vscale x 8 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s16>) from %ir.pa)453 $v8m2 = COPY %1(<vscale x 8 x s16>)454 PseudoRET implicit $v8m2455 456...457---458name: vload_nx16i16459legalized: true460tracksRegLiveness: true461body: |462 bb.1 (%ir-block.0):463 liveins: $x10464 465 ; CHECK-LABEL: name: vload_nx16i16466 ; CHECK: liveins: $x10467 ; CHECK-NEXT: {{ $}}468 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10469 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s16>) from %ir.pa)470 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x s16>)471 ; CHECK-NEXT: PseudoRET implicit $v8m4472 %0:_(p0) = COPY $x10473 %1:_(<vscale x 16 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s16>) from %ir.pa)474 $v8m4 = COPY %1(<vscale x 16 x s16>)475 PseudoRET implicit $v8m4476 477...478---479name: vload_nx32i16480legalized: true481tracksRegLiveness: true482body: |483 bb.1 (%ir-block.0):484 liveins: $x10485 486 ; CHECK-LABEL: name: vload_nx32i16487 ; CHECK: liveins: $x10488 ; CHECK-NEXT: {{ $}}489 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10490 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 32 x s16>) from %ir.pa)491 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 32 x s16>)492 ; CHECK-NEXT: PseudoRET implicit $v8m8493 %0:_(p0) = COPY $x10494 %1:_(<vscale x 32 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 32 x s16>) from %ir.pa)495 $v8m8 = COPY %1(<vscale x 32 x s16>)496 PseudoRET implicit $v8m8497 498...499---500name: vload_nx1i32501legalized: true502tracksRegLiveness: true503body: |504 bb.1 (%ir-block.0):505 liveins: $x10506 507 ; CHECK-LABEL: name: vload_nx1i32508 ; CHECK: liveins: $x10509 ; CHECK-NEXT: {{ $}}510 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10511 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s32>) from %ir.pa)512 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s32>)513 ; CHECK-NEXT: PseudoRET implicit $v8514 %0:_(p0) = COPY $x10515 %1:_(<vscale x 1 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s32>) from %ir.pa)516 $v8 = COPY %1(<vscale x 1 x s32>)517 PseudoRET implicit $v8518 519...520---521name: vload_nx2i32522legalized: true523tracksRegLiveness: true524body: |525 bb.1 (%ir-block.0):526 liveins: $x10527 528 ; CHECK-LABEL: name: vload_nx2i32529 ; CHECK: liveins: $x10530 ; CHECK-NEXT: {{ $}}531 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10532 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)533 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)534 ; CHECK-NEXT: PseudoRET implicit $v8535 %0:_(p0) = COPY $x10536 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)537 $v8 = COPY %1(<vscale x 2 x s32>)538 PseudoRET implicit $v8539 540...541---542name: vload_nx4i32543legalized: true544tracksRegLiveness: true545body: |546 bb.1 (%ir-block.0):547 liveins: $x10548 549 ; CHECK-LABEL: name: vload_nx4i32550 ; CHECK: liveins: $x10551 ; CHECK-NEXT: {{ $}}552 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10553 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s32>) from %ir.pa)554 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 4 x s32>)555 ; CHECK-NEXT: PseudoRET implicit $v8m2556 %0:_(p0) = COPY $x10557 %1:_(<vscale x 4 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s32>) from %ir.pa)558 $v8m2 = COPY %1(<vscale x 4 x s32>)559 PseudoRET implicit $v8m2560 561...562---563name: vload_nx8i32564legalized: true565tracksRegLiveness: true566body: |567 bb.1 (%ir-block.0):568 liveins: $x10569 570 ; CHECK-LABEL: name: vload_nx8i32571 ; CHECK: liveins: $x10572 ; CHECK-NEXT: {{ $}}573 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10574 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s32>) from %ir.pa)575 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x s32>)576 ; CHECK-NEXT: PseudoRET implicit $v8m4577 %0:_(p0) = COPY $x10578 %1:_(<vscale x 8 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s32>) from %ir.pa)579 $v8m4 = COPY %1(<vscale x 8 x s32>)580 PseudoRET implicit $v8m4581 582...583---584name: vload_nx16i32585legalized: true586tracksRegLiveness: true587body: |588 bb.1 (%ir-block.0):589 liveins: $x10590 591 ; CHECK-LABEL: name: vload_nx16i32592 ; CHECK: liveins: $x10593 ; CHECK-NEXT: {{ $}}594 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10595 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s32>) from %ir.pa)596 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 16 x s32>)597 ; CHECK-NEXT: PseudoRET implicit $v8m8598 %0:_(p0) = COPY $x10599 %1:_(<vscale x 16 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s32>) from %ir.pa)600 $v8m8 = COPY %1(<vscale x 16 x s32>)601 PseudoRET implicit $v8m8602 603...604---605name: vload_nx1i64606legalized: true607tracksRegLiveness: true608body: |609 bb.1 (%ir-block.0):610 liveins: $x10611 612 ; CHECK-LABEL: name: vload_nx1i64613 ; CHECK: liveins: $x10614 ; CHECK-NEXT: {{ $}}615 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10616 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x s64>) from %ir.pa)617 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x s64>)618 ; CHECK-NEXT: PseudoRET implicit $v8619 %0:_(p0) = COPY $x10620 %1:_(<vscale x 1 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 1 x s64>) from %ir.pa)621 $v8 = COPY %1(<vscale x 1 x s64>)622 PseudoRET implicit $v8623 624...625---626name: vload_nx2i64627legalized: true628tracksRegLiveness: true629body: |630 bb.1 (%ir-block.0):631 liveins: $x10632 633 ; CHECK-LABEL: name: vload_nx2i64634 ; CHECK: liveins: $x10635 ; CHECK-NEXT: {{ $}}636 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10637 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)638 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)639 ; CHECK-NEXT: PseudoRET implicit $v8m2640 %0:_(p0) = COPY $x10641 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)642 $v8m2 = COPY %1(<vscale x 2 x s64>)643 PseudoRET implicit $v8m2644 645...646---647name: vload_nx4i64648legalized: true649tracksRegLiveness: true650body: |651 bb.1 (%ir-block.0):652 liveins: $x10653 654 ; CHECK-LABEL: name: vload_nx4i64655 ; CHECK: liveins: $x10656 ; CHECK-NEXT: {{ $}}657 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10658 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s64>) from %ir.pa)659 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 4 x s64>)660 ; CHECK-NEXT: PseudoRET implicit $v8m4661 %0:_(p0) = COPY $x10662 %1:_(<vscale x 4 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s64>) from %ir.pa)663 $v8m4 = COPY %1(<vscale x 4 x s64>)664 PseudoRET implicit $v8m4665 666...667---668name: vload_nx8i64669legalized: true670tracksRegLiveness: true671body: |672 bb.1 (%ir-block.0):673 liveins: $x10674 675 ; CHECK-LABEL: name: vload_nx8i64676 ; CHECK: liveins: $x10677 ; CHECK-NEXT: {{ $}}678 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10679 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s64>) from %ir.pa)680 ; CHECK-NEXT: $v8m8 = COPY [[LOAD]](<vscale x 8 x s64>)681 ; CHECK-NEXT: PseudoRET implicit $v8m8682 %0:_(p0) = COPY $x10683 %1:_(<vscale x 8 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s64>) from %ir.pa)684 $v8m8 = COPY %1(<vscale x 8 x s64>)685 PseudoRET implicit $v8m8686 687...688---689name: vload_nx16i8_align1690legalized: true691tracksRegLiveness: true692body: |693 bb.1 (%ir-block.0):694 liveins: $x10695 696 ; CHECK-LABEL: name: vload_nx16i8_align1697 ; CHECK: liveins: $x10698 ; CHECK-NEXT: {{ $}}699 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10700 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)701 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)702 ; CHECK-NEXT: PseudoRET implicit $v8m2703 %0:_(p0) = COPY $x10704 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 1)705 $v8m2 = COPY %1(<vscale x 16 x s8>)706 PseudoRET implicit $v8m2707 708...709---710name: vload_nx16i8_align2711legalized: true712tracksRegLiveness: true713body: |714 bb.1 (%ir-block.0):715 liveins: $x10716 717 ; CHECK-LABEL: name: vload_nx16i8_align2718 ; CHECK: liveins: $x10719 ; CHECK-NEXT: {{ $}}720 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10721 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)722 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)723 ; CHECK-NEXT: PseudoRET implicit $v8m2724 %0:_(p0) = COPY $x10725 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 2)726 $v8m2 = COPY %1(<vscale x 16 x s8>)727 PseudoRET implicit $v8m2728 729...730---731name: vload_nx16i8_align16732legalized: true733tracksRegLiveness: true734body: |735 bb.1 (%ir-block.0):736 liveins: $x10737 738 ; CHECK-LABEL: name: vload_nx16i8_align16739 ; CHECK: liveins: $x10740 ; CHECK-NEXT: {{ $}}741 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10742 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa)743 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)744 ; CHECK-NEXT: PseudoRET implicit $v8m2745 %0:_(p0) = COPY $x10746 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa)747 $v8m2 = COPY %1(<vscale x 16 x s8>)748 PseudoRET implicit $v8m2749 750...751---752name: vload_nx16i8_align64753legalized: true754tracksRegLiveness: true755body: |756 bb.1 (%ir-block.0):757 liveins: $x10758 759 ; CHECK-LABEL: name: vload_nx16i8_align64760 ; CHECK: liveins: $x10761 ; CHECK-NEXT: {{ $}}762 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10763 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)764 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 16 x s8>)765 ; CHECK-NEXT: PseudoRET implicit $v8m2766 %0:_(p0) = COPY $x10767 %1:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 64)768 $v8m2 = COPY %1(<vscale x 16 x s8>)769 PseudoRET implicit $v8m2770 771...772---773name: vload_nx4i16_align1774legalized: true775tracksRegLiveness: true776body: |777 bb.1 (%ir-block.0):778 liveins: $x10779 780 ; CHECK-LABEL: name: vload_nx4i16_align1781 ; CHECK: liveins: $x10782 ; CHECK-NEXT: {{ $}}783 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10784 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 1)785 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)786 ; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 4 x s16>)787 ; CHECK-NEXT: PseudoRET implicit $v8788 %0:_(p0) = COPY $x10789 %2:_(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 1)790 %1:_(<vscale x 4 x s16>) = G_BITCAST %2(<vscale x 8 x s8>)791 $v8 = COPY %1(<vscale x 4 x s16>)792 PseudoRET implicit $v8793 794...795---796name: vload_nx4i16_align2797legalized: true798tracksRegLiveness: true799body: |800 bb.1 (%ir-block.0):801 liveins: $x10802 803 ; CHECK-LABEL: name: vload_nx4i16_align2804 ; CHECK: liveins: $x10805 ; CHECK-NEXT: {{ $}}806 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10807 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)808 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)809 ; CHECK-NEXT: PseudoRET implicit $v8810 %0:_(p0) = COPY $x10811 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 2)812 $v8 = COPY %1(<vscale x 4 x s16>)813 PseudoRET implicit $v8814 815...816---817name: vload_nx4i16_align4818legalized: true819tracksRegLiveness: true820body: |821 bb.1 (%ir-block.0):822 liveins: $x10823 824 ; CHECK-LABEL: name: vload_nx4i16_align4825 ; CHECK: liveins: $x10826 ; CHECK-NEXT: {{ $}}827 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10828 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)829 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)830 ; CHECK-NEXT: PseudoRET implicit $v8831 %0:_(p0) = COPY $x10832 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 4)833 $v8 = COPY %1(<vscale x 4 x s16>)834 PseudoRET implicit $v8835 836...837---838name: vload_nx4i16_align8839legalized: true840tracksRegLiveness: true841body: |842 bb.1 (%ir-block.0):843 liveins: $x10844 845 ; CHECK-LABEL: name: vload_nx4i16_align8846 ; CHECK: liveins: $x10847 ; CHECK-NEXT: {{ $}}848 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10849 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa)850 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)851 ; CHECK-NEXT: PseudoRET implicit $v8852 %0:_(p0) = COPY $x10853 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa)854 $v8 = COPY %1(<vscale x 4 x s16>)855 PseudoRET implicit $v8856 857...858---859name: vload_nx4i16_align16860legalized: true861tracksRegLiveness: true862body: |863 bb.1 (%ir-block.0):864 liveins: $x10865 866 ; CHECK-LABEL: name: vload_nx4i16_align16867 ; CHECK: liveins: $x10868 ; CHECK-NEXT: {{ $}}869 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10870 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)871 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 4 x s16>)872 ; CHECK-NEXT: PseudoRET implicit $v8873 %0:_(p0) = COPY $x10874 %1:_(<vscale x 4 x s16>) = G_LOAD %0(p0) :: (load (<vscale x 4 x s16>) from %ir.pa, align 16)875 $v8 = COPY %1(<vscale x 4 x s16>)876 PseudoRET implicit $v8877 878...879---880name: vload_nx2i32_align2881legalized: true882tracksRegLiveness: true883body: |884 bb.1 (%ir-block.0):885 liveins: $x10886 887 ; CHECK-LABEL: name: vload_nx2i32_align2888 ; CHECK: liveins: $x10889 ; CHECK-NEXT: {{ $}}890 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10891 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 2)892 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_BITCAST [[LOAD]](<vscale x 8 x s8>)893 ; CHECK-NEXT: $v8 = COPY [[BITCAST]](<vscale x 2 x s32>)894 ; CHECK-NEXT: PseudoRET implicit $v8895 %0:_(p0) = COPY $x10896 %2:_(<vscale x 8 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 8 x s8>) from %ir.pa, align 2)897 %1:_(<vscale x 2 x s32>) = G_BITCAST %2(<vscale x 8 x s8>)898 $v8 = COPY %1(<vscale x 2 x s32>)899 PseudoRET implicit $v8900 901...902---903name: vload_nx2i32_align4904legalized: true905tracksRegLiveness: true906body: |907 bb.1 (%ir-block.0):908 liveins: $x10909 910 ; CHECK-LABEL: name: vload_nx2i32_align4911 ; CHECK: liveins: $x10912 ; CHECK-NEXT: {{ $}}913 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10914 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)915 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)916 ; CHECK-NEXT: PseudoRET implicit $v8917 %0:_(p0) = COPY $x10918 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 4)919 $v8 = COPY %1(<vscale x 2 x s32>)920 PseudoRET implicit $v8921 922...923---924name: vload_nx2i32_align8925legalized: true926tracksRegLiveness: true927body: |928 bb.1 (%ir-block.0):929 liveins: $x10930 931 ; CHECK-LABEL: name: vload_nx2i32_align8932 ; CHECK: liveins: $x10933 ; CHECK-NEXT: {{ $}}934 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10935 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa)936 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)937 ; CHECK-NEXT: PseudoRET implicit $v8938 %0:_(p0) = COPY $x10939 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa)940 $v8 = COPY %1(<vscale x 2 x s32>)941 PseudoRET implicit $v8942 943...944---945name: vload_nx2i32_align16946legalized: true947tracksRegLiveness: true948body: |949 bb.1 (%ir-block.0):950 liveins: $x10951 952 ; CHECK-LABEL: name: vload_nx2i32_align16953 ; CHECK: liveins: $x10954 ; CHECK-NEXT: {{ $}}955 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10956 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)957 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)958 ; CHECK-NEXT: PseudoRET implicit $v8959 %0:_(p0) = COPY $x10960 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 16)961 $v8 = COPY %1(<vscale x 2 x s32>)962 PseudoRET implicit $v8963 964...965---966name: vload_nx2i32_align256967legalized: true968tracksRegLiveness: true969body: |970 bb.1 (%ir-block.0):971 liveins: $x10972 973 ; CHECK-LABEL: name: vload_nx2i32_align256974 ; CHECK: liveins: $x10975 ; CHECK-NEXT: {{ $}}976 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10977 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)978 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x s32>)979 ; CHECK-NEXT: PseudoRET implicit $v8980 %0:_(p0) = COPY $x10981 %1:_(<vscale x 2 x s32>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s32>) from %ir.pa, align 256)982 $v8 = COPY %1(<vscale x 2 x s32>)983 PseudoRET implicit $v8984 985...986---987name: vload_nx2i64_align4988legalized: true989tracksRegLiveness: true990body: |991 bb.1 (%ir-block.0):992 liveins: $x10993 994 ; CHECK-LABEL: name: vload_nx2i64_align4995 ; CHECK: liveins: $x10996 ; CHECK-NEXT: {{ $}}997 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10998 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 4)999 ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_BITCAST [[LOAD]](<vscale x 16 x s8>)1000 ; CHECK-NEXT: $v8m2 = COPY [[BITCAST]](<vscale x 2 x s64>)1001 ; CHECK-NEXT: PseudoRET implicit $v8m21002 %0:_(p0) = COPY $x101003 %2:_(<vscale x 16 x s8>) = G_LOAD %0(p0) :: (load (<vscale x 16 x s8>) from %ir.pa, align 4)1004 %1:_(<vscale x 2 x s64>) = G_BITCAST %2(<vscale x 16 x s8>)1005 $v8m2 = COPY %1(<vscale x 2 x s64>)1006 PseudoRET implicit $v8m21007 1008...1009---1010name: vload_nx2i64_align81011legalized: true1012tracksRegLiveness: true1013body: |1014 bb.1 (%ir-block.0):1015 liveins: $x101016 1017 ; CHECK-LABEL: name: vload_nx2i64_align81018 ; CHECK: liveins: $x101019 ; CHECK-NEXT: {{ $}}1020 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x101021 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)1022 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)1023 ; CHECK-NEXT: PseudoRET implicit $v8m21024 %0:_(p0) = COPY $x101025 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 8)1026 $v8m2 = COPY %1(<vscale x 2 x s64>)1027 PseudoRET implicit $v8m21028 1029...1030---1031name: vload_nx2i64_align161032legalized: true1033tracksRegLiveness: true1034body: |1035 bb.1 (%ir-block.0):1036 liveins: $x101037 1038 ; CHECK-LABEL: name: vload_nx2i64_align161039 ; CHECK: liveins: $x101040 ; CHECK-NEXT: {{ $}}1041 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x101042 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa)1043 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)1044 ; CHECK-NEXT: PseudoRET implicit $v8m21045 %0:_(p0) = COPY $x101046 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa)1047 $v8m2 = COPY %1(<vscale x 2 x s64>)1048 PseudoRET implicit $v8m21049 1050...1051---1052name: vload_nx2i64_align321053legalized: true1054tracksRegLiveness: true1055body: |1056 bb.1 (%ir-block.0):1057 liveins: $x101058 1059 ; CHECK-LABEL: name: vload_nx2i64_align321060 ; CHECK: liveins: $x101061 ; CHECK-NEXT: {{ $}}1062 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x101063 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)1064 ; CHECK-NEXT: $v8m2 = COPY [[LOAD]](<vscale x 2 x s64>)1065 ; CHECK-NEXT: PseudoRET implicit $v8m21066 %0:_(p0) = COPY $x101067 %1:_(<vscale x 2 x s64>) = G_LOAD %0(p0) :: (load (<vscale x 2 x s64>) from %ir.pa, align 32)1068 $v8m2 = COPY %1(<vscale x 2 x s64>)1069 PseudoRET implicit $v8m21070 1071...1072---1073name: vload_nx1ptr1074legalized: true1075tracksRegLiveness: true1076body: |1077 bb.1 (%ir-block.0):1078 liveins: $x101079 1080 ; CHECK-LABEL: name: vload_nx1ptr1081 ; CHECK: liveins: $x101082 ; CHECK-NEXT: {{ $}}1083 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x101084 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>) from %ir.pa)1085 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)1086 ; CHECK-NEXT: PseudoRET implicit $v81087 %0:_(p0) = COPY $x101088 %1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>) from %ir.pa)1089 $v8 = COPY %1(<vscale x 1 x p0>)1090 PseudoRET implicit $v81091 1092...1093---1094name: vload_nx2ptr1095legalized: true1096tracksRegLiveness: true1097body: |1098 bb.1 (%ir-block.0):1099 liveins: $x101100 1101 ; CHECK-LABEL: name: vload_nx2ptr1102 ; CHECK: liveins: $x101103 ; CHECK-NEXT: {{ $}}1104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x101105 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>) from %ir.pa)1106 ; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)1107 ; CHECK-NEXT: PseudoRET implicit $v81108 %0:_(p0) = COPY $x101109 %1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>) from %ir.pa)1110 $v8 = COPY %1(<vscale x 2 x p0>)1111 PseudoRET implicit $v81112 1113...1114---1115name: vload_nx8ptr1116legalized: true1117tracksRegLiveness: true1118body: |1119 bb.1 (%ir-block.0):1120 liveins: $x101121 1122 ; CHECK-LABEL: name: vload_nx8ptr1123 ; CHECK: liveins: $x101124 ; CHECK-NEXT: {{ $}}1125 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x101126 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vrb(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>) from %ir.pa)1127 ; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)1128 ; CHECK-NEXT: PseudoRET implicit $v8m41129 %0:_(p0) = COPY $x101130 %1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>) from %ir.pa)1131 $v8m4 = COPY %1(<vscale x 8 x p0>)1132 PseudoRET implicit $v8m41133 1134...1135