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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \3# RUN: -simplify-mir -verify-machineinstrs %s \4# RUN: -o - | FileCheck %s5 6---7name: splat_zero_nxv1i88legalized: true9regBankSelected: false10body: |11 bb.1:12 ; CHECK-LABEL: name: splat_zero_nxv1i813 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 014 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 1 x s8>) = G_SPLAT_VECTOR [[C]](s32)15 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s8>)16 ; CHECK-NEXT: PseudoRET implicit $v817 %3:_(s32) = G_CONSTANT i32 018 %0:_(<vscale x 1 x s8>) = G_SPLAT_VECTOR %3(s32)19 $v8 = COPY %0(<vscale x 1 x s8>)20 PseudoRET implicit $v821 22...23---24name: splat_zero_nxv2i825legalized: true26regBankSelected: false27body: |28 bb.1:29 ; CHECK-LABEL: name: splat_zero_nxv2i830 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 031 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 2 x s8>) = G_SPLAT_VECTOR [[C]](s32)32 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s8>)33 ; CHECK-NEXT: PseudoRET implicit $v834 %3:_(s32) = G_CONSTANT i32 035 %0:_(<vscale x 2 x s8>) = G_SPLAT_VECTOR %3(s32)36 $v8 = COPY %0(<vscale x 2 x s8>)37 PseudoRET implicit $v838 39...40---41name: splat_zero_nxv4i842legalized: true43regBankSelected: false44body: |45 bb.1:46 ; CHECK-LABEL: name: splat_zero_nxv4i847 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 048 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 4 x s8>) = G_SPLAT_VECTOR [[C]](s32)49 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s8>)50 ; CHECK-NEXT: PseudoRET implicit $v851 %3:_(s32) = G_CONSTANT i32 052 %0:_(<vscale x 4 x s8>) = G_SPLAT_VECTOR %3(s32)53 $v8 = COPY %0(<vscale x 4 x s8>)54 PseudoRET implicit $v855 56...57---58name: splat_zero_nxv8i859legalized: true60regBankSelected: false61body: |62 bb.1:63 ; CHECK-LABEL: name: splat_zero_nxv8i864 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 065 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 8 x s8>) = G_SPLAT_VECTOR [[C]](s32)66 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s8>)67 ; CHECK-NEXT: PseudoRET implicit $v868 %3:_(s32) = G_CONSTANT i32 069 %0:_(<vscale x 8 x s8>) = G_SPLAT_VECTOR %3(s32)70 $v8 = COPY %0(<vscale x 8 x s8>)71 PseudoRET implicit $v872 73...74---75name: splat_zero_nxv16i876legalized: true77regBankSelected: false78body: |79 bb.1:80 ; CHECK-LABEL: name: splat_zero_nxv16i881 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 082 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 16 x s8>) = G_SPLAT_VECTOR [[C]](s32)83 ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s8>)84 ; CHECK-NEXT: PseudoRET implicit $v8m285 %3:_(s32) = G_CONSTANT i32 086 %0:_(<vscale x 16 x s8>) = G_SPLAT_VECTOR %3(s32)87 $v8m2 = COPY %0(<vscale x 16 x s8>)88 PseudoRET implicit $v8m289 90...91---92name: splat_zero_nxv32i893legalized: true94regBankSelected: false95body: |96 bb.1:97 ; CHECK-LABEL: name: splat_zero_nxv32i898 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 099 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 32 x s8>) = G_SPLAT_VECTOR [[C]](s32)100 ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s8>)101 ; CHECK-NEXT: PseudoRET implicit $v8m4102 %3:_(s32) = G_CONSTANT i32 0103 %0:_(<vscale x 32 x s8>) = G_SPLAT_VECTOR %3(s32)104 $v8m4 = COPY %0(<vscale x 32 x s8>)105 PseudoRET implicit $v8m4106 107...108---109name: splat_zero_nxv64i8110legalized: true111regBankSelected: false112body: |113 bb.1:114 ; CHECK-LABEL: name: splat_zero_nxv64i8115 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0116 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 64 x s8>) = G_SPLAT_VECTOR [[C]](s32)117 ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 64 x s8>)118 ; CHECK-NEXT: PseudoRET implicit $v8m8119 %3:_(s32) = G_CONSTANT i32 0120 %0:_(<vscale x 64 x s8>) = G_SPLAT_VECTOR %3(s32)121 $v8m8 = COPY %0(<vscale x 64 x s8>)122 PseudoRET implicit $v8m8123 124...125---126name: splat_zero_nxv1i16127legalized: true128regBankSelected: false129body: |130 bb.1:131 ; CHECK-LABEL: name: splat_zero_nxv1i16132 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0133 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 1 x s16>) = G_SPLAT_VECTOR [[C]](s32)134 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s16>)135 ; CHECK-NEXT: PseudoRET implicit $v8136 %3:_(s32) = G_CONSTANT i32 0137 %0:_(<vscale x 1 x s16>) = G_SPLAT_VECTOR %3(s32)138 $v8 = COPY %0(<vscale x 1 x s16>)139 PseudoRET implicit $v8140 141...142---143name: splat_zero_nxv2i16144legalized: true145regBankSelected: false146body: |147 bb.1:148 ; CHECK-LABEL: name: splat_zero_nxv2i16149 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0150 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 2 x s16>) = G_SPLAT_VECTOR [[C]](s32)151 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s16>)152 ; CHECK-NEXT: PseudoRET implicit $v8153 %3:_(s32) = G_CONSTANT i32 0154 %0:_(<vscale x 2 x s16>) = G_SPLAT_VECTOR %3(s32)155 $v8 = COPY %0(<vscale x 2 x s16>)156 PseudoRET implicit $v8157 158...159---160name: splat_zero_nxv4i16161legalized: true162regBankSelected: false163body: |164 bb.1:165 ; CHECK-LABEL: name: splat_zero_nxv4i16166 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0167 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 4 x s16>) = G_SPLAT_VECTOR [[C]](s32)168 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s16>)169 ; CHECK-NEXT: PseudoRET implicit $v8170 %3:_(s32) = G_CONSTANT i32 0171 %0:_(<vscale x 4 x s16>) = G_SPLAT_VECTOR %3(s32)172 $v8 = COPY %0(<vscale x 4 x s16>)173 PseudoRET implicit $v8174 175...176---177name: splat_zero_nxv8i16178legalized: true179regBankSelected: false180body: |181 bb.1:182 ; CHECK-LABEL: name: splat_zero_nxv8i16183 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0184 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 8 x s16>) = G_SPLAT_VECTOR [[C]](s32)185 ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s16>)186 ; CHECK-NEXT: PseudoRET implicit $v8m2187 %3:_(s32) = G_CONSTANT i32 0188 %0:_(<vscale x 8 x s16>) = G_SPLAT_VECTOR %3(s32)189 $v8m2 = COPY %0(<vscale x 8 x s16>)190 PseudoRET implicit $v8m2191 192...193---194name: splat_zero_nxv16i16195legalized: true196regBankSelected: false197body: |198 bb.1:199 ; CHECK-LABEL: name: splat_zero_nxv16i16200 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0201 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 16 x s16>) = G_SPLAT_VECTOR [[C]](s32)202 ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s16>)203 ; CHECK-NEXT: PseudoRET implicit $v8m4204 %3:_(s32) = G_CONSTANT i32 0205 %0:_(<vscale x 16 x s16>) = G_SPLAT_VECTOR %3(s32)206 $v8m4 = COPY %0(<vscale x 16 x s16>)207 PseudoRET implicit $v8m4208 209...210---211name: splat_zero_nxv32i16212legalized: true213regBankSelected: false214body: |215 bb.1:216 ; CHECK-LABEL: name: splat_zero_nxv32i16217 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0218 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 32 x s16>) = G_SPLAT_VECTOR [[C]](s32)219 ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 32 x s16>)220 ; CHECK-NEXT: PseudoRET implicit $v8m8221 %3:_(s32) = G_CONSTANT i32 0222 %0:_(<vscale x 32 x s16>) = G_SPLAT_VECTOR %3(s32)223 $v8m8 = COPY %0(<vscale x 32 x s16>)224 PseudoRET implicit $v8m8225 226...227---228name: splat_zero_nxv1i32229legalized: true230regBankSelected: false231body: |232 bb.1:233 ; CHECK-LABEL: name: splat_zero_nxv1i32234 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0235 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32)236 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>)237 ; CHECK-NEXT: PseudoRET implicit $v8238 %1:_(s32) = G_CONSTANT i32 0239 %0:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR %1(s32)240 $v8 = COPY %0(<vscale x 1 x s32>)241 PseudoRET implicit $v8242 243...244---245name: splat_zero_nxv2i32246legalized: true247regBankSelected: false248body: |249 bb.1:250 ; CHECK-LABEL: name: splat_zero_nxv2i32251 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0252 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32)253 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>)254 ; CHECK-NEXT: PseudoRET implicit $v8255 %1:_(s32) = G_CONSTANT i32 0256 %0:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR %1(s32)257 $v8 = COPY %0(<vscale x 2 x s32>)258 PseudoRET implicit $v8259 260...261---262name: splat_zero_nxv4i32263legalized: true264regBankSelected: false265body: |266 bb.1:267 ; CHECK-LABEL: name: splat_zero_nxv4i32268 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0269 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32)270 ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>)271 ; CHECK-NEXT: PseudoRET implicit $v8m2272 %1:_(s32) = G_CONSTANT i32 0273 %0:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %1(s32)274 $v8m2 = COPY %0(<vscale x 4 x s32>)275 PseudoRET implicit $v8m2276 277...278---279name: splat_zero_nxv8i32280legalized: true281regBankSelected: false282body: |283 bb.1:284 ; CHECK-LABEL: name: splat_zero_nxv8i32285 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0286 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32)287 ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>)288 ; CHECK-NEXT: PseudoRET implicit $v8m4289 %1:_(s32) = G_CONSTANT i32 0290 %0:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR %1(s32)291 $v8m4 = COPY %0(<vscale x 8 x s32>)292 PseudoRET implicit $v8m4293 294...295---296name: splat_zero_nxv16i32297legalized: true298regBankSelected: false299body: |300 bb.1:301 ; CHECK-LABEL: name: splat_zero_nxv16i32302 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0303 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32)304 ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>)305 ; CHECK-NEXT: PseudoRET implicit $v8m8306 %1:_(s32) = G_CONSTANT i32 0307 %0:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR %1(s32)308 $v8m8 = COPY %0(<vscale x 16 x s32>)309 PseudoRET implicit $v8m8310 311...312---313name: splat_zero_nxv1i64314legalized: true315regBankSelected: false316body: |317 bb.1:318 ; CHECK-LABEL: name: splat_zero_nxv1i64319 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0320 ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0321 ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)322 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[MV]](s64)323 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>)324 ; CHECK-NEXT: PseudoRET implicit $v8325 %2:_(s32) = G_CONSTANT i32 0326 %3:_(s32) = G_CONSTANT i32 0327 %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)328 %0:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR %1(s64)329 $v8 = COPY %0(<vscale x 1 x s64>)330 PseudoRET implicit $v8331 332...333---334name: splat_zero_nxv2i64335legalized: true336regBankSelected: false337body: |338 bb.1:339 ; CHECK-LABEL: name: splat_zero_nxv2i64340 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0341 ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0342 ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)343 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[MV]](s64)344 ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>)345 ; CHECK-NEXT: PseudoRET implicit $v8m2346 %2:_(s32) = G_CONSTANT i32 0347 %3:_(s32) = G_CONSTANT i32 0348 %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)349 %0:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %1(s64)350 $v8m2 = COPY %0(<vscale x 2 x s64>)351 PseudoRET implicit $v8m2352 353...354---355name: splat_zero_nxv4i64356legalized: true357regBankSelected: false358body: |359 bb.1:360 ; CHECK-LABEL: name: splat_zero_nxv4i64361 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0362 ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0363 ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)364 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[MV]](s64)365 ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>)366 ; CHECK-NEXT: PseudoRET implicit $v8m4367 %2:_(s32) = G_CONSTANT i32 0368 %3:_(s32) = G_CONSTANT i32 0369 %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)370 %0:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR %1(s64)371 $v8m4 = COPY %0(<vscale x 4 x s64>)372 PseudoRET implicit $v8m4373 374...375---376name: splat_zero_nxv8i64377legalized: true378regBankSelected: false379body: |380 bb.1:381 ; CHECK-LABEL: name: splat_zero_nxv8i64382 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0383 ; CHECK-NEXT: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0384 ; CHECK-NEXT: [[MV:%[0-9]+]]:fprb(s64) = G_MERGE_VALUES [[C]](s32), [[C1]](s32)385 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[MV]](s64)386 ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>)387 ; CHECK-NEXT: PseudoRET implicit $v8m8388 %2:_(s32) = G_CONSTANT i32 0389 %3:_(s32) = G_CONSTANT i32 0390 %1:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)391 %0:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR %1(s64)392 $v8m8 = COPY %0(<vscale x 8 x s64>)393 PseudoRET implicit $v8m8394 395...396 397---398name: splat_zero_nxv1f32399legalized: true400regBankSelected: false401body: |402 bb.1:403 ; CHECK-LABEL: name: splat_zero_nxv1f32404 ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00405 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 1 x s32>) = G_SPLAT_VECTOR [[C]](s32)406 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s32>)407 ; CHECK-NEXT: PseudoRET implicit $v8408 %1:_(s32) = G_FCONSTANT float 0.000000e+00409 %0:_(<vscale x 1 x s32>) = G_SPLAT_VECTOR %1(s32)410 $v8 = COPY %0(<vscale x 1 x s32>)411 PseudoRET implicit $v8412 413...414---415name: splat_zero_nxv2f32416legalized: true417regBankSelected: false418body: |419 bb.1:420 ; CHECK-LABEL: name: splat_zero_nxv2f32421 ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00422 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 2 x s32>) = G_SPLAT_VECTOR [[C]](s32)423 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s32>)424 ; CHECK-NEXT: PseudoRET implicit $v8425 %1:_(s32) = G_FCONSTANT float 0.000000e+00426 %0:_(<vscale x 2 x s32>) = G_SPLAT_VECTOR %1(s32)427 $v8 = COPY %0(<vscale x 2 x s32>)428 PseudoRET implicit $v8429 430...431---432name: splat_zero_nxv4f32433legalized: true434regBankSelected: false435body: |436 bb.1:437 ; CHECK-LABEL: name: splat_zero_nxv4f32438 ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00439 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 4 x s32>) = G_SPLAT_VECTOR [[C]](s32)440 ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s32>)441 ; CHECK-NEXT: PseudoRET implicit $v8m2442 %1:_(s32) = G_FCONSTANT float 0.000000e+00443 %0:_(<vscale x 4 x s32>) = G_SPLAT_VECTOR %1(s32)444 $v8m2 = COPY %0(<vscale x 4 x s32>)445 PseudoRET implicit $v8m2446 447...448---449name: splat_zero_nxv8f32450legalized: true451regBankSelected: false452body: |453 bb.1:454 ; CHECK-LABEL: name: splat_zero_nxv8f32455 ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00456 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 8 x s32>) = G_SPLAT_VECTOR [[C]](s32)457 ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s32>)458 ; CHECK-NEXT: PseudoRET implicit $v8m4459 %1:_(s32) = G_FCONSTANT float 0.000000e+00460 %0:_(<vscale x 8 x s32>) = G_SPLAT_VECTOR %1(s32)461 $v8m4 = COPY %0(<vscale x 8 x s32>)462 PseudoRET implicit $v8m4463 464...465---466name: splat_zero_nxv16f32467legalized: true468regBankSelected: false469body: |470 bb.1:471 ; CHECK-LABEL: name: splat_zero_nxv16f32472 ; CHECK: [[C:%[0-9]+]]:fprb(s32) = G_FCONSTANT float 0.000000e+00473 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 16 x s32>) = G_SPLAT_VECTOR [[C]](s32)474 ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 16 x s32>)475 ; CHECK-NEXT: PseudoRET implicit $v8m8476 %1:_(s32) = G_FCONSTANT float 0.000000e+00477 %0:_(<vscale x 16 x s32>) = G_SPLAT_VECTOR %1(s32)478 $v8m8 = COPY %0(<vscale x 16 x s32>)479 PseudoRET implicit $v8m8480 481...482---483name: splat_zero_nxv1f64484legalized: true485regBankSelected: false486body: |487 bb.1:488 ; CHECK-LABEL: name: splat_zero_nxv1f64489 ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00490 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 1 x s64>) = G_SPLAT_VECTOR [[C]](s64)491 ; CHECK-NEXT: $v8 = COPY [[SPLAT_VECTOR]](<vscale x 1 x s64>)492 ; CHECK-NEXT: PseudoRET implicit $v8493 %1:_(s64) = G_FCONSTANT double 0.000000e+00494 %0:_(<vscale x 1 x s64>) = G_SPLAT_VECTOR %1(s64)495 $v8 = COPY %0(<vscale x 1 x s64>)496 PseudoRET implicit $v8497 498...499---500name: splat_zero_nxv2f64501legalized: true502regBankSelected: false503body: |504 bb.1:505 ; CHECK-LABEL: name: splat_zero_nxv2f64506 ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00507 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 2 x s64>) = G_SPLAT_VECTOR [[C]](s64)508 ; CHECK-NEXT: $v8m2 = COPY [[SPLAT_VECTOR]](<vscale x 2 x s64>)509 ; CHECK-NEXT: PseudoRET implicit $v8m2510 %1:_(s64) = G_FCONSTANT double 0.000000e+00511 %0:_(<vscale x 2 x s64>) = G_SPLAT_VECTOR %1(s64)512 $v8m2 = COPY %0(<vscale x 2 x s64>)513 PseudoRET implicit $v8m2514 515...516---517name: splat_zero_nxv4f64518legalized: true519regBankSelected: false520body: |521 bb.1:522 ; CHECK-LABEL: name: splat_zero_nxv4f64523 ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00524 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 4 x s64>) = G_SPLAT_VECTOR [[C]](s64)525 ; CHECK-NEXT: $v8m4 = COPY [[SPLAT_VECTOR]](<vscale x 4 x s64>)526 ; CHECK-NEXT: PseudoRET implicit $v8m4527 %1:_(s64) = G_FCONSTANT double 0.000000e+00528 %0:_(<vscale x 4 x s64>) = G_SPLAT_VECTOR %1(s64)529 $v8m4 = COPY %0(<vscale x 4 x s64>)530 PseudoRET implicit $v8m4531 532...533---534name: splat_zero_nxv8f64535legalized: true536regBankSelected: false537body: |538 bb.1:539 ; CHECK-LABEL: name: splat_zero_nxv8f64540 ; CHECK: [[C:%[0-9]+]]:fprb(s64) = G_FCONSTANT double 0.000000e+00541 ; CHECK-NEXT: [[SPLAT_VECTOR:%[0-9]+]]:vrb(<vscale x 8 x s64>) = G_SPLAT_VECTOR [[C]](s64)542 ; CHECK-NEXT: $v8m8 = COPY [[SPLAT_VECTOR]](<vscale x 8 x s64>)543 ; CHECK-NEXT: PseudoRET implicit $v8m8544 %1:_(s64) = G_FCONSTANT double 0.000000e+00545 %0:_(<vscale x 8 x s64>) = G_SPLAT_VECTOR %1(s64)546 $v8m8 = COPY %0(<vscale x 8 x s64>)547 PseudoRET implicit $v8m8548 549...550