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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=riscv32 -mattr=+m,+v -run-pass=regbankselect \3# RUN: -simplify-mir -verify-machineinstrs %s \4# RUN: -o - | FileCheck %s5 6---7name: splat_zero_nxv1i18legalized: true9regBankSelected: false10body: |11 bb.1:12 ; CHECK-LABEL: name: splat_zero_nxv1i113 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -114 ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 1 x s1>) = G_VMCLR_VL [[C]](s32)15 ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 1 x s1>)16 ; CHECK-NEXT: PseudoRET implicit $v017 %0:_(s32) = G_CONSTANT i32 -118 %1:_(<vscale x 1 x s1>) = G_VMCLR_VL %0(s32)19 $v0 = COPY %1(<vscale x 1 x s1>)20 PseudoRET implicit $v021 22...23---24name: splat_zero_nxv2i125legalized: true26regBankSelected: false27body: |28 bb.1:29 ; CHECK-LABEL: name: splat_zero_nxv2i130 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -131 ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 2 x s1>) = G_VMCLR_VL [[C]](s32)32 ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 2 x s1>)33 ; CHECK-NEXT: PseudoRET implicit $v034 %0:_(s32) = G_CONSTANT i32 -135 %1:_(<vscale x 2 x s1>) = G_VMCLR_VL %0(s32)36 $v0 = COPY %1(<vscale x 2 x s1>)37 PseudoRET implicit $v038 39...40---41name: splat_zero_nxv4i142legalized: true43regBankSelected: false44body: |45 bb.1:46 ; CHECK-LABEL: name: splat_zero_nxv4i147 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -148 ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 4 x s1>) = G_VMCLR_VL [[C]](s32)49 ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 4 x s1>)50 ; CHECK-NEXT: PseudoRET implicit $v051 %0:_(s32) = G_CONSTANT i32 -152 %1:_(<vscale x 4 x s1>) = G_VMCLR_VL %0(s32)53 $v0 = COPY %1(<vscale x 4 x s1>)54 PseudoRET implicit $v055 56...57---58name: splat_zero_nxv8i159legalized: true60regBankSelected: false61body: |62 bb.1:63 ; CHECK-LABEL: name: splat_zero_nxv8i164 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -165 ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 8 x s1>) = G_VMCLR_VL [[C]](s32)66 ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 8 x s1>)67 ; CHECK-NEXT: PseudoRET implicit $v068 %0:_(s32) = G_CONSTANT i32 -169 %1:_(<vscale x 8 x s1>) = G_VMCLR_VL %0(s32)70 $v0 = COPY %1(<vscale x 8 x s1>)71 PseudoRET implicit $v072 73...74---75name: splat_zero_nxv16i176legalized: true77regBankSelected: false78body: |79 bb.1:80 ; CHECK-LABEL: name: splat_zero_nxv16i181 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -182 ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 16 x s1>) = G_VMCLR_VL [[C]](s32)83 ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 16 x s1>)84 ; CHECK-NEXT: PseudoRET implicit $v085 %0:_(s32) = G_CONSTANT i32 -186 %1:_(<vscale x 16 x s1>) = G_VMCLR_VL %0(s32)87 $v0 = COPY %1(<vscale x 16 x s1>)88 PseudoRET implicit $v089 90...91---92name: splat_zero_nxv32i193legalized: true94regBankSelected: false95body: |96 bb.1:97 ; CHECK-LABEL: name: splat_zero_nxv32i198 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -199 ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 32 x s1>) = G_VMCLR_VL [[C]](s32)100 ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 32 x s1>)101 ; CHECK-NEXT: PseudoRET implicit $v0102 %0:_(s32) = G_CONSTANT i32 -1103 %1:_(<vscale x 32 x s1>) = G_VMCLR_VL %0(s32)104 $v0 = COPY %1(<vscale x 32 x s1>)105 PseudoRET implicit $v0106 107...108---109name: splat_zero_nxv64i1110legalized: true111regBankSelected: false112body: |113 bb.1:114 ; CHECK-LABEL: name: splat_zero_nxv64i1115 ; CHECK: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1116 ; CHECK-NEXT: [[VMCLR_VL:%[0-9]+]]:vrb(<vscale x 64 x s1>) = G_VMCLR_VL [[C]](s32)117 ; CHECK-NEXT: $v0 = COPY [[VMCLR_VL]](<vscale x 64 x s1>)118 ; CHECK-NEXT: PseudoRET implicit $v0119 %0:_(s32) = G_CONSTANT i32 -1120 %1:_(<vscale x 64 x s1>) = G_VMCLR_VL %0(s32)121 $v0 = COPY %1(<vscale x 64 x s1>)122 PseudoRET implicit $v0123 124...125 126