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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs -global-isel < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -enable-legalize-types-checking -global-isel < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs -global-isel < %s \7; RUN: | FileCheck %s -check-prefix=RV32ZBB8; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs -global-isel < %s \9; RUN: | FileCheck %s -check-prefix=RV64ZBB10; RUN: llc -mtriple=riscv32 -mattr=+xtheadbb -verify-machineinstrs -global-isel < %s \11; RUN: | FileCheck %s -check-prefix=RV32XTHEADBB12; RUN: llc -mtriple=riscv64 -mattr=+xtheadbb -verify-machineinstrs -global-isel < %s \13; RUN: | FileCheck %s -check-prefix=RV64XTHEADBB14 15; NOTE: -enable-legalize-types-checking is on one command line due to a previous16; assertion failure on an expensive checks build for @rotr_32_mask_multiple.17 18; These IR sequences are idioms for rotates. If rotate instructions are19; supported, they will be turned into ISD::ROTL or ISD::ROTR.20 21define i32 @rotl_32(i32 %x, i32 %y) nounwind {22; RV32I-LABEL: rotl_32:23; RV32I: # %bb.0:24; RV32I-NEXT: neg a2, a125; RV32I-NEXT: sll a1, a0, a126; RV32I-NEXT: srl a0, a0, a227; RV32I-NEXT: or a0, a1, a028; RV32I-NEXT: ret29;30; RV64I-LABEL: rotl_32:31; RV64I: # %bb.0:32; RV64I-NEXT: neg a2, a133; RV64I-NEXT: sllw a1, a0, a134; RV64I-NEXT: srlw a0, a0, a235; RV64I-NEXT: or a0, a1, a036; RV64I-NEXT: ret37;38; RV32ZBB-LABEL: rotl_32:39; RV32ZBB: # %bb.0:40; RV32ZBB-NEXT: rol a0, a0, a141; RV32ZBB-NEXT: ret42;43; RV64ZBB-LABEL: rotl_32:44; RV64ZBB: # %bb.0:45; RV64ZBB-NEXT: rolw a0, a0, a146; RV64ZBB-NEXT: ret47;48; RV32XTHEADBB-LABEL: rotl_32:49; RV32XTHEADBB: # %bb.0:50; RV32XTHEADBB-NEXT: neg a2, a151; RV32XTHEADBB-NEXT: sll a1, a0, a152; RV32XTHEADBB-NEXT: srl a0, a0, a253; RV32XTHEADBB-NEXT: or a0, a1, a054; RV32XTHEADBB-NEXT: ret55;56; RV64XTHEADBB-LABEL: rotl_32:57; RV64XTHEADBB: # %bb.0:58; RV64XTHEADBB-NEXT: neg a2, a159; RV64XTHEADBB-NEXT: sllw a1, a0, a160; RV64XTHEADBB-NEXT: srlw a0, a0, a261; RV64XTHEADBB-NEXT: or a0, a1, a062; RV64XTHEADBB-NEXT: ret63 %z = sub i32 32, %y64 %b = shl i32 %x, %y65 %c = lshr i32 %x, %z66 %d = or i32 %b, %c67 ret i32 %d68}69 70define i32 @rotr_32(i32 %x, i32 %y) nounwind {71; RV32I-LABEL: rotr_32:72; RV32I: # %bb.0:73; RV32I-NEXT: neg a2, a174; RV32I-NEXT: srl a1, a0, a175; RV32I-NEXT: sll a0, a0, a276; RV32I-NEXT: or a0, a1, a077; RV32I-NEXT: ret78;79; RV64I-LABEL: rotr_32:80; RV64I: # %bb.0:81; RV64I-NEXT: neg a2, a182; RV64I-NEXT: srlw a1, a0, a183; RV64I-NEXT: sllw a0, a0, a284; RV64I-NEXT: or a0, a1, a085; RV64I-NEXT: ret86;87; RV32ZBB-LABEL: rotr_32:88; RV32ZBB: # %bb.0:89; RV32ZBB-NEXT: ror a0, a0, a190; RV32ZBB-NEXT: ret91;92; RV64ZBB-LABEL: rotr_32:93; RV64ZBB: # %bb.0:94; RV64ZBB-NEXT: rorw a0, a0, a195; RV64ZBB-NEXT: ret96;97; RV32XTHEADBB-LABEL: rotr_32:98; RV32XTHEADBB: # %bb.0:99; RV32XTHEADBB-NEXT: neg a2, a1100; RV32XTHEADBB-NEXT: srl a1, a0, a1101; RV32XTHEADBB-NEXT: sll a0, a0, a2102; RV32XTHEADBB-NEXT: or a0, a1, a0103; RV32XTHEADBB-NEXT: ret104;105; RV64XTHEADBB-LABEL: rotr_32:106; RV64XTHEADBB: # %bb.0:107; RV64XTHEADBB-NEXT: neg a2, a1108; RV64XTHEADBB-NEXT: srlw a1, a0, a1109; RV64XTHEADBB-NEXT: sllw a0, a0, a2110; RV64XTHEADBB-NEXT: or a0, a1, a0111; RV64XTHEADBB-NEXT: ret112 %z = sub i32 32, %y113 %b = lshr i32 %x, %y114 %c = shl i32 %x, %z115 %d = or i32 %b, %c116 ret i32 %d117}118 119define i64 @rotl_64(i64 %x, i64 %y) nounwind {120; RV32I-LABEL: rotl_64:121; RV32I: # %bb.0:122; RV32I-NEXT: andi a6, a2, 63123; RV32I-NEXT: li a4, 32124; RV32I-NEXT: bltu a6, a4, .LBB2_2125; RV32I-NEXT: # %bb.1:126; RV32I-NEXT: li a3, 0127; RV32I-NEXT: sll a7, a0, a6128; RV32I-NEXT: j .LBB2_3129; RV32I-NEXT: .LBB2_2:130; RV32I-NEXT: sll a3, a0, a2131; RV32I-NEXT: neg a5, a6132; RV32I-NEXT: srl a5, a0, a5133; RV32I-NEXT: sll a7, a1, a2134; RV32I-NEXT: or a7, a5, a7135; RV32I-NEXT: .LBB2_3:136; RV32I-NEXT: neg a5, a2137; RV32I-NEXT: mv a2, a1138; RV32I-NEXT: beqz a6, .LBB2_5139; RV32I-NEXT: # %bb.4:140; RV32I-NEXT: mv a2, a7141; RV32I-NEXT: .LBB2_5:142; RV32I-NEXT: andi a6, a5, 63143; RV32I-NEXT: bltu a6, a4, .LBB2_7144; RV32I-NEXT: # %bb.6:145; RV32I-NEXT: srl a7, a1, a6146; RV32I-NEXT: bnez a6, .LBB2_8147; RV32I-NEXT: j .LBB2_9148; RV32I-NEXT: .LBB2_7:149; RV32I-NEXT: srl a7, a0, a5150; RV32I-NEXT: neg t0, a6151; RV32I-NEXT: sll t0, a1, t0152; RV32I-NEXT: or a7, a7, t0153; RV32I-NEXT: beqz a6, .LBB2_9154; RV32I-NEXT: .LBB2_8:155; RV32I-NEXT: mv a0, a7156; RV32I-NEXT: .LBB2_9:157; RV32I-NEXT: bltu a6, a4, .LBB2_11158; RV32I-NEXT: # %bb.10:159; RV32I-NEXT: li a1, 0160; RV32I-NEXT: j .LBB2_12161; RV32I-NEXT: .LBB2_11:162; RV32I-NEXT: srl a1, a1, a5163; RV32I-NEXT: .LBB2_12:164; RV32I-NEXT: or a0, a3, a0165; RV32I-NEXT: or a1, a2, a1166; RV32I-NEXT: ret167;168; RV64I-LABEL: rotl_64:169; RV64I: # %bb.0:170; RV64I-NEXT: neg a2, a1171; RV64I-NEXT: sll a1, a0, a1172; RV64I-NEXT: srl a0, a0, a2173; RV64I-NEXT: or a0, a1, a0174; RV64I-NEXT: ret175;176; RV32ZBB-LABEL: rotl_64:177; RV32ZBB: # %bb.0:178; RV32ZBB-NEXT: andi a6, a2, 63179; RV32ZBB-NEXT: li a4, 32180; RV32ZBB-NEXT: bltu a6, a4, .LBB2_2181; RV32ZBB-NEXT: # %bb.1:182; RV32ZBB-NEXT: li a3, 0183; RV32ZBB-NEXT: sll a7, a0, a6184; RV32ZBB-NEXT: j .LBB2_3185; RV32ZBB-NEXT: .LBB2_2:186; RV32ZBB-NEXT: sll a3, a0, a2187; RV32ZBB-NEXT: neg a5, a6188; RV32ZBB-NEXT: srl a5, a0, a5189; RV32ZBB-NEXT: sll a7, a1, a2190; RV32ZBB-NEXT: or a7, a5, a7191; RV32ZBB-NEXT: .LBB2_3:192; RV32ZBB-NEXT: neg a5, a2193; RV32ZBB-NEXT: mv a2, a1194; RV32ZBB-NEXT: beqz a6, .LBB2_5195; RV32ZBB-NEXT: # %bb.4:196; RV32ZBB-NEXT: mv a2, a7197; RV32ZBB-NEXT: .LBB2_5:198; RV32ZBB-NEXT: andi a6, a5, 63199; RV32ZBB-NEXT: bltu a6, a4, .LBB2_7200; RV32ZBB-NEXT: # %bb.6:201; RV32ZBB-NEXT: srl a7, a1, a6202; RV32ZBB-NEXT: bnez a6, .LBB2_8203; RV32ZBB-NEXT: j .LBB2_9204; RV32ZBB-NEXT: .LBB2_7:205; RV32ZBB-NEXT: srl a7, a0, a5206; RV32ZBB-NEXT: neg t0, a6207; RV32ZBB-NEXT: sll t0, a1, t0208; RV32ZBB-NEXT: or a7, a7, t0209; RV32ZBB-NEXT: beqz a6, .LBB2_9210; RV32ZBB-NEXT: .LBB2_8:211; RV32ZBB-NEXT: mv a0, a7212; RV32ZBB-NEXT: .LBB2_9:213; RV32ZBB-NEXT: bltu a6, a4, .LBB2_11214; RV32ZBB-NEXT: # %bb.10:215; RV32ZBB-NEXT: li a1, 0216; RV32ZBB-NEXT: j .LBB2_12217; RV32ZBB-NEXT: .LBB2_11:218; RV32ZBB-NEXT: srl a1, a1, a5219; RV32ZBB-NEXT: .LBB2_12:220; RV32ZBB-NEXT: or a0, a3, a0221; RV32ZBB-NEXT: or a1, a2, a1222; RV32ZBB-NEXT: ret223;224; RV64ZBB-LABEL: rotl_64:225; RV64ZBB: # %bb.0:226; RV64ZBB-NEXT: rol a0, a0, a1227; RV64ZBB-NEXT: ret228;229; RV32XTHEADBB-LABEL: rotl_64:230; RV32XTHEADBB: # %bb.0:231; RV32XTHEADBB-NEXT: andi a6, a2, 63232; RV32XTHEADBB-NEXT: li a4, 32233; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB2_2234; RV32XTHEADBB-NEXT: # %bb.1:235; RV32XTHEADBB-NEXT: li a3, 0236; RV32XTHEADBB-NEXT: sll a7, a0, a6237; RV32XTHEADBB-NEXT: j .LBB2_3238; RV32XTHEADBB-NEXT: .LBB2_2:239; RV32XTHEADBB-NEXT: sll a3, a0, a2240; RV32XTHEADBB-NEXT: neg a5, a6241; RV32XTHEADBB-NEXT: srl a5, a0, a5242; RV32XTHEADBB-NEXT: sll a7, a1, a2243; RV32XTHEADBB-NEXT: or a7, a5, a7244; RV32XTHEADBB-NEXT: .LBB2_3:245; RV32XTHEADBB-NEXT: neg a5, a2246; RV32XTHEADBB-NEXT: mv a2, a1247; RV32XTHEADBB-NEXT: beqz a6, .LBB2_5248; RV32XTHEADBB-NEXT: # %bb.4:249; RV32XTHEADBB-NEXT: mv a2, a7250; RV32XTHEADBB-NEXT: .LBB2_5:251; RV32XTHEADBB-NEXT: andi a6, a5, 63252; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB2_7253; RV32XTHEADBB-NEXT: # %bb.6:254; RV32XTHEADBB-NEXT: srl a7, a1, a6255; RV32XTHEADBB-NEXT: bnez a6, .LBB2_8256; RV32XTHEADBB-NEXT: j .LBB2_9257; RV32XTHEADBB-NEXT: .LBB2_7:258; RV32XTHEADBB-NEXT: srl a7, a0, a5259; RV32XTHEADBB-NEXT: neg t0, a6260; RV32XTHEADBB-NEXT: sll t0, a1, t0261; RV32XTHEADBB-NEXT: or a7, a7, t0262; RV32XTHEADBB-NEXT: beqz a6, .LBB2_9263; RV32XTHEADBB-NEXT: .LBB2_8:264; RV32XTHEADBB-NEXT: mv a0, a7265; RV32XTHEADBB-NEXT: .LBB2_9:266; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB2_11267; RV32XTHEADBB-NEXT: # %bb.10:268; RV32XTHEADBB-NEXT: li a1, 0269; RV32XTHEADBB-NEXT: j .LBB2_12270; RV32XTHEADBB-NEXT: .LBB2_11:271; RV32XTHEADBB-NEXT: srl a1, a1, a5272; RV32XTHEADBB-NEXT: .LBB2_12:273; RV32XTHEADBB-NEXT: or a0, a3, a0274; RV32XTHEADBB-NEXT: or a1, a2, a1275; RV32XTHEADBB-NEXT: ret276;277; RV64XTHEADBB-LABEL: rotl_64:278; RV64XTHEADBB: # %bb.0:279; RV64XTHEADBB-NEXT: neg a2, a1280; RV64XTHEADBB-NEXT: sll a1, a0, a1281; RV64XTHEADBB-NEXT: srl a0, a0, a2282; RV64XTHEADBB-NEXT: or a0, a1, a0283; RV64XTHEADBB-NEXT: ret284 %z = sub i64 64, %y285 %b = shl i64 %x, %y286 %c = lshr i64 %x, %z287 %d = or i64 %b, %c288 ret i64 %d289}290 291define i64 @rotr_64(i64 %x, i64 %y) nounwind {292; RV32I-LABEL: rotr_64:293; RV32I: # %bb.0:294; RV32I-NEXT: andi a5, a2, 63295; RV32I-NEXT: li a4, 32296; RV32I-NEXT: bltu a5, a4, .LBB3_2297; RV32I-NEXT: # %bb.1:298; RV32I-NEXT: srl a6, a1, a5299; RV32I-NEXT: mv a3, a0300; RV32I-NEXT: bnez a5, .LBB3_3301; RV32I-NEXT: j .LBB3_4302; RV32I-NEXT: .LBB3_2:303; RV32I-NEXT: srl a3, a0, a2304; RV32I-NEXT: neg a6, a5305; RV32I-NEXT: sll a6, a1, a6306; RV32I-NEXT: or a6, a3, a6307; RV32I-NEXT: mv a3, a0308; RV32I-NEXT: beqz a5, .LBB3_4309; RV32I-NEXT: .LBB3_3:310; RV32I-NEXT: mv a3, a6311; RV32I-NEXT: .LBB3_4:312; RV32I-NEXT: neg a6, a2313; RV32I-NEXT: bltu a5, a4, .LBB3_7314; RV32I-NEXT: # %bb.5:315; RV32I-NEXT: li a2, 0316; RV32I-NEXT: andi a5, a6, 63317; RV32I-NEXT: bgeu a5, a4, .LBB3_8318; RV32I-NEXT: .LBB3_6:319; RV32I-NEXT: sll a4, a0, a6320; RV32I-NEXT: neg a7, a5321; RV32I-NEXT: srl a0, a0, a7322; RV32I-NEXT: sll a6, a1, a6323; RV32I-NEXT: or a0, a0, a6324; RV32I-NEXT: bnez a5, .LBB3_9325; RV32I-NEXT: j .LBB3_10326; RV32I-NEXT: .LBB3_7:327; RV32I-NEXT: srl a2, a1, a2328; RV32I-NEXT: andi a5, a6, 63329; RV32I-NEXT: bltu a5, a4, .LBB3_6330; RV32I-NEXT: .LBB3_8:331; RV32I-NEXT: li a4, 0332; RV32I-NEXT: sll a0, a0, a5333; RV32I-NEXT: beqz a5, .LBB3_10334; RV32I-NEXT: .LBB3_9:335; RV32I-NEXT: mv a1, a0336; RV32I-NEXT: .LBB3_10:337; RV32I-NEXT: or a0, a3, a4338; RV32I-NEXT: or a1, a2, a1339; RV32I-NEXT: ret340;341; RV64I-LABEL: rotr_64:342; RV64I: # %bb.0:343; RV64I-NEXT: neg a2, a1344; RV64I-NEXT: srl a1, a0, a1345; RV64I-NEXT: sll a0, a0, a2346; RV64I-NEXT: or a0, a1, a0347; RV64I-NEXT: ret348;349; RV32ZBB-LABEL: rotr_64:350; RV32ZBB: # %bb.0:351; RV32ZBB-NEXT: andi a5, a2, 63352; RV32ZBB-NEXT: li a4, 32353; RV32ZBB-NEXT: bltu a5, a4, .LBB3_2354; RV32ZBB-NEXT: # %bb.1:355; RV32ZBB-NEXT: srl a6, a1, a5356; RV32ZBB-NEXT: mv a3, a0357; RV32ZBB-NEXT: bnez a5, .LBB3_3358; RV32ZBB-NEXT: j .LBB3_4359; RV32ZBB-NEXT: .LBB3_2:360; RV32ZBB-NEXT: srl a3, a0, a2361; RV32ZBB-NEXT: neg a6, a5362; RV32ZBB-NEXT: sll a6, a1, a6363; RV32ZBB-NEXT: or a6, a3, a6364; RV32ZBB-NEXT: mv a3, a0365; RV32ZBB-NEXT: beqz a5, .LBB3_4366; RV32ZBB-NEXT: .LBB3_3:367; RV32ZBB-NEXT: mv a3, a6368; RV32ZBB-NEXT: .LBB3_4:369; RV32ZBB-NEXT: neg a6, a2370; RV32ZBB-NEXT: bltu a5, a4, .LBB3_7371; RV32ZBB-NEXT: # %bb.5:372; RV32ZBB-NEXT: li a2, 0373; RV32ZBB-NEXT: andi a5, a6, 63374; RV32ZBB-NEXT: bgeu a5, a4, .LBB3_8375; RV32ZBB-NEXT: .LBB3_6:376; RV32ZBB-NEXT: sll a4, a0, a6377; RV32ZBB-NEXT: neg a7, a5378; RV32ZBB-NEXT: srl a0, a0, a7379; RV32ZBB-NEXT: sll a6, a1, a6380; RV32ZBB-NEXT: or a0, a0, a6381; RV32ZBB-NEXT: bnez a5, .LBB3_9382; RV32ZBB-NEXT: j .LBB3_10383; RV32ZBB-NEXT: .LBB3_7:384; RV32ZBB-NEXT: srl a2, a1, a2385; RV32ZBB-NEXT: andi a5, a6, 63386; RV32ZBB-NEXT: bltu a5, a4, .LBB3_6387; RV32ZBB-NEXT: .LBB3_8:388; RV32ZBB-NEXT: li a4, 0389; RV32ZBB-NEXT: sll a0, a0, a5390; RV32ZBB-NEXT: beqz a5, .LBB3_10391; RV32ZBB-NEXT: .LBB3_9:392; RV32ZBB-NEXT: mv a1, a0393; RV32ZBB-NEXT: .LBB3_10:394; RV32ZBB-NEXT: or a0, a3, a4395; RV32ZBB-NEXT: or a1, a2, a1396; RV32ZBB-NEXT: ret397;398; RV64ZBB-LABEL: rotr_64:399; RV64ZBB: # %bb.0:400; RV64ZBB-NEXT: ror a0, a0, a1401; RV64ZBB-NEXT: ret402;403; RV32XTHEADBB-LABEL: rotr_64:404; RV32XTHEADBB: # %bb.0:405; RV32XTHEADBB-NEXT: andi a5, a2, 63406; RV32XTHEADBB-NEXT: li a4, 32407; RV32XTHEADBB-NEXT: bltu a5, a4, .LBB3_2408; RV32XTHEADBB-NEXT: # %bb.1:409; RV32XTHEADBB-NEXT: srl a6, a1, a5410; RV32XTHEADBB-NEXT: mv a3, a0411; RV32XTHEADBB-NEXT: bnez a5, .LBB3_3412; RV32XTHEADBB-NEXT: j .LBB3_4413; RV32XTHEADBB-NEXT: .LBB3_2:414; RV32XTHEADBB-NEXT: srl a3, a0, a2415; RV32XTHEADBB-NEXT: neg a6, a5416; RV32XTHEADBB-NEXT: sll a6, a1, a6417; RV32XTHEADBB-NEXT: or a6, a3, a6418; RV32XTHEADBB-NEXT: mv a3, a0419; RV32XTHEADBB-NEXT: beqz a5, .LBB3_4420; RV32XTHEADBB-NEXT: .LBB3_3:421; RV32XTHEADBB-NEXT: mv a3, a6422; RV32XTHEADBB-NEXT: .LBB3_4:423; RV32XTHEADBB-NEXT: neg a6, a2424; RV32XTHEADBB-NEXT: bltu a5, a4, .LBB3_7425; RV32XTHEADBB-NEXT: # %bb.5:426; RV32XTHEADBB-NEXT: li a2, 0427; RV32XTHEADBB-NEXT: andi a5, a6, 63428; RV32XTHEADBB-NEXT: bgeu a5, a4, .LBB3_8429; RV32XTHEADBB-NEXT: .LBB3_6:430; RV32XTHEADBB-NEXT: sll a4, a0, a6431; RV32XTHEADBB-NEXT: neg a7, a5432; RV32XTHEADBB-NEXT: srl a0, a0, a7433; RV32XTHEADBB-NEXT: sll a6, a1, a6434; RV32XTHEADBB-NEXT: or a0, a0, a6435; RV32XTHEADBB-NEXT: bnez a5, .LBB3_9436; RV32XTHEADBB-NEXT: j .LBB3_10437; RV32XTHEADBB-NEXT: .LBB3_7:438; RV32XTHEADBB-NEXT: srl a2, a1, a2439; RV32XTHEADBB-NEXT: andi a5, a6, 63440; RV32XTHEADBB-NEXT: bltu a5, a4, .LBB3_6441; RV32XTHEADBB-NEXT: .LBB3_8:442; RV32XTHEADBB-NEXT: li a4, 0443; RV32XTHEADBB-NEXT: sll a0, a0, a5444; RV32XTHEADBB-NEXT: beqz a5, .LBB3_10445; RV32XTHEADBB-NEXT: .LBB3_9:446; RV32XTHEADBB-NEXT: mv a1, a0447; RV32XTHEADBB-NEXT: .LBB3_10:448; RV32XTHEADBB-NEXT: or a0, a3, a4449; RV32XTHEADBB-NEXT: or a1, a2, a1450; RV32XTHEADBB-NEXT: ret451;452; RV64XTHEADBB-LABEL: rotr_64:453; RV64XTHEADBB: # %bb.0:454; RV64XTHEADBB-NEXT: neg a2, a1455; RV64XTHEADBB-NEXT: srl a1, a0, a1456; RV64XTHEADBB-NEXT: sll a0, a0, a2457; RV64XTHEADBB-NEXT: or a0, a1, a0458; RV64XTHEADBB-NEXT: ret459 %z = sub i64 64, %y460 %b = lshr i64 %x, %y461 %c = shl i64 %x, %z462 %d = or i64 %b, %c463 ret i64 %d464}465 466define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {467; RV32I-LABEL: rotl_32_mask:468; RV32I: # %bb.0:469; RV32I-NEXT: neg a2, a1470; RV32I-NEXT: sll a1, a0, a1471; RV32I-NEXT: srl a0, a0, a2472; RV32I-NEXT: or a0, a1, a0473; RV32I-NEXT: ret474;475; RV64I-LABEL: rotl_32_mask:476; RV64I: # %bb.0:477; RV64I-NEXT: neg a2, a1478; RV64I-NEXT: sllw a1, a0, a1479; RV64I-NEXT: srlw a0, a0, a2480; RV64I-NEXT: or a0, a1, a0481; RV64I-NEXT: ret482;483; RV32ZBB-LABEL: rotl_32_mask:484; RV32ZBB: # %bb.0:485; RV32ZBB-NEXT: neg a2, a1486; RV32ZBB-NEXT: sll a1, a0, a1487; RV32ZBB-NEXT: srl a0, a0, a2488; RV32ZBB-NEXT: or a0, a1, a0489; RV32ZBB-NEXT: ret490;491; RV64ZBB-LABEL: rotl_32_mask:492; RV64ZBB: # %bb.0:493; RV64ZBB-NEXT: neg a2, a1494; RV64ZBB-NEXT: sllw a1, a0, a1495; RV64ZBB-NEXT: srlw a0, a0, a2496; RV64ZBB-NEXT: or a0, a1, a0497; RV64ZBB-NEXT: ret498;499; RV32XTHEADBB-LABEL: rotl_32_mask:500; RV32XTHEADBB: # %bb.0:501; RV32XTHEADBB-NEXT: neg a2, a1502; RV32XTHEADBB-NEXT: sll a1, a0, a1503; RV32XTHEADBB-NEXT: srl a0, a0, a2504; RV32XTHEADBB-NEXT: or a0, a1, a0505; RV32XTHEADBB-NEXT: ret506;507; RV64XTHEADBB-LABEL: rotl_32_mask:508; RV64XTHEADBB: # %bb.0:509; RV64XTHEADBB-NEXT: neg a2, a1510; RV64XTHEADBB-NEXT: sllw a1, a0, a1511; RV64XTHEADBB-NEXT: srlw a0, a0, a2512; RV64XTHEADBB-NEXT: or a0, a1, a0513; RV64XTHEADBB-NEXT: ret514 %z = sub i32 0, %y515 %and = and i32 %z, 31516 %b = shl i32 %x, %y517 %c = lshr i32 %x, %and518 %d = or i32 %b, %c519 ret i32 %d520}521 522define i32 @rotl_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {523; RV32I-LABEL: rotl_32_mask_and_63_and_31:524; RV32I: # %bb.0:525; RV32I-NEXT: sll a2, a0, a1526; RV32I-NEXT: neg a1, a1527; RV32I-NEXT: srl a0, a0, a1528; RV32I-NEXT: or a0, a2, a0529; RV32I-NEXT: ret530;531; RV64I-LABEL: rotl_32_mask_and_63_and_31:532; RV64I: # %bb.0:533; RV64I-NEXT: sllw a2, a0, a1534; RV64I-NEXT: neg a1, a1535; RV64I-NEXT: srlw a0, a0, a1536; RV64I-NEXT: or a0, a2, a0537; RV64I-NEXT: ret538;539; RV32ZBB-LABEL: rotl_32_mask_and_63_and_31:540; RV32ZBB: # %bb.0:541; RV32ZBB-NEXT: sll a2, a0, a1542; RV32ZBB-NEXT: neg a1, a1543; RV32ZBB-NEXT: srl a0, a0, a1544; RV32ZBB-NEXT: or a0, a2, a0545; RV32ZBB-NEXT: ret546;547; RV64ZBB-LABEL: rotl_32_mask_and_63_and_31:548; RV64ZBB: # %bb.0:549; RV64ZBB-NEXT: sllw a2, a0, a1550; RV64ZBB-NEXT: neg a1, a1551; RV64ZBB-NEXT: srlw a0, a0, a1552; RV64ZBB-NEXT: or a0, a2, a0553; RV64ZBB-NEXT: ret554;555; RV32XTHEADBB-LABEL: rotl_32_mask_and_63_and_31:556; RV32XTHEADBB: # %bb.0:557; RV32XTHEADBB-NEXT: sll a2, a0, a1558; RV32XTHEADBB-NEXT: neg a1, a1559; RV32XTHEADBB-NEXT: srl a0, a0, a1560; RV32XTHEADBB-NEXT: or a0, a2, a0561; RV32XTHEADBB-NEXT: ret562;563; RV64XTHEADBB-LABEL: rotl_32_mask_and_63_and_31:564; RV64XTHEADBB: # %bb.0:565; RV64XTHEADBB-NEXT: sllw a2, a0, a1566; RV64XTHEADBB-NEXT: neg a1, a1567; RV64XTHEADBB-NEXT: srlw a0, a0, a1568; RV64XTHEADBB-NEXT: or a0, a2, a0569; RV64XTHEADBB-NEXT: ret570 %a = and i32 %y, 63571 %b = shl i32 %x, %a572 %c = sub i32 0, %y573 %d = and i32 %c, 31574 %e = lshr i32 %x, %d575 %f = or i32 %b, %e576 ret i32 %f577}578 579define i32 @rotl_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {580; RV32I-LABEL: rotl_32_mask_or_64_or_32:581; RV32I: # %bb.0:582; RV32I-NEXT: ori a1, a1, 64583; RV32I-NEXT: sll a0, a0, a1584; RV32I-NEXT: ret585;586; RV64I-LABEL: rotl_32_mask_or_64_or_32:587; RV64I: # %bb.0:588; RV64I-NEXT: ori a1, a1, 64589; RV64I-NEXT: sllw a0, a0, a1590; RV64I-NEXT: ret591;592; RV32ZBB-LABEL: rotl_32_mask_or_64_or_32:593; RV32ZBB: # %bb.0:594; RV32ZBB-NEXT: ori a1, a1, 64595; RV32ZBB-NEXT: sll a0, a0, a1596; RV32ZBB-NEXT: ret597;598; RV64ZBB-LABEL: rotl_32_mask_or_64_or_32:599; RV64ZBB: # %bb.0:600; RV64ZBB-NEXT: ori a1, a1, 64601; RV64ZBB-NEXT: sllw a0, a0, a1602; RV64ZBB-NEXT: ret603;604; RV32XTHEADBB-LABEL: rotl_32_mask_or_64_or_32:605; RV32XTHEADBB: # %bb.0:606; RV32XTHEADBB-NEXT: ori a1, a1, 64607; RV32XTHEADBB-NEXT: sll a0, a0, a1608; RV32XTHEADBB-NEXT: ret609;610; RV64XTHEADBB-LABEL: rotl_32_mask_or_64_or_32:611; RV64XTHEADBB: # %bb.0:612; RV64XTHEADBB-NEXT: ori a1, a1, 64613; RV64XTHEADBB-NEXT: sllw a0, a0, a1614; RV64XTHEADBB-NEXT: ret615 %a = or i32 %y, 64616 %b = shl i32 %x, %a617 %c = sub i32 0, %y618 %d = or i32 %c, 32619 %e = lshr i32 %x, %d620 %f = or i32 %b, %e621 ret i32 %f622}623 624define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {625; RV32I-LABEL: rotr_32_mask:626; RV32I: # %bb.0:627; RV32I-NEXT: neg a2, a1628; RV32I-NEXT: srl a1, a0, a1629; RV32I-NEXT: sll a0, a0, a2630; RV32I-NEXT: or a0, a1, a0631; RV32I-NEXT: ret632;633; RV64I-LABEL: rotr_32_mask:634; RV64I: # %bb.0:635; RV64I-NEXT: neg a2, a1636; RV64I-NEXT: srlw a1, a0, a1637; RV64I-NEXT: sllw a0, a0, a2638; RV64I-NEXT: or a0, a1, a0639; RV64I-NEXT: ret640;641; RV32ZBB-LABEL: rotr_32_mask:642; RV32ZBB: # %bb.0:643; RV32ZBB-NEXT: neg a2, a1644; RV32ZBB-NEXT: srl a1, a0, a1645; RV32ZBB-NEXT: sll a0, a0, a2646; RV32ZBB-NEXT: or a0, a1, a0647; RV32ZBB-NEXT: ret648;649; RV64ZBB-LABEL: rotr_32_mask:650; RV64ZBB: # %bb.0:651; RV64ZBB-NEXT: neg a2, a1652; RV64ZBB-NEXT: srlw a1, a0, a1653; RV64ZBB-NEXT: sllw a0, a0, a2654; RV64ZBB-NEXT: or a0, a1, a0655; RV64ZBB-NEXT: ret656;657; RV32XTHEADBB-LABEL: rotr_32_mask:658; RV32XTHEADBB: # %bb.0:659; RV32XTHEADBB-NEXT: neg a2, a1660; RV32XTHEADBB-NEXT: srl a1, a0, a1661; RV32XTHEADBB-NEXT: sll a0, a0, a2662; RV32XTHEADBB-NEXT: or a0, a1, a0663; RV32XTHEADBB-NEXT: ret664;665; RV64XTHEADBB-LABEL: rotr_32_mask:666; RV64XTHEADBB: # %bb.0:667; RV64XTHEADBB-NEXT: neg a2, a1668; RV64XTHEADBB-NEXT: srlw a1, a0, a1669; RV64XTHEADBB-NEXT: sllw a0, a0, a2670; RV64XTHEADBB-NEXT: or a0, a1, a0671; RV64XTHEADBB-NEXT: ret672 %z = sub i32 0, %y673 %and = and i32 %z, 31674 %b = lshr i32 %x, %y675 %c = shl i32 %x, %and676 %d = or i32 %b, %c677 ret i32 %d678}679 680define i32 @rotr_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {681; RV32I-LABEL: rotr_32_mask_and_63_and_31:682; RV32I: # %bb.0:683; RV32I-NEXT: srl a2, a0, a1684; RV32I-NEXT: neg a1, a1685; RV32I-NEXT: sll a0, a0, a1686; RV32I-NEXT: or a0, a2, a0687; RV32I-NEXT: ret688;689; RV64I-LABEL: rotr_32_mask_and_63_and_31:690; RV64I: # %bb.0:691; RV64I-NEXT: srlw a2, a0, a1692; RV64I-NEXT: neg a1, a1693; RV64I-NEXT: sllw a0, a0, a1694; RV64I-NEXT: or a0, a2, a0695; RV64I-NEXT: ret696;697; RV32ZBB-LABEL: rotr_32_mask_and_63_and_31:698; RV32ZBB: # %bb.0:699; RV32ZBB-NEXT: srl a2, a0, a1700; RV32ZBB-NEXT: neg a1, a1701; RV32ZBB-NEXT: sll a0, a0, a1702; RV32ZBB-NEXT: or a0, a2, a0703; RV32ZBB-NEXT: ret704;705; RV64ZBB-LABEL: rotr_32_mask_and_63_and_31:706; RV64ZBB: # %bb.0:707; RV64ZBB-NEXT: srlw a2, a0, a1708; RV64ZBB-NEXT: neg a1, a1709; RV64ZBB-NEXT: sllw a0, a0, a1710; RV64ZBB-NEXT: or a0, a2, a0711; RV64ZBB-NEXT: ret712;713; RV32XTHEADBB-LABEL: rotr_32_mask_and_63_and_31:714; RV32XTHEADBB: # %bb.0:715; RV32XTHEADBB-NEXT: srl a2, a0, a1716; RV32XTHEADBB-NEXT: neg a1, a1717; RV32XTHEADBB-NEXT: sll a0, a0, a1718; RV32XTHEADBB-NEXT: or a0, a2, a0719; RV32XTHEADBB-NEXT: ret720;721; RV64XTHEADBB-LABEL: rotr_32_mask_and_63_and_31:722; RV64XTHEADBB: # %bb.0:723; RV64XTHEADBB-NEXT: srlw a2, a0, a1724; RV64XTHEADBB-NEXT: neg a1, a1725; RV64XTHEADBB-NEXT: sllw a0, a0, a1726; RV64XTHEADBB-NEXT: or a0, a2, a0727; RV64XTHEADBB-NEXT: ret728 %a = and i32 %y, 63729 %b = lshr i32 %x, %a730 %c = sub i32 0, %y731 %d = and i32 %c, 31732 %e = shl i32 %x, %d733 %f = or i32 %b, %e734 ret i32 %f735}736 737define i32 @rotr_32_mask_or_64_or_32(i32 %x, i32 %y) nounwind {738; RV32I-LABEL: rotr_32_mask_or_64_or_32:739; RV32I: # %bb.0:740; RV32I-NEXT: ori a1, a1, 64741; RV32I-NEXT: srl a0, a0, a1742; RV32I-NEXT: ret743;744; RV64I-LABEL: rotr_32_mask_or_64_or_32:745; RV64I: # %bb.0:746; RV64I-NEXT: ori a1, a1, 64747; RV64I-NEXT: srlw a0, a0, a1748; RV64I-NEXT: ret749;750; RV32ZBB-LABEL: rotr_32_mask_or_64_or_32:751; RV32ZBB: # %bb.0:752; RV32ZBB-NEXT: ori a1, a1, 64753; RV32ZBB-NEXT: srl a0, a0, a1754; RV32ZBB-NEXT: ret755;756; RV64ZBB-LABEL: rotr_32_mask_or_64_or_32:757; RV64ZBB: # %bb.0:758; RV64ZBB-NEXT: ori a1, a1, 64759; RV64ZBB-NEXT: srlw a0, a0, a1760; RV64ZBB-NEXT: ret761;762; RV32XTHEADBB-LABEL: rotr_32_mask_or_64_or_32:763; RV32XTHEADBB: # %bb.0:764; RV32XTHEADBB-NEXT: ori a1, a1, 64765; RV32XTHEADBB-NEXT: srl a0, a0, a1766; RV32XTHEADBB-NEXT: ret767;768; RV64XTHEADBB-LABEL: rotr_32_mask_or_64_or_32:769; RV64XTHEADBB: # %bb.0:770; RV64XTHEADBB-NEXT: ori a1, a1, 64771; RV64XTHEADBB-NEXT: srlw a0, a0, a1772; RV64XTHEADBB-NEXT: ret773 %a = or i32 %y, 64774 %b = lshr i32 %x, %a775 %c = sub i32 0, %y776 %d = or i32 %c, 32777 %e = shl i32 %x, %d778 %f = or i32 %b, %e779 ret i32 %f780}781 782define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {783; RV32I-LABEL: rotl_64_mask:784; RV32I: # %bb.0:785; RV32I-NEXT: li a5, 32786; RV32I-NEXT: neg a4, a2787; RV32I-NEXT: bltu a2, a5, .LBB10_2788; RV32I-NEXT: # %bb.1:789; RV32I-NEXT: li a3, 0790; RV32I-NEXT: sll t0, a0, a2791; RV32I-NEXT: j .LBB10_3792; RV32I-NEXT: .LBB10_2:793; RV32I-NEXT: sll a3, a0, a2794; RV32I-NEXT: neg a6, a2795; RV32I-NEXT: srl a6, a0, a6796; RV32I-NEXT: sll a7, a1, a2797; RV32I-NEXT: or t0, a6, a7798; RV32I-NEXT: .LBB10_3:799; RV32I-NEXT: andi a7, a4, 63800; RV32I-NEXT: mv a6, a1801; RV32I-NEXT: beqz a2, .LBB10_5802; RV32I-NEXT: # %bb.4:803; RV32I-NEXT: mv a6, t0804; RV32I-NEXT: .LBB10_5:805; RV32I-NEXT: bltu a7, a5, .LBB10_7806; RV32I-NEXT: # %bb.6:807; RV32I-NEXT: srl a2, a1, a7808; RV32I-NEXT: bnez a7, .LBB10_8809; RV32I-NEXT: j .LBB10_9810; RV32I-NEXT: .LBB10_7:811; RV32I-NEXT: srl a2, a0, a4812; RV32I-NEXT: neg t0, a7813; RV32I-NEXT: sll t0, a1, t0814; RV32I-NEXT: or a2, a2, t0815; RV32I-NEXT: beqz a7, .LBB10_9816; RV32I-NEXT: .LBB10_8:817; RV32I-NEXT: mv a0, a2818; RV32I-NEXT: .LBB10_9:819; RV32I-NEXT: bltu a7, a5, .LBB10_11820; RV32I-NEXT: # %bb.10:821; RV32I-NEXT: li a1, 0822; RV32I-NEXT: j .LBB10_12823; RV32I-NEXT: .LBB10_11:824; RV32I-NEXT: srl a1, a1, a4825; RV32I-NEXT: .LBB10_12:826; RV32I-NEXT: or a0, a3, a0827; RV32I-NEXT: or a1, a6, a1828; RV32I-NEXT: ret829;830; RV64I-LABEL: rotl_64_mask:831; RV64I: # %bb.0:832; RV64I-NEXT: neg a2, a1833; RV64I-NEXT: sll a1, a0, a1834; RV64I-NEXT: srl a0, a0, a2835; RV64I-NEXT: or a0, a1, a0836; RV64I-NEXT: ret837;838; RV32ZBB-LABEL: rotl_64_mask:839; RV32ZBB: # %bb.0:840; RV32ZBB-NEXT: li a5, 32841; RV32ZBB-NEXT: neg a4, a2842; RV32ZBB-NEXT: bltu a2, a5, .LBB10_2843; RV32ZBB-NEXT: # %bb.1:844; RV32ZBB-NEXT: li a3, 0845; RV32ZBB-NEXT: sll t0, a0, a2846; RV32ZBB-NEXT: j .LBB10_3847; RV32ZBB-NEXT: .LBB10_2:848; RV32ZBB-NEXT: sll a3, a0, a2849; RV32ZBB-NEXT: neg a6, a2850; RV32ZBB-NEXT: srl a6, a0, a6851; RV32ZBB-NEXT: sll a7, a1, a2852; RV32ZBB-NEXT: or t0, a6, a7853; RV32ZBB-NEXT: .LBB10_3:854; RV32ZBB-NEXT: andi a7, a4, 63855; RV32ZBB-NEXT: mv a6, a1856; RV32ZBB-NEXT: beqz a2, .LBB10_5857; RV32ZBB-NEXT: # %bb.4:858; RV32ZBB-NEXT: mv a6, t0859; RV32ZBB-NEXT: .LBB10_5:860; RV32ZBB-NEXT: bltu a7, a5, .LBB10_7861; RV32ZBB-NEXT: # %bb.6:862; RV32ZBB-NEXT: srl a2, a1, a7863; RV32ZBB-NEXT: bnez a7, .LBB10_8864; RV32ZBB-NEXT: j .LBB10_9865; RV32ZBB-NEXT: .LBB10_7:866; RV32ZBB-NEXT: srl a2, a0, a4867; RV32ZBB-NEXT: neg t0, a7868; RV32ZBB-NEXT: sll t0, a1, t0869; RV32ZBB-NEXT: or a2, a2, t0870; RV32ZBB-NEXT: beqz a7, .LBB10_9871; RV32ZBB-NEXT: .LBB10_8:872; RV32ZBB-NEXT: mv a0, a2873; RV32ZBB-NEXT: .LBB10_9:874; RV32ZBB-NEXT: bltu a7, a5, .LBB10_11875; RV32ZBB-NEXT: # %bb.10:876; RV32ZBB-NEXT: li a1, 0877; RV32ZBB-NEXT: j .LBB10_12878; RV32ZBB-NEXT: .LBB10_11:879; RV32ZBB-NEXT: srl a1, a1, a4880; RV32ZBB-NEXT: .LBB10_12:881; RV32ZBB-NEXT: or a0, a3, a0882; RV32ZBB-NEXT: or a1, a6, a1883; RV32ZBB-NEXT: ret884;885; RV64ZBB-LABEL: rotl_64_mask:886; RV64ZBB: # %bb.0:887; RV64ZBB-NEXT: neg a2, a1888; RV64ZBB-NEXT: sll a1, a0, a1889; RV64ZBB-NEXT: srl a0, a0, a2890; RV64ZBB-NEXT: or a0, a1, a0891; RV64ZBB-NEXT: ret892;893; RV32XTHEADBB-LABEL: rotl_64_mask:894; RV32XTHEADBB: # %bb.0:895; RV32XTHEADBB-NEXT: li a5, 32896; RV32XTHEADBB-NEXT: neg a4, a2897; RV32XTHEADBB-NEXT: bltu a2, a5, .LBB10_2898; RV32XTHEADBB-NEXT: # %bb.1:899; RV32XTHEADBB-NEXT: li a3, 0900; RV32XTHEADBB-NEXT: sll t0, a0, a2901; RV32XTHEADBB-NEXT: j .LBB10_3902; RV32XTHEADBB-NEXT: .LBB10_2:903; RV32XTHEADBB-NEXT: sll a3, a0, a2904; RV32XTHEADBB-NEXT: neg a6, a2905; RV32XTHEADBB-NEXT: srl a6, a0, a6906; RV32XTHEADBB-NEXT: sll a7, a1, a2907; RV32XTHEADBB-NEXT: or t0, a6, a7908; RV32XTHEADBB-NEXT: .LBB10_3:909; RV32XTHEADBB-NEXT: andi a7, a4, 63910; RV32XTHEADBB-NEXT: mv a6, a1911; RV32XTHEADBB-NEXT: beqz a2, .LBB10_5912; RV32XTHEADBB-NEXT: # %bb.4:913; RV32XTHEADBB-NEXT: mv a6, t0914; RV32XTHEADBB-NEXT: .LBB10_5:915; RV32XTHEADBB-NEXT: bltu a7, a5, .LBB10_7916; RV32XTHEADBB-NEXT: # %bb.6:917; RV32XTHEADBB-NEXT: srl a2, a1, a7918; RV32XTHEADBB-NEXT: bnez a7, .LBB10_8919; RV32XTHEADBB-NEXT: j .LBB10_9920; RV32XTHEADBB-NEXT: .LBB10_7:921; RV32XTHEADBB-NEXT: srl a2, a0, a4922; RV32XTHEADBB-NEXT: neg t0, a7923; RV32XTHEADBB-NEXT: sll t0, a1, t0924; RV32XTHEADBB-NEXT: or a2, a2, t0925; RV32XTHEADBB-NEXT: beqz a7, .LBB10_9926; RV32XTHEADBB-NEXT: .LBB10_8:927; RV32XTHEADBB-NEXT: mv a0, a2928; RV32XTHEADBB-NEXT: .LBB10_9:929; RV32XTHEADBB-NEXT: bltu a7, a5, .LBB10_11930; RV32XTHEADBB-NEXT: # %bb.10:931; RV32XTHEADBB-NEXT: li a1, 0932; RV32XTHEADBB-NEXT: j .LBB10_12933; RV32XTHEADBB-NEXT: .LBB10_11:934; RV32XTHEADBB-NEXT: srl a1, a1, a4935; RV32XTHEADBB-NEXT: .LBB10_12:936; RV32XTHEADBB-NEXT: or a0, a3, a0937; RV32XTHEADBB-NEXT: or a1, a6, a1938; RV32XTHEADBB-NEXT: ret939;940; RV64XTHEADBB-LABEL: rotl_64_mask:941; RV64XTHEADBB: # %bb.0:942; RV64XTHEADBB-NEXT: neg a2, a1943; RV64XTHEADBB-NEXT: sll a1, a0, a1944; RV64XTHEADBB-NEXT: srl a0, a0, a2945; RV64XTHEADBB-NEXT: or a0, a1, a0946; RV64XTHEADBB-NEXT: ret947 %z = sub i64 0, %y948 %and = and i64 %z, 63949 %b = shl i64 %x, %y950 %c = lshr i64 %x, %and951 %d = or i64 %b, %c952 ret i64 %d953}954 955define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {956; RV32I-LABEL: rotl_64_mask_and_127_and_63:957; RV32I: # %bb.0:958; RV32I-NEXT: andi a6, a2, 127959; RV32I-NEXT: li a4, 32960; RV32I-NEXT: bltu a6, a4, .LBB11_2961; RV32I-NEXT: # %bb.1:962; RV32I-NEXT: li a3, 0963; RV32I-NEXT: sll a7, a0, a6964; RV32I-NEXT: mv a5, a1965; RV32I-NEXT: bnez a6, .LBB11_3966; RV32I-NEXT: j .LBB11_4967; RV32I-NEXT: .LBB11_2:968; RV32I-NEXT: sll a3, a0, a2969; RV32I-NEXT: neg a5, a6970; RV32I-NEXT: srl a5, a0, a5971; RV32I-NEXT: sll a7, a1, a2972; RV32I-NEXT: or a7, a5, a7973; RV32I-NEXT: mv a5, a1974; RV32I-NEXT: beqz a6, .LBB11_4975; RV32I-NEXT: .LBB11_3:976; RV32I-NEXT: mv a5, a7977; RV32I-NEXT: .LBB11_4:978; RV32I-NEXT: neg a2, a2979; RV32I-NEXT: andi a6, a2, 63980; RV32I-NEXT: bltu a6, a4, .LBB11_6981; RV32I-NEXT: # %bb.5:982; RV32I-NEXT: srl a7, a1, a6983; RV32I-NEXT: bnez a6, .LBB11_7984; RV32I-NEXT: j .LBB11_8985; RV32I-NEXT: .LBB11_6:986; RV32I-NEXT: srl a7, a0, a2987; RV32I-NEXT: neg t0, a6988; RV32I-NEXT: sll t0, a1, t0989; RV32I-NEXT: or a7, a7, t0990; RV32I-NEXT: beqz a6, .LBB11_8991; RV32I-NEXT: .LBB11_7:992; RV32I-NEXT: mv a0, a7993; RV32I-NEXT: .LBB11_8:994; RV32I-NEXT: bltu a6, a4, .LBB11_10995; RV32I-NEXT: # %bb.9:996; RV32I-NEXT: li a1, 0997; RV32I-NEXT: j .LBB11_11998; RV32I-NEXT: .LBB11_10:999; RV32I-NEXT: srl a1, a1, a21000; RV32I-NEXT: .LBB11_11:1001; RV32I-NEXT: or a0, a3, a01002; RV32I-NEXT: or a1, a5, a11003; RV32I-NEXT: ret1004;1005; RV64I-LABEL: rotl_64_mask_and_127_and_63:1006; RV64I: # %bb.0:1007; RV64I-NEXT: sll a2, a0, a11008; RV64I-NEXT: neg a1, a11009; RV64I-NEXT: srl a0, a0, a11010; RV64I-NEXT: or a0, a2, a01011; RV64I-NEXT: ret1012;1013; RV32ZBB-LABEL: rotl_64_mask_and_127_and_63:1014; RV32ZBB: # %bb.0:1015; RV32ZBB-NEXT: andi a6, a2, 1271016; RV32ZBB-NEXT: li a4, 321017; RV32ZBB-NEXT: bltu a6, a4, .LBB11_21018; RV32ZBB-NEXT: # %bb.1:1019; RV32ZBB-NEXT: li a3, 01020; RV32ZBB-NEXT: sll a7, a0, a61021; RV32ZBB-NEXT: mv a5, a11022; RV32ZBB-NEXT: bnez a6, .LBB11_31023; RV32ZBB-NEXT: j .LBB11_41024; RV32ZBB-NEXT: .LBB11_2:1025; RV32ZBB-NEXT: sll a3, a0, a21026; RV32ZBB-NEXT: neg a5, a61027; RV32ZBB-NEXT: srl a5, a0, a51028; RV32ZBB-NEXT: sll a7, a1, a21029; RV32ZBB-NEXT: or a7, a5, a71030; RV32ZBB-NEXT: mv a5, a11031; RV32ZBB-NEXT: beqz a6, .LBB11_41032; RV32ZBB-NEXT: .LBB11_3:1033; RV32ZBB-NEXT: mv a5, a71034; RV32ZBB-NEXT: .LBB11_4:1035; RV32ZBB-NEXT: neg a2, a21036; RV32ZBB-NEXT: andi a6, a2, 631037; RV32ZBB-NEXT: bltu a6, a4, .LBB11_61038; RV32ZBB-NEXT: # %bb.5:1039; RV32ZBB-NEXT: srl a7, a1, a61040; RV32ZBB-NEXT: bnez a6, .LBB11_71041; RV32ZBB-NEXT: j .LBB11_81042; RV32ZBB-NEXT: .LBB11_6:1043; RV32ZBB-NEXT: srl a7, a0, a21044; RV32ZBB-NEXT: neg t0, a61045; RV32ZBB-NEXT: sll t0, a1, t01046; RV32ZBB-NEXT: or a7, a7, t01047; RV32ZBB-NEXT: beqz a6, .LBB11_81048; RV32ZBB-NEXT: .LBB11_7:1049; RV32ZBB-NEXT: mv a0, a71050; RV32ZBB-NEXT: .LBB11_8:1051; RV32ZBB-NEXT: bltu a6, a4, .LBB11_101052; RV32ZBB-NEXT: # %bb.9:1053; RV32ZBB-NEXT: li a1, 01054; RV32ZBB-NEXT: j .LBB11_111055; RV32ZBB-NEXT: .LBB11_10:1056; RV32ZBB-NEXT: srl a1, a1, a21057; RV32ZBB-NEXT: .LBB11_11:1058; RV32ZBB-NEXT: or a0, a3, a01059; RV32ZBB-NEXT: or a1, a5, a11060; RV32ZBB-NEXT: ret1061;1062; RV64ZBB-LABEL: rotl_64_mask_and_127_and_63:1063; RV64ZBB: # %bb.0:1064; RV64ZBB-NEXT: sll a2, a0, a11065; RV64ZBB-NEXT: neg a1, a11066; RV64ZBB-NEXT: srl a0, a0, a11067; RV64ZBB-NEXT: or a0, a2, a01068; RV64ZBB-NEXT: ret1069;1070; RV32XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:1071; RV32XTHEADBB: # %bb.0:1072; RV32XTHEADBB-NEXT: andi a6, a2, 1271073; RV32XTHEADBB-NEXT: li a4, 321074; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB11_21075; RV32XTHEADBB-NEXT: # %bb.1:1076; RV32XTHEADBB-NEXT: li a3, 01077; RV32XTHEADBB-NEXT: sll a7, a0, a61078; RV32XTHEADBB-NEXT: mv a5, a11079; RV32XTHEADBB-NEXT: bnez a6, .LBB11_31080; RV32XTHEADBB-NEXT: j .LBB11_41081; RV32XTHEADBB-NEXT: .LBB11_2:1082; RV32XTHEADBB-NEXT: sll a3, a0, a21083; RV32XTHEADBB-NEXT: neg a5, a61084; RV32XTHEADBB-NEXT: srl a5, a0, a51085; RV32XTHEADBB-NEXT: sll a7, a1, a21086; RV32XTHEADBB-NEXT: or a7, a5, a71087; RV32XTHEADBB-NEXT: mv a5, a11088; RV32XTHEADBB-NEXT: beqz a6, .LBB11_41089; RV32XTHEADBB-NEXT: .LBB11_3:1090; RV32XTHEADBB-NEXT: mv a5, a71091; RV32XTHEADBB-NEXT: .LBB11_4:1092; RV32XTHEADBB-NEXT: neg a2, a21093; RV32XTHEADBB-NEXT: andi a6, a2, 631094; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB11_61095; RV32XTHEADBB-NEXT: # %bb.5:1096; RV32XTHEADBB-NEXT: srl a7, a1, a61097; RV32XTHEADBB-NEXT: bnez a6, .LBB11_71098; RV32XTHEADBB-NEXT: j .LBB11_81099; RV32XTHEADBB-NEXT: .LBB11_6:1100; RV32XTHEADBB-NEXT: srl a7, a0, a21101; RV32XTHEADBB-NEXT: neg t0, a61102; RV32XTHEADBB-NEXT: sll t0, a1, t01103; RV32XTHEADBB-NEXT: or a7, a7, t01104; RV32XTHEADBB-NEXT: beqz a6, .LBB11_81105; RV32XTHEADBB-NEXT: .LBB11_7:1106; RV32XTHEADBB-NEXT: mv a0, a71107; RV32XTHEADBB-NEXT: .LBB11_8:1108; RV32XTHEADBB-NEXT: bltu a6, a4, .LBB11_101109; RV32XTHEADBB-NEXT: # %bb.9:1110; RV32XTHEADBB-NEXT: li a1, 01111; RV32XTHEADBB-NEXT: j .LBB11_111112; RV32XTHEADBB-NEXT: .LBB11_10:1113; RV32XTHEADBB-NEXT: srl a1, a1, a21114; RV32XTHEADBB-NEXT: .LBB11_11:1115; RV32XTHEADBB-NEXT: or a0, a3, a01116; RV32XTHEADBB-NEXT: or a1, a5, a11117; RV32XTHEADBB-NEXT: ret1118;1119; RV64XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:1120; RV64XTHEADBB: # %bb.0:1121; RV64XTHEADBB-NEXT: sll a2, a0, a11122; RV64XTHEADBB-NEXT: neg a1, a11123; RV64XTHEADBB-NEXT: srl a0, a0, a11124; RV64XTHEADBB-NEXT: or a0, a2, a01125; RV64XTHEADBB-NEXT: ret1126 %a = and i64 %y, 1271127 %b = shl i64 %x, %a1128 %c = sub i64 0, %y1129 %d = and i64 %c, 631130 %e = lshr i64 %x, %d1131 %f = or i64 %b, %e1132 ret i64 %f1133}1134 1135define i64 @rotl_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {1136; RV32I-LABEL: rotl_64_mask_or_128_or_64:1137; RV32I: # %bb.0:1138; RV32I-NEXT: mv a3, a01139; RV32I-NEXT: ori a2, a2, 1281140; RV32I-NEXT: li a0, 321141; RV32I-NEXT: bltu a2, a0, .LBB12_21142; RV32I-NEXT: # %bb.1:1143; RV32I-NEXT: li a0, 01144; RV32I-NEXT: sll a3, a3, a21145; RV32I-NEXT: bnez a2, .LBB12_31146; RV32I-NEXT: j .LBB12_41147; RV32I-NEXT: .LBB12_2:1148; RV32I-NEXT: sll a0, a3, a21149; RV32I-NEXT: neg a4, a21150; RV32I-NEXT: srl a3, a3, a41151; RV32I-NEXT: sll a4, a1, a21152; RV32I-NEXT: or a3, a3, a41153; RV32I-NEXT: beqz a2, .LBB12_41154; RV32I-NEXT: .LBB12_3:1155; RV32I-NEXT: mv a1, a31156; RV32I-NEXT: .LBB12_4:1157; RV32I-NEXT: ret1158;1159; RV64I-LABEL: rotl_64_mask_or_128_or_64:1160; RV64I: # %bb.0:1161; RV64I-NEXT: ori a1, a1, 1281162; RV64I-NEXT: sll a0, a0, a11163; RV64I-NEXT: ret1164;1165; RV32ZBB-LABEL: rotl_64_mask_or_128_or_64:1166; RV32ZBB: # %bb.0:1167; RV32ZBB-NEXT: mv a3, a01168; RV32ZBB-NEXT: ori a2, a2, 1281169; RV32ZBB-NEXT: li a0, 321170; RV32ZBB-NEXT: bltu a2, a0, .LBB12_21171; RV32ZBB-NEXT: # %bb.1:1172; RV32ZBB-NEXT: li a0, 01173; RV32ZBB-NEXT: sll a3, a3, a21174; RV32ZBB-NEXT: bnez a2, .LBB12_31175; RV32ZBB-NEXT: j .LBB12_41176; RV32ZBB-NEXT: .LBB12_2:1177; RV32ZBB-NEXT: sll a0, a3, a21178; RV32ZBB-NEXT: neg a4, a21179; RV32ZBB-NEXT: srl a3, a3, a41180; RV32ZBB-NEXT: sll a4, a1, a21181; RV32ZBB-NEXT: or a3, a3, a41182; RV32ZBB-NEXT: beqz a2, .LBB12_41183; RV32ZBB-NEXT: .LBB12_3:1184; RV32ZBB-NEXT: mv a1, a31185; RV32ZBB-NEXT: .LBB12_4:1186; RV32ZBB-NEXT: ret1187;1188; RV64ZBB-LABEL: rotl_64_mask_or_128_or_64:1189; RV64ZBB: # %bb.0:1190; RV64ZBB-NEXT: ori a1, a1, 1281191; RV64ZBB-NEXT: sll a0, a0, a11192; RV64ZBB-NEXT: ret1193;1194; RV32XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:1195; RV32XTHEADBB: # %bb.0:1196; RV32XTHEADBB-NEXT: mv a3, a01197; RV32XTHEADBB-NEXT: ori a2, a2, 1281198; RV32XTHEADBB-NEXT: li a0, 321199; RV32XTHEADBB-NEXT: bltu a2, a0, .LBB12_21200; RV32XTHEADBB-NEXT: # %bb.1:1201; RV32XTHEADBB-NEXT: li a0, 01202; RV32XTHEADBB-NEXT: sll a3, a3, a21203; RV32XTHEADBB-NEXT: bnez a2, .LBB12_31204; RV32XTHEADBB-NEXT: j .LBB12_41205; RV32XTHEADBB-NEXT: .LBB12_2:1206; RV32XTHEADBB-NEXT: sll a0, a3, a21207; RV32XTHEADBB-NEXT: neg a4, a21208; RV32XTHEADBB-NEXT: srl a3, a3, a41209; RV32XTHEADBB-NEXT: sll a4, a1, a21210; RV32XTHEADBB-NEXT: or a3, a3, a41211; RV32XTHEADBB-NEXT: beqz a2, .LBB12_41212; RV32XTHEADBB-NEXT: .LBB12_3:1213; RV32XTHEADBB-NEXT: mv a1, a31214; RV32XTHEADBB-NEXT: .LBB12_4:1215; RV32XTHEADBB-NEXT: ret1216;1217; RV64XTHEADBB-LABEL: rotl_64_mask_or_128_or_64:1218; RV64XTHEADBB: # %bb.0:1219; RV64XTHEADBB-NEXT: ori a1, a1, 1281220; RV64XTHEADBB-NEXT: sll a0, a0, a11221; RV64XTHEADBB-NEXT: ret1222 %a = or i64 %y, 1281223 %b = shl i64 %x, %a1224 %c = sub i64 0, %y1225 %d = or i64 %c, 641226 %e = lshr i64 %x, %d1227 %f = or i64 %b, %e1228 ret i64 %f1229}1230 1231define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {1232; RV32I-LABEL: rotr_64_mask:1233; RV32I: # %bb.0:1234; RV32I-NEXT: li a4, 321235; RV32I-NEXT: bltu a2, a4, .LBB13_21236; RV32I-NEXT: # %bb.1:1237; RV32I-NEXT: srl a5, a1, a21238; RV32I-NEXT: j .LBB13_31239; RV32I-NEXT: .LBB13_2:1240; RV32I-NEXT: srl a3, a0, a21241; RV32I-NEXT: neg a5, a21242; RV32I-NEXT: sll a5, a1, a51243; RV32I-NEXT: or a5, a3, a51244; RV32I-NEXT: .LBB13_3:1245; RV32I-NEXT: neg a6, a21246; RV32I-NEXT: mv a3, a01247; RV32I-NEXT: beqz a2, .LBB13_51248; RV32I-NEXT: # %bb.4:1249; RV32I-NEXT: mv a3, a51250; RV32I-NEXT: .LBB13_5:1251; RV32I-NEXT: andi a5, a6, 631252; RV32I-NEXT: bltu a2, a4, .LBB13_81253; RV32I-NEXT: # %bb.6:1254; RV32I-NEXT: li a2, 01255; RV32I-NEXT: bgeu a5, a4, .LBB13_91256; RV32I-NEXT: .LBB13_7:1257; RV32I-NEXT: sll a4, a0, a61258; RV32I-NEXT: neg a7, a51259; RV32I-NEXT: srl a0, a0, a71260; RV32I-NEXT: sll a6, a1, a61261; RV32I-NEXT: or a0, a0, a61262; RV32I-NEXT: bnez a5, .LBB13_101263; RV32I-NEXT: j .LBB13_111264; RV32I-NEXT: .LBB13_8:1265; RV32I-NEXT: srl a2, a1, a21266; RV32I-NEXT: bltu a5, a4, .LBB13_71267; RV32I-NEXT: .LBB13_9:1268; RV32I-NEXT: li a4, 01269; RV32I-NEXT: sll a0, a0, a51270; RV32I-NEXT: beqz a5, .LBB13_111271; RV32I-NEXT: .LBB13_10:1272; RV32I-NEXT: mv a1, a01273; RV32I-NEXT: .LBB13_11:1274; RV32I-NEXT: or a0, a3, a41275; RV32I-NEXT: or a1, a2, a11276; RV32I-NEXT: ret1277;1278; RV64I-LABEL: rotr_64_mask:1279; RV64I: # %bb.0:1280; RV64I-NEXT: neg a2, a11281; RV64I-NEXT: srl a1, a0, a11282; RV64I-NEXT: sll a0, a0, a21283; RV64I-NEXT: or a0, a1, a01284; RV64I-NEXT: ret1285;1286; RV32ZBB-LABEL: rotr_64_mask:1287; RV32ZBB: # %bb.0:1288; RV32ZBB-NEXT: li a4, 321289; RV32ZBB-NEXT: bltu a2, a4, .LBB13_21290; RV32ZBB-NEXT: # %bb.1:1291; RV32ZBB-NEXT: srl a5, a1, a21292; RV32ZBB-NEXT: j .LBB13_31293; RV32ZBB-NEXT: .LBB13_2:1294; RV32ZBB-NEXT: srl a3, a0, a21295; RV32ZBB-NEXT: neg a5, a21296; RV32ZBB-NEXT: sll a5, a1, a51297; RV32ZBB-NEXT: or a5, a3, a51298; RV32ZBB-NEXT: .LBB13_3:1299; RV32ZBB-NEXT: neg a6, a21300; RV32ZBB-NEXT: mv a3, a01301; RV32ZBB-NEXT: beqz a2, .LBB13_51302; RV32ZBB-NEXT: # %bb.4:1303; RV32ZBB-NEXT: mv a3, a51304; RV32ZBB-NEXT: .LBB13_5:1305; RV32ZBB-NEXT: andi a5, a6, 631306; RV32ZBB-NEXT: bltu a2, a4, .LBB13_81307; RV32ZBB-NEXT: # %bb.6:1308; RV32ZBB-NEXT: li a2, 01309; RV32ZBB-NEXT: bgeu a5, a4, .LBB13_91310; RV32ZBB-NEXT: .LBB13_7:1311; RV32ZBB-NEXT: sll a4, a0, a61312; RV32ZBB-NEXT: neg a7, a51313; RV32ZBB-NEXT: srl a0, a0, a71314; RV32ZBB-NEXT: sll a6, a1, a61315; RV32ZBB-NEXT: or a0, a0, a61316; RV32ZBB-NEXT: bnez a5, .LBB13_101317; RV32ZBB-NEXT: j .LBB13_111318; RV32ZBB-NEXT: .LBB13_8:1319; RV32ZBB-NEXT: srl a2, a1, a21320; RV32ZBB-NEXT: bltu a5, a4, .LBB13_71321; RV32ZBB-NEXT: .LBB13_9:1322; RV32ZBB-NEXT: li a4, 01323; RV32ZBB-NEXT: sll a0, a0, a51324; RV32ZBB-NEXT: beqz a5, .LBB13_111325; RV32ZBB-NEXT: .LBB13_10:1326; RV32ZBB-NEXT: mv a1, a01327; RV32ZBB-NEXT: .LBB13_11:1328; RV32ZBB-NEXT: or a0, a3, a41329; RV32ZBB-NEXT: or a1, a2, a11330; RV32ZBB-NEXT: ret1331;1332; RV64ZBB-LABEL: rotr_64_mask:1333; RV64ZBB: # %bb.0:1334; RV64ZBB-NEXT: neg a2, a11335; RV64ZBB-NEXT: srl a1, a0, a11336; RV64ZBB-NEXT: sll a0, a0, a21337; RV64ZBB-NEXT: or a0, a1, a01338; RV64ZBB-NEXT: ret1339;1340; RV32XTHEADBB-LABEL: rotr_64_mask:1341; RV32XTHEADBB: # %bb.0:1342; RV32XTHEADBB-NEXT: li a4, 321343; RV32XTHEADBB-NEXT: bltu a2, a4, .LBB13_21344; RV32XTHEADBB-NEXT: # %bb.1:1345; RV32XTHEADBB-NEXT: srl a5, a1, a21346; RV32XTHEADBB-NEXT: j .LBB13_31347; RV32XTHEADBB-NEXT: .LBB13_2:1348; RV32XTHEADBB-NEXT: srl a3, a0, a21349; RV32XTHEADBB-NEXT: neg a5, a21350; RV32XTHEADBB-NEXT: sll a5, a1, a51351; RV32XTHEADBB-NEXT: or a5, a3, a51352; RV32XTHEADBB-NEXT: .LBB13_3:1353; RV32XTHEADBB-NEXT: neg a6, a21354; RV32XTHEADBB-NEXT: mv a3, a01355; RV32XTHEADBB-NEXT: beqz a2, .LBB13_51356; RV32XTHEADBB-NEXT: # %bb.4:1357; RV32XTHEADBB-NEXT: mv a3, a51358; RV32XTHEADBB-NEXT: .LBB13_5:1359; RV32XTHEADBB-NEXT: andi a5, a6, 631360; RV32XTHEADBB-NEXT: bltu a2, a4, .LBB13_81361; RV32XTHEADBB-NEXT: # %bb.6:1362; RV32XTHEADBB-NEXT: li a2, 01363; RV32XTHEADBB-NEXT: bgeu a5, a4, .LBB13_91364; RV32XTHEADBB-NEXT: .LBB13_7:1365; RV32XTHEADBB-NEXT: sll a4, a0, a61366; RV32XTHEADBB-NEXT: neg a7, a51367; RV32XTHEADBB-NEXT: srl a0, a0, a71368; RV32XTHEADBB-NEXT: sll a6, a1, a61369; RV32XTHEADBB-NEXT: or a0, a0, a61370; RV32XTHEADBB-NEXT: bnez a5, .LBB13_101371; RV32XTHEADBB-NEXT: j .LBB13_111372; RV32XTHEADBB-NEXT: .LBB13_8:1373; RV32XTHEADBB-NEXT: srl a2, a1, a21374; RV32XTHEADBB-NEXT: bltu a5, a4, .LBB13_71375; RV32XTHEADBB-NEXT: .LBB13_9:1376; RV32XTHEADBB-NEXT: li a4, 01377; RV32XTHEADBB-NEXT: sll a0, a0, a51378; RV32XTHEADBB-NEXT: beqz a5, .LBB13_111379; RV32XTHEADBB-NEXT: .LBB13_10:1380; RV32XTHEADBB-NEXT: mv a1, a01381; RV32XTHEADBB-NEXT: .LBB13_11:1382; RV32XTHEADBB-NEXT: or a0, a3, a41383; RV32XTHEADBB-NEXT: or a1, a2, a11384; RV32XTHEADBB-NEXT: ret1385;1386; RV64XTHEADBB-LABEL: rotr_64_mask:1387; RV64XTHEADBB: # %bb.0:1388; RV64XTHEADBB-NEXT: neg a2, a11389; RV64XTHEADBB-NEXT: srl a1, a0, a11390; RV64XTHEADBB-NEXT: sll a0, a0, a21391; RV64XTHEADBB-NEXT: or a0, a1, a01392; RV64XTHEADBB-NEXT: ret1393 %z = sub i64 0, %y1394 %and = and i64 %z, 631395 %b = lshr i64 %x, %y1396 %c = shl i64 %x, %and1397 %d = or i64 %b, %c1398 ret i64 %d1399}1400 1401define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {1402; RV32I-LABEL: rotr_64_mask_and_127_and_63:1403; RV32I: # %bb.0:1404; RV32I-NEXT: andi a4, a2, 1271405; RV32I-NEXT: li a5, 321406; RV32I-NEXT: bltu a4, a5, .LBB14_21407; RV32I-NEXT: # %bb.1:1408; RV32I-NEXT: srl a6, a1, a41409; RV32I-NEXT: mv a3, a01410; RV32I-NEXT: bnez a4, .LBB14_31411; RV32I-NEXT: j .LBB14_41412; RV32I-NEXT: .LBB14_2:1413; RV32I-NEXT: srl a3, a0, a21414; RV32I-NEXT: neg a6, a41415; RV32I-NEXT: sll a6, a1, a61416; RV32I-NEXT: or a6, a3, a61417; RV32I-NEXT: mv a3, a01418; RV32I-NEXT: beqz a4, .LBB14_41419; RV32I-NEXT: .LBB14_3:1420; RV32I-NEXT: mv a3, a61421; RV32I-NEXT: .LBB14_4:1422; RV32I-NEXT: bltu a4, a5, .LBB14_61423; RV32I-NEXT: # %bb.5:1424; RV32I-NEXT: li a4, 01425; RV32I-NEXT: j .LBB14_71426; RV32I-NEXT: .LBB14_6:1427; RV32I-NEXT: srl a4, a1, a21428; RV32I-NEXT: .LBB14_7:1429; RV32I-NEXT: neg a7, a21430; RV32I-NEXT: andi a6, a7, 631431; RV32I-NEXT: bltu a6, a5, .LBB14_91432; RV32I-NEXT: # %bb.8:1433; RV32I-NEXT: li a2, 01434; RV32I-NEXT: sll a0, a0, a61435; RV32I-NEXT: bnez a6, .LBB14_101436; RV32I-NEXT: j .LBB14_111437; RV32I-NEXT: .LBB14_9:1438; RV32I-NEXT: sll a2, a0, a71439; RV32I-NEXT: neg a5, a61440; RV32I-NEXT: srl a0, a0, a51441; RV32I-NEXT: sll a5, a1, a71442; RV32I-NEXT: or a0, a0, a51443; RV32I-NEXT: beqz a6, .LBB14_111444; RV32I-NEXT: .LBB14_10:1445; RV32I-NEXT: mv a1, a01446; RV32I-NEXT: .LBB14_11:1447; RV32I-NEXT: or a0, a3, a21448; RV32I-NEXT: or a1, a4, a11449; RV32I-NEXT: ret1450;1451; RV64I-LABEL: rotr_64_mask_and_127_and_63:1452; RV64I: # %bb.0:1453; RV64I-NEXT: srl a2, a0, a11454; RV64I-NEXT: neg a1, a11455; RV64I-NEXT: sll a0, a0, a11456; RV64I-NEXT: or a0, a2, a01457; RV64I-NEXT: ret1458;1459; RV32ZBB-LABEL: rotr_64_mask_and_127_and_63:1460; RV32ZBB: # %bb.0:1461; RV32ZBB-NEXT: andi a4, a2, 1271462; RV32ZBB-NEXT: li a5, 321463; RV32ZBB-NEXT: bltu a4, a5, .LBB14_21464; RV32ZBB-NEXT: # %bb.1:1465; RV32ZBB-NEXT: srl a6, a1, a41466; RV32ZBB-NEXT: mv a3, a01467; RV32ZBB-NEXT: bnez a4, .LBB14_31468; RV32ZBB-NEXT: j .LBB14_41469; RV32ZBB-NEXT: .LBB14_2:1470; RV32ZBB-NEXT: srl a3, a0, a21471; RV32ZBB-NEXT: neg a6, a41472; RV32ZBB-NEXT: sll a6, a1, a61473; RV32ZBB-NEXT: or a6, a3, a61474; RV32ZBB-NEXT: mv a3, a01475; RV32ZBB-NEXT: beqz a4, .LBB14_41476; RV32ZBB-NEXT: .LBB14_3:1477; RV32ZBB-NEXT: mv a3, a61478; RV32ZBB-NEXT: .LBB14_4:1479; RV32ZBB-NEXT: bltu a4, a5, .LBB14_61480; RV32ZBB-NEXT: # %bb.5:1481; RV32ZBB-NEXT: li a4, 01482; RV32ZBB-NEXT: j .LBB14_71483; RV32ZBB-NEXT: .LBB14_6:1484; RV32ZBB-NEXT: srl a4, a1, a21485; RV32ZBB-NEXT: .LBB14_7:1486; RV32ZBB-NEXT: neg a7, a21487; RV32ZBB-NEXT: andi a6, a7, 631488; RV32ZBB-NEXT: bltu a6, a5, .LBB14_91489; RV32ZBB-NEXT: # %bb.8:1490; RV32ZBB-NEXT: li a2, 01491; RV32ZBB-NEXT: sll a0, a0, a61492; RV32ZBB-NEXT: bnez a6, .LBB14_101493; RV32ZBB-NEXT: j .LBB14_111494; RV32ZBB-NEXT: .LBB14_9:1495; RV32ZBB-NEXT: sll a2, a0, a71496; RV32ZBB-NEXT: neg a5, a61497; RV32ZBB-NEXT: srl a0, a0, a51498; RV32ZBB-NEXT: sll a5, a1, a71499; RV32ZBB-NEXT: or a0, a0, a51500; RV32ZBB-NEXT: beqz a6, .LBB14_111501; RV32ZBB-NEXT: .LBB14_10:1502; RV32ZBB-NEXT: mv a1, a01503; RV32ZBB-NEXT: .LBB14_11:1504; RV32ZBB-NEXT: or a0, a3, a21505; RV32ZBB-NEXT: or a1, a4, a11506; RV32ZBB-NEXT: ret1507;1508; RV64ZBB-LABEL: rotr_64_mask_and_127_and_63:1509; RV64ZBB: # %bb.0:1510; RV64ZBB-NEXT: srl a2, a0, a11511; RV64ZBB-NEXT: neg a1, a11512; RV64ZBB-NEXT: sll a0, a0, a11513; RV64ZBB-NEXT: or a0, a2, a01514; RV64ZBB-NEXT: ret1515;1516; RV32XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:1517; RV32XTHEADBB: # %bb.0:1518; RV32XTHEADBB-NEXT: andi a4, a2, 1271519; RV32XTHEADBB-NEXT: li a5, 321520; RV32XTHEADBB-NEXT: bltu a4, a5, .LBB14_21521; RV32XTHEADBB-NEXT: # %bb.1:1522; RV32XTHEADBB-NEXT: srl a6, a1, a41523; RV32XTHEADBB-NEXT: mv a3, a01524; RV32XTHEADBB-NEXT: bnez a4, .LBB14_31525; RV32XTHEADBB-NEXT: j .LBB14_41526; RV32XTHEADBB-NEXT: .LBB14_2:1527; RV32XTHEADBB-NEXT: srl a3, a0, a21528; RV32XTHEADBB-NEXT: neg a6, a41529; RV32XTHEADBB-NEXT: sll a6, a1, a61530; RV32XTHEADBB-NEXT: or a6, a3, a61531; RV32XTHEADBB-NEXT: mv a3, a01532; RV32XTHEADBB-NEXT: beqz a4, .LBB14_41533; RV32XTHEADBB-NEXT: .LBB14_3:1534; RV32XTHEADBB-NEXT: mv a3, a61535; RV32XTHEADBB-NEXT: .LBB14_4:1536; RV32XTHEADBB-NEXT: bltu a4, a5, .LBB14_61537; RV32XTHEADBB-NEXT: # %bb.5:1538; RV32XTHEADBB-NEXT: li a4, 01539; RV32XTHEADBB-NEXT: j .LBB14_71540; RV32XTHEADBB-NEXT: .LBB14_6:1541; RV32XTHEADBB-NEXT: srl a4, a1, a21542; RV32XTHEADBB-NEXT: .LBB14_7:1543; RV32XTHEADBB-NEXT: neg a7, a21544; RV32XTHEADBB-NEXT: andi a6, a7, 631545; RV32XTHEADBB-NEXT: bltu a6, a5, .LBB14_91546; RV32XTHEADBB-NEXT: # %bb.8:1547; RV32XTHEADBB-NEXT: li a2, 01548; RV32XTHEADBB-NEXT: sll a0, a0, a61549; RV32XTHEADBB-NEXT: bnez a6, .LBB14_101550; RV32XTHEADBB-NEXT: j .LBB14_111551; RV32XTHEADBB-NEXT: .LBB14_9:1552; RV32XTHEADBB-NEXT: sll a2, a0, a71553; RV32XTHEADBB-NEXT: neg a5, a61554; RV32XTHEADBB-NEXT: srl a0, a0, a51555; RV32XTHEADBB-NEXT: sll a5, a1, a71556; RV32XTHEADBB-NEXT: or a0, a0, a51557; RV32XTHEADBB-NEXT: beqz a6, .LBB14_111558; RV32XTHEADBB-NEXT: .LBB14_10:1559; RV32XTHEADBB-NEXT: mv a1, a01560; RV32XTHEADBB-NEXT: .LBB14_11:1561; RV32XTHEADBB-NEXT: or a0, a3, a21562; RV32XTHEADBB-NEXT: or a1, a4, a11563; RV32XTHEADBB-NEXT: ret1564;1565; RV64XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:1566; RV64XTHEADBB: # %bb.0:1567; RV64XTHEADBB-NEXT: srl a2, a0, a11568; RV64XTHEADBB-NEXT: neg a1, a11569; RV64XTHEADBB-NEXT: sll a0, a0, a11570; RV64XTHEADBB-NEXT: or a0, a2, a01571; RV64XTHEADBB-NEXT: ret1572 %a = and i64 %y, 1271573 %b = lshr i64 %x, %a1574 %c = sub i64 0, %y1575 %d = and i64 %c, 631576 %e = shl i64 %x, %d1577 %f = or i64 %b, %e1578 ret i64 %f1579}1580 1581define i64 @rotr_64_mask_or_128_or_64(i64 %x, i64 %y) nounwind {1582; RV32I-LABEL: rotr_64_mask_or_128_or_64:1583; RV32I: # %bb.0:1584; RV32I-NEXT: ori a2, a2, 1281585; RV32I-NEXT: li a3, 321586; RV32I-NEXT: bltu a2, a3, .LBB15_21587; RV32I-NEXT: # %bb.1:1588; RV32I-NEXT: srl a4, a1, a21589; RV32I-NEXT: bnez a2, .LBB15_31590; RV32I-NEXT: j .LBB15_41591; RV32I-NEXT: .LBB15_2:1592; RV32I-NEXT: srl a4, a0, a21593; RV32I-NEXT: neg a5, a21594; RV32I-NEXT: sll a5, a1, a51595; RV32I-NEXT: or a4, a4, a51596; RV32I-NEXT: beqz a2, .LBB15_41597; RV32I-NEXT: .LBB15_3:1598; RV32I-NEXT: mv a0, a41599; RV32I-NEXT: .LBB15_4:1600; RV32I-NEXT: bltu a2, a3, .LBB15_61601; RV32I-NEXT: # %bb.5:1602; RV32I-NEXT: li a1, 01603; RV32I-NEXT: ret1604; RV32I-NEXT: .LBB15_6:1605; RV32I-NEXT: srl a1, a1, a21606; RV32I-NEXT: ret1607;1608; RV64I-LABEL: rotr_64_mask_or_128_or_64:1609; RV64I: # %bb.0:1610; RV64I-NEXT: ori a1, a1, 1281611; RV64I-NEXT: srl a0, a0, a11612; RV64I-NEXT: ret1613;1614; RV32ZBB-LABEL: rotr_64_mask_or_128_or_64:1615; RV32ZBB: # %bb.0:1616; RV32ZBB-NEXT: ori a2, a2, 1281617; RV32ZBB-NEXT: li a3, 321618; RV32ZBB-NEXT: bltu a2, a3, .LBB15_21619; RV32ZBB-NEXT: # %bb.1:1620; RV32ZBB-NEXT: srl a4, a1, a21621; RV32ZBB-NEXT: bnez a2, .LBB15_31622; RV32ZBB-NEXT: j .LBB15_41623; RV32ZBB-NEXT: .LBB15_2:1624; RV32ZBB-NEXT: srl a4, a0, a21625; RV32ZBB-NEXT: neg a5, a21626; RV32ZBB-NEXT: sll a5, a1, a51627; RV32ZBB-NEXT: or a4, a4, a51628; RV32ZBB-NEXT: beqz a2, .LBB15_41629; RV32ZBB-NEXT: .LBB15_3:1630; RV32ZBB-NEXT: mv a0, a41631; RV32ZBB-NEXT: .LBB15_4:1632; RV32ZBB-NEXT: bltu a2, a3, .LBB15_61633; RV32ZBB-NEXT: # %bb.5:1634; RV32ZBB-NEXT: li a1, 01635; RV32ZBB-NEXT: ret1636; RV32ZBB-NEXT: .LBB15_6:1637; RV32ZBB-NEXT: srl a1, a1, a21638; RV32ZBB-NEXT: ret1639;1640; RV64ZBB-LABEL: rotr_64_mask_or_128_or_64:1641; RV64ZBB: # %bb.0:1642; RV64ZBB-NEXT: ori a1, a1, 1281643; RV64ZBB-NEXT: srl a0, a0, a11644; RV64ZBB-NEXT: ret1645;1646; RV32XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:1647; RV32XTHEADBB: # %bb.0:1648; RV32XTHEADBB-NEXT: ori a2, a2, 1281649; RV32XTHEADBB-NEXT: li a3, 321650; RV32XTHEADBB-NEXT: bltu a2, a3, .LBB15_21651; RV32XTHEADBB-NEXT: # %bb.1:1652; RV32XTHEADBB-NEXT: srl a4, a1, a21653; RV32XTHEADBB-NEXT: bnez a2, .LBB15_31654; RV32XTHEADBB-NEXT: j .LBB15_41655; RV32XTHEADBB-NEXT: .LBB15_2:1656; RV32XTHEADBB-NEXT: srl a4, a0, a21657; RV32XTHEADBB-NEXT: neg a5, a21658; RV32XTHEADBB-NEXT: sll a5, a1, a51659; RV32XTHEADBB-NEXT: or a4, a4, a51660; RV32XTHEADBB-NEXT: beqz a2, .LBB15_41661; RV32XTHEADBB-NEXT: .LBB15_3:1662; RV32XTHEADBB-NEXT: mv a0, a41663; RV32XTHEADBB-NEXT: .LBB15_4:1664; RV32XTHEADBB-NEXT: bltu a2, a3, .LBB15_61665; RV32XTHEADBB-NEXT: # %bb.5:1666; RV32XTHEADBB-NEXT: li a1, 01667; RV32XTHEADBB-NEXT: ret1668; RV32XTHEADBB-NEXT: .LBB15_6:1669; RV32XTHEADBB-NEXT: srl a1, a1, a21670; RV32XTHEADBB-NEXT: ret1671;1672; RV64XTHEADBB-LABEL: rotr_64_mask_or_128_or_64:1673; RV64XTHEADBB: # %bb.0:1674; RV64XTHEADBB-NEXT: ori a1, a1, 1281675; RV64XTHEADBB-NEXT: srl a0, a0, a11676; RV64XTHEADBB-NEXT: ret1677 %a = or i64 %y, 1281678 %b = lshr i64 %x, %a1679 %c = sub i64 0, %y1680 %d = or i64 %c, 641681 %e = shl i64 %x, %d1682 %f = or i64 %b, %e1683 ret i64 %f1684}1685 1686; Test that we're able to remove a mask on the rotate amount that has more than1687; one use.1688define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {1689; RV32I-LABEL: rotl_32_mask_shared:1690; RV32I: # %bb.0:1691; RV32I-NEXT: andi a3, a2, 311692; RV32I-NEXT: sll a4, a0, a21693; RV32I-NEXT: neg a3, a31694; RV32I-NEXT: srl a0, a0, a31695; RV32I-NEXT: or a0, a4, a01696; RV32I-NEXT: sll a1, a1, a21697; RV32I-NEXT: add a0, a0, a11698; RV32I-NEXT: ret1699;1700; RV64I-LABEL: rotl_32_mask_shared:1701; RV64I: # %bb.0:1702; RV64I-NEXT: andi a3, a2, 311703; RV64I-NEXT: sllw a4, a0, a21704; RV64I-NEXT: neg a3, a31705; RV64I-NEXT: srlw a0, a0, a31706; RV64I-NEXT: or a0, a4, a01707; RV64I-NEXT: sllw a1, a1, a21708; RV64I-NEXT: addw a0, a0, a11709; RV64I-NEXT: ret1710;1711; RV32ZBB-LABEL: rotl_32_mask_shared:1712; RV32ZBB: # %bb.0:1713; RV32ZBB-NEXT: rol a0, a0, a21714; RV32ZBB-NEXT: sll a1, a1, a21715; RV32ZBB-NEXT: add a0, a0, a11716; RV32ZBB-NEXT: ret1717;1718; RV64ZBB-LABEL: rotl_32_mask_shared:1719; RV64ZBB: # %bb.0:1720; RV64ZBB-NEXT: rolw a0, a0, a21721; RV64ZBB-NEXT: sllw a1, a1, a21722; RV64ZBB-NEXT: addw a0, a0, a11723; RV64ZBB-NEXT: ret1724;1725; RV32XTHEADBB-LABEL: rotl_32_mask_shared:1726; RV32XTHEADBB: # %bb.0:1727; RV32XTHEADBB-NEXT: andi a3, a2, 311728; RV32XTHEADBB-NEXT: sll a4, a0, a21729; RV32XTHEADBB-NEXT: neg a3, a31730; RV32XTHEADBB-NEXT: srl a0, a0, a31731; RV32XTHEADBB-NEXT: or a0, a4, a01732; RV32XTHEADBB-NEXT: sll a1, a1, a21733; RV32XTHEADBB-NEXT: add a0, a0, a11734; RV32XTHEADBB-NEXT: ret1735;1736; RV64XTHEADBB-LABEL: rotl_32_mask_shared:1737; RV64XTHEADBB: # %bb.0:1738; RV64XTHEADBB-NEXT: andi a3, a2, 311739; RV64XTHEADBB-NEXT: sllw a4, a0, a21740; RV64XTHEADBB-NEXT: neg a3, a31741; RV64XTHEADBB-NEXT: srlw a0, a0, a31742; RV64XTHEADBB-NEXT: or a0, a4, a01743; RV64XTHEADBB-NEXT: sllw a1, a1, a21744; RV64XTHEADBB-NEXT: addw a0, a0, a11745; RV64XTHEADBB-NEXT: ret1746 %maskedamt = and i32 %amt, 311747 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)1748 %2 = shl i32 %b, %maskedamt1749 %3 = add i32 %1, %21750 ret i32 %31751}1752 1753define signext i64 @rotl_64_mask_shared(i64 signext %a, i64 signext %b, i64 signext %amt) nounwind {1754; RV32I-LABEL: rotl_64_mask_shared:1755; RV32I: # %bb.0:1756; RV32I-NEXT: andi a5, a4, 631757; RV32I-NEXT: li t0, 321758; RV32I-NEXT: neg a7, a51759; RV32I-NEXT: bltu a5, t0, .LBB17_21760; RV32I-NEXT: # %bb.1:1761; RV32I-NEXT: li a6, 01762; RV32I-NEXT: sll t3, a0, a51763; RV32I-NEXT: j .LBB17_31764; RV32I-NEXT: .LBB17_2:1765; RV32I-NEXT: sll a6, a0, a41766; RV32I-NEXT: srl t1, a0, a71767; RV32I-NEXT: sll t2, a1, a41768; RV32I-NEXT: or t3, t1, t21769; RV32I-NEXT: .LBB17_3:1770; RV32I-NEXT: neg t2, a51771; RV32I-NEXT: mv t1, a11772; RV32I-NEXT: beqz a5, .LBB17_51773; RV32I-NEXT: # %bb.4:1774; RV32I-NEXT: mv t1, t31775; RV32I-NEXT: .LBB17_5:1776; RV32I-NEXT: andi t3, t2, 631777; RV32I-NEXT: bltu t3, t0, .LBB17_71778; RV32I-NEXT: # %bb.6:1779; RV32I-NEXT: srl t4, a1, t31780; RV32I-NEXT: bnez t3, .LBB17_81781; RV32I-NEXT: j .LBB17_91782; RV32I-NEXT: .LBB17_7:1783; RV32I-NEXT: srl t4, a0, t21784; RV32I-NEXT: neg t5, t31785; RV32I-NEXT: sll t5, a1, t51786; RV32I-NEXT: or t4, t4, t51787; RV32I-NEXT: beqz t3, .LBB17_91788; RV32I-NEXT: .LBB17_8:1789; RV32I-NEXT: mv a0, t41790; RV32I-NEXT: .LBB17_9:1791; RV32I-NEXT: bltu t3, t0, .LBB17_121792; RV32I-NEXT: # %bb.10:1793; RV32I-NEXT: li a1, 01794; RV32I-NEXT: bgeu a5, t0, .LBB17_131795; RV32I-NEXT: .LBB17_11:1796; RV32I-NEXT: sll t0, a2, a41797; RV32I-NEXT: srl a2, a2, a71798; RV32I-NEXT: sll a4, a3, a41799; RV32I-NEXT: or a2, a2, a41800; RV32I-NEXT: j .LBB17_141801; RV32I-NEXT: .LBB17_12:1802; RV32I-NEXT: srl a1, a1, t21803; RV32I-NEXT: bltu a5, t0, .LBB17_111804; RV32I-NEXT: .LBB17_13:1805; RV32I-NEXT: li t0, 01806; RV32I-NEXT: sll a2, a2, a51807; RV32I-NEXT: .LBB17_14:1808; RV32I-NEXT: or a0, a6, a01809; RV32I-NEXT: or a1, t1, a11810; RV32I-NEXT: beqz a5, .LBB17_161811; RV32I-NEXT: # %bb.15:1812; RV32I-NEXT: mv a3, a21813; RV32I-NEXT: .LBB17_16:1814; RV32I-NEXT: add a0, a0, t01815; RV32I-NEXT: sltu a2, a0, t01816; RV32I-NEXT: add a1, a1, a31817; RV32I-NEXT: add a1, a1, a21818; RV32I-NEXT: ret1819;1820; RV64I-LABEL: rotl_64_mask_shared:1821; RV64I: # %bb.0:1822; RV64I-NEXT: andi a3, a2, 631823; RV64I-NEXT: sll a4, a0, a21824; RV64I-NEXT: neg a3, a31825; RV64I-NEXT: srl a0, a0, a31826; RV64I-NEXT: or a0, a4, a01827; RV64I-NEXT: sll a1, a1, a21828; RV64I-NEXT: add a0, a0, a11829; RV64I-NEXT: ret1830;1831; RV32ZBB-LABEL: rotl_64_mask_shared:1832; RV32ZBB: # %bb.0:1833; RV32ZBB-NEXT: andi a5, a4, 631834; RV32ZBB-NEXT: li t0, 321835; RV32ZBB-NEXT: neg a7, a51836; RV32ZBB-NEXT: bltu a5, t0, .LBB17_21837; RV32ZBB-NEXT: # %bb.1:1838; RV32ZBB-NEXT: li a6, 01839; RV32ZBB-NEXT: sll t3, a0, a51840; RV32ZBB-NEXT: j .LBB17_31841; RV32ZBB-NEXT: .LBB17_2:1842; RV32ZBB-NEXT: sll a6, a0, a41843; RV32ZBB-NEXT: srl t1, a0, a71844; RV32ZBB-NEXT: sll t2, a1, a41845; RV32ZBB-NEXT: or t3, t1, t21846; RV32ZBB-NEXT: .LBB17_3:1847; RV32ZBB-NEXT: neg t2, a51848; RV32ZBB-NEXT: mv t1, a11849; RV32ZBB-NEXT: beqz a5, .LBB17_51850; RV32ZBB-NEXT: # %bb.4:1851; RV32ZBB-NEXT: mv t1, t31852; RV32ZBB-NEXT: .LBB17_5:1853; RV32ZBB-NEXT: andi t3, t2, 631854; RV32ZBB-NEXT: bltu t3, t0, .LBB17_71855; RV32ZBB-NEXT: # %bb.6:1856; RV32ZBB-NEXT: srl t4, a1, t31857; RV32ZBB-NEXT: bnez t3, .LBB17_81858; RV32ZBB-NEXT: j .LBB17_91859; RV32ZBB-NEXT: .LBB17_7:1860; RV32ZBB-NEXT: srl t4, a0, t21861; RV32ZBB-NEXT: neg t5, t31862; RV32ZBB-NEXT: sll t5, a1, t51863; RV32ZBB-NEXT: or t4, t4, t51864; RV32ZBB-NEXT: beqz t3, .LBB17_91865; RV32ZBB-NEXT: .LBB17_8:1866; RV32ZBB-NEXT: mv a0, t41867; RV32ZBB-NEXT: .LBB17_9:1868; RV32ZBB-NEXT: bltu t3, t0, .LBB17_121869; RV32ZBB-NEXT: # %bb.10:1870; RV32ZBB-NEXT: li a1, 01871; RV32ZBB-NEXT: bgeu a5, t0, .LBB17_131872; RV32ZBB-NEXT: .LBB17_11:1873; RV32ZBB-NEXT: sll t0, a2, a41874; RV32ZBB-NEXT: srl a2, a2, a71875; RV32ZBB-NEXT: sll a4, a3, a41876; RV32ZBB-NEXT: or a2, a2, a41877; RV32ZBB-NEXT: j .LBB17_141878; RV32ZBB-NEXT: .LBB17_12:1879; RV32ZBB-NEXT: srl a1, a1, t21880; RV32ZBB-NEXT: bltu a5, t0, .LBB17_111881; RV32ZBB-NEXT: .LBB17_13:1882; RV32ZBB-NEXT: li t0, 01883; RV32ZBB-NEXT: sll a2, a2, a51884; RV32ZBB-NEXT: .LBB17_14:1885; RV32ZBB-NEXT: or a0, a6, a01886; RV32ZBB-NEXT: or a1, t1, a11887; RV32ZBB-NEXT: beqz a5, .LBB17_161888; RV32ZBB-NEXT: # %bb.15:1889; RV32ZBB-NEXT: mv a3, a21890; RV32ZBB-NEXT: .LBB17_16:1891; RV32ZBB-NEXT: add a0, a0, t01892; RV32ZBB-NEXT: sltu a2, a0, t01893; RV32ZBB-NEXT: add a1, a1, a31894; RV32ZBB-NEXT: add a1, a1, a21895; RV32ZBB-NEXT: ret1896;1897; RV64ZBB-LABEL: rotl_64_mask_shared:1898; RV64ZBB: # %bb.0:1899; RV64ZBB-NEXT: rol a0, a0, a21900; RV64ZBB-NEXT: sll a1, a1, a21901; RV64ZBB-NEXT: add a0, a0, a11902; RV64ZBB-NEXT: ret1903;1904; RV32XTHEADBB-LABEL: rotl_64_mask_shared:1905; RV32XTHEADBB: # %bb.0:1906; RV32XTHEADBB-NEXT: andi a5, a4, 631907; RV32XTHEADBB-NEXT: li t0, 321908; RV32XTHEADBB-NEXT: neg a7, a51909; RV32XTHEADBB-NEXT: bltu a5, t0, .LBB17_21910; RV32XTHEADBB-NEXT: # %bb.1:1911; RV32XTHEADBB-NEXT: li a6, 01912; RV32XTHEADBB-NEXT: sll t3, a0, a51913; RV32XTHEADBB-NEXT: j .LBB17_31914; RV32XTHEADBB-NEXT: .LBB17_2:1915; RV32XTHEADBB-NEXT: sll a6, a0, a41916; RV32XTHEADBB-NEXT: srl t1, a0, a71917; RV32XTHEADBB-NEXT: sll t2, a1, a41918; RV32XTHEADBB-NEXT: or t3, t1, t21919; RV32XTHEADBB-NEXT: .LBB17_3:1920; RV32XTHEADBB-NEXT: neg t2, a51921; RV32XTHEADBB-NEXT: mv t1, a11922; RV32XTHEADBB-NEXT: beqz a5, .LBB17_51923; RV32XTHEADBB-NEXT: # %bb.4:1924; RV32XTHEADBB-NEXT: mv t1, t31925; RV32XTHEADBB-NEXT: .LBB17_5:1926; RV32XTHEADBB-NEXT: andi t3, t2, 631927; RV32XTHEADBB-NEXT: bltu t3, t0, .LBB17_71928; RV32XTHEADBB-NEXT: # %bb.6:1929; RV32XTHEADBB-NEXT: srl t4, a1, t31930; RV32XTHEADBB-NEXT: bnez t3, .LBB17_81931; RV32XTHEADBB-NEXT: j .LBB17_91932; RV32XTHEADBB-NEXT: .LBB17_7:1933; RV32XTHEADBB-NEXT: srl t4, a0, t21934; RV32XTHEADBB-NEXT: neg t5, t31935; RV32XTHEADBB-NEXT: sll t5, a1, t51936; RV32XTHEADBB-NEXT: or t4, t4, t51937; RV32XTHEADBB-NEXT: beqz t3, .LBB17_91938; RV32XTHEADBB-NEXT: .LBB17_8:1939; RV32XTHEADBB-NEXT: mv a0, t41940; RV32XTHEADBB-NEXT: .LBB17_9:1941; RV32XTHEADBB-NEXT: bltu t3, t0, .LBB17_121942; RV32XTHEADBB-NEXT: # %bb.10:1943; RV32XTHEADBB-NEXT: li a1, 01944; RV32XTHEADBB-NEXT: bgeu a5, t0, .LBB17_131945; RV32XTHEADBB-NEXT: .LBB17_11:1946; RV32XTHEADBB-NEXT: sll t0, a2, a41947; RV32XTHEADBB-NEXT: srl a2, a2, a71948; RV32XTHEADBB-NEXT: sll a4, a3, a41949; RV32XTHEADBB-NEXT: or a2, a2, a41950; RV32XTHEADBB-NEXT: j .LBB17_141951; RV32XTHEADBB-NEXT: .LBB17_12:1952; RV32XTHEADBB-NEXT: srl a1, a1, t21953; RV32XTHEADBB-NEXT: bltu a5, t0, .LBB17_111954; RV32XTHEADBB-NEXT: .LBB17_13:1955; RV32XTHEADBB-NEXT: li t0, 01956; RV32XTHEADBB-NEXT: sll a2, a2, a51957; RV32XTHEADBB-NEXT: .LBB17_14:1958; RV32XTHEADBB-NEXT: or a0, a6, a01959; RV32XTHEADBB-NEXT: or a1, t1, a11960; RV32XTHEADBB-NEXT: beqz a5, .LBB17_161961; RV32XTHEADBB-NEXT: # %bb.15:1962; RV32XTHEADBB-NEXT: mv a3, a21963; RV32XTHEADBB-NEXT: .LBB17_16:1964; RV32XTHEADBB-NEXT: add a0, a0, t01965; RV32XTHEADBB-NEXT: sltu a2, a0, t01966; RV32XTHEADBB-NEXT: add a1, a1, a31967; RV32XTHEADBB-NEXT: add a1, a1, a21968; RV32XTHEADBB-NEXT: ret1969;1970; RV64XTHEADBB-LABEL: rotl_64_mask_shared:1971; RV64XTHEADBB: # %bb.0:1972; RV64XTHEADBB-NEXT: andi a3, a2, 631973; RV64XTHEADBB-NEXT: sll a4, a0, a21974; RV64XTHEADBB-NEXT: neg a3, a31975; RV64XTHEADBB-NEXT: srl a0, a0, a31976; RV64XTHEADBB-NEXT: or a0, a4, a01977; RV64XTHEADBB-NEXT: sll a1, a1, a21978; RV64XTHEADBB-NEXT: add a0, a0, a11979; RV64XTHEADBB-NEXT: ret1980 %maskedamt = and i64 %amt, 631981 %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %maskedamt)1982 %2 = shl i64 %b, %maskedamt1983 %3 = add i64 %1, %21984 ret i64 %31985}1986 1987define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {1988; RV32I-LABEL: rotr_32_mask_shared:1989; RV32I: # %bb.0:1990; RV32I-NEXT: andi a3, a2, 311991; RV32I-NEXT: srl a4, a0, a21992; RV32I-NEXT: neg a3, a31993; RV32I-NEXT: sll a0, a0, a31994; RV32I-NEXT: or a0, a4, a01995; RV32I-NEXT: sll a1, a1, a21996; RV32I-NEXT: add a0, a0, a11997; RV32I-NEXT: ret1998;1999; RV64I-LABEL: rotr_32_mask_shared:2000; RV64I: # %bb.0:2001; RV64I-NEXT: andi a3, a2, 312002; RV64I-NEXT: srlw a4, a0, a22003; RV64I-NEXT: neg a3, a32004; RV64I-NEXT: sllw a0, a0, a32005; RV64I-NEXT: or a0, a4, a02006; RV64I-NEXT: sllw a1, a1, a22007; RV64I-NEXT: addw a0, a0, a12008; RV64I-NEXT: ret2009;2010; RV32ZBB-LABEL: rotr_32_mask_shared:2011; RV32ZBB: # %bb.0:2012; RV32ZBB-NEXT: ror a0, a0, a22013; RV32ZBB-NEXT: sll a1, a1, a22014; RV32ZBB-NEXT: add a0, a0, a12015; RV32ZBB-NEXT: ret2016;2017; RV64ZBB-LABEL: rotr_32_mask_shared:2018; RV64ZBB: # %bb.0:2019; RV64ZBB-NEXT: rorw a0, a0, a22020; RV64ZBB-NEXT: sllw a1, a1, a22021; RV64ZBB-NEXT: addw a0, a0, a12022; RV64ZBB-NEXT: ret2023;2024; RV32XTHEADBB-LABEL: rotr_32_mask_shared:2025; RV32XTHEADBB: # %bb.0:2026; RV32XTHEADBB-NEXT: andi a3, a2, 312027; RV32XTHEADBB-NEXT: srl a4, a0, a22028; RV32XTHEADBB-NEXT: neg a3, a32029; RV32XTHEADBB-NEXT: sll a0, a0, a32030; RV32XTHEADBB-NEXT: or a0, a4, a02031; RV32XTHEADBB-NEXT: sll a1, a1, a22032; RV32XTHEADBB-NEXT: add a0, a0, a12033; RV32XTHEADBB-NEXT: ret2034;2035; RV64XTHEADBB-LABEL: rotr_32_mask_shared:2036; RV64XTHEADBB: # %bb.0:2037; RV64XTHEADBB-NEXT: andi a3, a2, 312038; RV64XTHEADBB-NEXT: srlw a4, a0, a22039; RV64XTHEADBB-NEXT: neg a3, a32040; RV64XTHEADBB-NEXT: sllw a0, a0, a32041; RV64XTHEADBB-NEXT: or a0, a4, a02042; RV64XTHEADBB-NEXT: sllw a1, a1, a22043; RV64XTHEADBB-NEXT: addw a0, a0, a12044; RV64XTHEADBB-NEXT: ret2045 %maskedamt = and i32 %amt, 312046 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)2047 %2 = shl i32 %b, %maskedamt2048 %3 = add i32 %1, %22049 ret i32 %32050}2051 2052define signext i64 @rotr_64_mask_shared(i64 signext %a, i64 signext %b, i64 signext %amt) nounwind {2053; RV32I-LABEL: rotr_64_mask_shared:2054; RV32I: # %bb.0:2055; RV32I-NEXT: andi a5, a4, 632056; RV32I-NEXT: li t0, 322057; RV32I-NEXT: neg a6, a52058; RV32I-NEXT: bltu a5, t0, .LBB19_22059; RV32I-NEXT: # %bb.1:2060; RV32I-NEXT: srl t1, a1, a52061; RV32I-NEXT: mv a7, a02062; RV32I-NEXT: bnez a5, .LBB19_32063; RV32I-NEXT: j .LBB19_42064; RV32I-NEXT: .LBB19_2:2065; RV32I-NEXT: srl a7, a0, a42066; RV32I-NEXT: sll t1, a1, a62067; RV32I-NEXT: or t1, a7, t12068; RV32I-NEXT: mv a7, a02069; RV32I-NEXT: beqz a5, .LBB19_42070; RV32I-NEXT: .LBB19_3:2071; RV32I-NEXT: mv a7, t12072; RV32I-NEXT: .LBB19_4:2073; RV32I-NEXT: neg t4, a52074; RV32I-NEXT: bltu a5, t0, .LBB19_72075; RV32I-NEXT: # %bb.5:2076; RV32I-NEXT: li t1, 02077; RV32I-NEXT: andi t3, t4, 632078; RV32I-NEXT: bgeu t3, t0, .LBB19_82079; RV32I-NEXT: .LBB19_6:2080; RV32I-NEXT: sll t2, a0, t42081; RV32I-NEXT: neg t5, t32082; RV32I-NEXT: srl a0, a0, t52083; RV32I-NEXT: sll t4, a1, t42084; RV32I-NEXT: or a0, a0, t42085; RV32I-NEXT: bnez t3, .LBB19_92086; RV32I-NEXT: j .LBB19_102087; RV32I-NEXT: .LBB19_7:2088; RV32I-NEXT: srl t1, a1, a42089; RV32I-NEXT: andi t3, t4, 632090; RV32I-NEXT: bltu t3, t0, .LBB19_62091; RV32I-NEXT: .LBB19_8:2092; RV32I-NEXT: li t2, 02093; RV32I-NEXT: sll a0, a0, t32094; RV32I-NEXT: beqz t3, .LBB19_102095; RV32I-NEXT: .LBB19_9:2096; RV32I-NEXT: mv a1, a02097; RV32I-NEXT: .LBB19_10:2098; RV32I-NEXT: bltu a5, t0, .LBB19_122099; RV32I-NEXT: # %bb.11:2100; RV32I-NEXT: li t0, 02101; RV32I-NEXT: sll a0, a2, a52102; RV32I-NEXT: j .LBB19_132103; RV32I-NEXT: .LBB19_12:2104; RV32I-NEXT: sll t0, a2, a42105; RV32I-NEXT: srl a0, a2, a62106; RV32I-NEXT: sll a2, a3, a42107; RV32I-NEXT: or a0, a0, a22108; RV32I-NEXT: .LBB19_13:2109; RV32I-NEXT: or a2, a7, t22110; RV32I-NEXT: or a1, t1, a12111; RV32I-NEXT: beqz a5, .LBB19_152112; RV32I-NEXT: # %bb.14:2113; RV32I-NEXT: mv a3, a02114; RV32I-NEXT: .LBB19_15:2115; RV32I-NEXT: add a0, a2, t02116; RV32I-NEXT: sltu a2, a0, t02117; RV32I-NEXT: add a1, a1, a32118; RV32I-NEXT: add a1, a1, a22119; RV32I-NEXT: ret2120;2121; RV64I-LABEL: rotr_64_mask_shared:2122; RV64I: # %bb.0:2123; RV64I-NEXT: andi a3, a2, 632124; RV64I-NEXT: srl a4, a0, a22125; RV64I-NEXT: neg a3, a32126; RV64I-NEXT: sll a0, a0, a32127; RV64I-NEXT: or a0, a4, a02128; RV64I-NEXT: sll a1, a1, a22129; RV64I-NEXT: add a0, a0, a12130; RV64I-NEXT: ret2131;2132; RV32ZBB-LABEL: rotr_64_mask_shared:2133; RV32ZBB: # %bb.0:2134; RV32ZBB-NEXT: andi a5, a4, 632135; RV32ZBB-NEXT: li t0, 322136; RV32ZBB-NEXT: neg a6, a52137; RV32ZBB-NEXT: bltu a5, t0, .LBB19_22138; RV32ZBB-NEXT: # %bb.1:2139; RV32ZBB-NEXT: srl t1, a1, a52140; RV32ZBB-NEXT: mv a7, a02141; RV32ZBB-NEXT: bnez a5, .LBB19_32142; RV32ZBB-NEXT: j .LBB19_42143; RV32ZBB-NEXT: .LBB19_2:2144; RV32ZBB-NEXT: srl a7, a0, a42145; RV32ZBB-NEXT: sll t1, a1, a62146; RV32ZBB-NEXT: or t1, a7, t12147; RV32ZBB-NEXT: mv a7, a02148; RV32ZBB-NEXT: beqz a5, .LBB19_42149; RV32ZBB-NEXT: .LBB19_3:2150; RV32ZBB-NEXT: mv a7, t12151; RV32ZBB-NEXT: .LBB19_4:2152; RV32ZBB-NEXT: neg t4, a52153; RV32ZBB-NEXT: bltu a5, t0, .LBB19_72154; RV32ZBB-NEXT: # %bb.5:2155; RV32ZBB-NEXT: li t1, 02156; RV32ZBB-NEXT: andi t3, t4, 632157; RV32ZBB-NEXT: bgeu t3, t0, .LBB19_82158; RV32ZBB-NEXT: .LBB19_6:2159; RV32ZBB-NEXT: sll t2, a0, t42160; RV32ZBB-NEXT: neg t5, t32161; RV32ZBB-NEXT: srl a0, a0, t52162; RV32ZBB-NEXT: sll t4, a1, t42163; RV32ZBB-NEXT: or a0, a0, t42164; RV32ZBB-NEXT: bnez t3, .LBB19_92165; RV32ZBB-NEXT: j .LBB19_102166; RV32ZBB-NEXT: .LBB19_7:2167; RV32ZBB-NEXT: srl t1, a1, a42168; RV32ZBB-NEXT: andi t3, t4, 632169; RV32ZBB-NEXT: bltu t3, t0, .LBB19_62170; RV32ZBB-NEXT: .LBB19_8:2171; RV32ZBB-NEXT: li t2, 02172; RV32ZBB-NEXT: sll a0, a0, t32173; RV32ZBB-NEXT: beqz t3, .LBB19_102174; RV32ZBB-NEXT: .LBB19_9:2175; RV32ZBB-NEXT: mv a1, a02176; RV32ZBB-NEXT: .LBB19_10:2177; RV32ZBB-NEXT: bltu a5, t0, .LBB19_122178; RV32ZBB-NEXT: # %bb.11:2179; RV32ZBB-NEXT: li t0, 02180; RV32ZBB-NEXT: sll a0, a2, a52181; RV32ZBB-NEXT: j .LBB19_132182; RV32ZBB-NEXT: .LBB19_12:2183; RV32ZBB-NEXT: sll t0, a2, a42184; RV32ZBB-NEXT: srl a0, a2, a62185; RV32ZBB-NEXT: sll a2, a3, a42186; RV32ZBB-NEXT: or a0, a0, a22187; RV32ZBB-NEXT: .LBB19_13:2188; RV32ZBB-NEXT: or a2, a7, t22189; RV32ZBB-NEXT: or a1, t1, a12190; RV32ZBB-NEXT: beqz a5, .LBB19_152191; RV32ZBB-NEXT: # %bb.14:2192; RV32ZBB-NEXT: mv a3, a02193; RV32ZBB-NEXT: .LBB19_15:2194; RV32ZBB-NEXT: add a0, a2, t02195; RV32ZBB-NEXT: sltu a2, a0, t02196; RV32ZBB-NEXT: add a1, a1, a32197; RV32ZBB-NEXT: add a1, a1, a22198; RV32ZBB-NEXT: ret2199;2200; RV64ZBB-LABEL: rotr_64_mask_shared:2201; RV64ZBB: # %bb.0:2202; RV64ZBB-NEXT: ror a0, a0, a22203; RV64ZBB-NEXT: sll a1, a1, a22204; RV64ZBB-NEXT: add a0, a0, a12205; RV64ZBB-NEXT: ret2206;2207; RV32XTHEADBB-LABEL: rotr_64_mask_shared:2208; RV32XTHEADBB: # %bb.0:2209; RV32XTHEADBB-NEXT: andi a5, a4, 632210; RV32XTHEADBB-NEXT: li t0, 322211; RV32XTHEADBB-NEXT: neg a6, a52212; RV32XTHEADBB-NEXT: bltu a5, t0, .LBB19_22213; RV32XTHEADBB-NEXT: # %bb.1:2214; RV32XTHEADBB-NEXT: srl t1, a1, a52215; RV32XTHEADBB-NEXT: mv a7, a02216; RV32XTHEADBB-NEXT: bnez a5, .LBB19_32217; RV32XTHEADBB-NEXT: j .LBB19_42218; RV32XTHEADBB-NEXT: .LBB19_2:2219; RV32XTHEADBB-NEXT: srl a7, a0, a42220; RV32XTHEADBB-NEXT: sll t1, a1, a62221; RV32XTHEADBB-NEXT: or t1, a7, t12222; RV32XTHEADBB-NEXT: mv a7, a02223; RV32XTHEADBB-NEXT: beqz a5, .LBB19_42224; RV32XTHEADBB-NEXT: .LBB19_3:2225; RV32XTHEADBB-NEXT: mv a7, t12226; RV32XTHEADBB-NEXT: .LBB19_4:2227; RV32XTHEADBB-NEXT: neg t4, a52228; RV32XTHEADBB-NEXT: bltu a5, t0, .LBB19_72229; RV32XTHEADBB-NEXT: # %bb.5:2230; RV32XTHEADBB-NEXT: li t1, 02231; RV32XTHEADBB-NEXT: andi t3, t4, 632232; RV32XTHEADBB-NEXT: bgeu t3, t0, .LBB19_82233; RV32XTHEADBB-NEXT: .LBB19_6:2234; RV32XTHEADBB-NEXT: sll t2, a0, t42235; RV32XTHEADBB-NEXT: neg t5, t32236; RV32XTHEADBB-NEXT: srl a0, a0, t52237; RV32XTHEADBB-NEXT: sll t4, a1, t42238; RV32XTHEADBB-NEXT: or a0, a0, t42239; RV32XTHEADBB-NEXT: bnez t3, .LBB19_92240; RV32XTHEADBB-NEXT: j .LBB19_102241; RV32XTHEADBB-NEXT: .LBB19_7:2242; RV32XTHEADBB-NEXT: srl t1, a1, a42243; RV32XTHEADBB-NEXT: andi t3, t4, 632244; RV32XTHEADBB-NEXT: bltu t3, t0, .LBB19_62245; RV32XTHEADBB-NEXT: .LBB19_8:2246; RV32XTHEADBB-NEXT: li t2, 02247; RV32XTHEADBB-NEXT: sll a0, a0, t32248; RV32XTHEADBB-NEXT: beqz t3, .LBB19_102249; RV32XTHEADBB-NEXT: .LBB19_9:2250; RV32XTHEADBB-NEXT: mv a1, a02251; RV32XTHEADBB-NEXT: .LBB19_10:2252; RV32XTHEADBB-NEXT: bltu a5, t0, .LBB19_122253; RV32XTHEADBB-NEXT: # %bb.11:2254; RV32XTHEADBB-NEXT: li t0, 02255; RV32XTHEADBB-NEXT: sll a0, a2, a52256; RV32XTHEADBB-NEXT: j .LBB19_132257; RV32XTHEADBB-NEXT: .LBB19_12:2258; RV32XTHEADBB-NEXT: sll t0, a2, a42259; RV32XTHEADBB-NEXT: srl a0, a2, a62260; RV32XTHEADBB-NEXT: sll a2, a3, a42261; RV32XTHEADBB-NEXT: or a0, a0, a22262; RV32XTHEADBB-NEXT: .LBB19_13:2263; RV32XTHEADBB-NEXT: or a2, a7, t22264; RV32XTHEADBB-NEXT: or a1, t1, a12265; RV32XTHEADBB-NEXT: beqz a5, .LBB19_152266; RV32XTHEADBB-NEXT: # %bb.14:2267; RV32XTHEADBB-NEXT: mv a3, a02268; RV32XTHEADBB-NEXT: .LBB19_15:2269; RV32XTHEADBB-NEXT: add a0, a2, t02270; RV32XTHEADBB-NEXT: sltu a2, a0, t02271; RV32XTHEADBB-NEXT: add a1, a1, a32272; RV32XTHEADBB-NEXT: add a1, a1, a22273; RV32XTHEADBB-NEXT: ret2274;2275; RV64XTHEADBB-LABEL: rotr_64_mask_shared:2276; RV64XTHEADBB: # %bb.0:2277; RV64XTHEADBB-NEXT: andi a3, a2, 632278; RV64XTHEADBB-NEXT: srl a4, a0, a22279; RV64XTHEADBB-NEXT: neg a3, a32280; RV64XTHEADBB-NEXT: sll a0, a0, a32281; RV64XTHEADBB-NEXT: or a0, a4, a02282; RV64XTHEADBB-NEXT: sll a1, a1, a22283; RV64XTHEADBB-NEXT: add a0, a0, a12284; RV64XTHEADBB-NEXT: ret2285 %maskedamt = and i64 %amt, 632286 %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %maskedamt)2287 %2 = shl i64 %b, %maskedamt2288 %3 = add i64 %1, %22289 ret i64 %32290}2291 2292define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {2293; RV32I-LABEL: rotl_32_mask_multiple:2294; RV32I: # %bb.0:2295; RV32I-NEXT: andi a3, a2, 312296; RV32I-NEXT: sll a4, a0, a22297; RV32I-NEXT: sll a2, a1, a22298; RV32I-NEXT: neg a3, a32299; RV32I-NEXT: srl a0, a0, a32300; RV32I-NEXT: srl a1, a1, a32301; RV32I-NEXT: or a0, a4, a02302; RV32I-NEXT: or a1, a2, a12303; RV32I-NEXT: add a0, a0, a12304; RV32I-NEXT: ret2305;2306; RV64I-LABEL: rotl_32_mask_multiple:2307; RV64I: # %bb.0:2308; RV64I-NEXT: andi a3, a2, 312309; RV64I-NEXT: sllw a4, a0, a22310; RV64I-NEXT: sllw a2, a1, a22311; RV64I-NEXT: neg a5, a32312; RV64I-NEXT: neg a3, a32313; RV64I-NEXT: srlw a0, a0, a52314; RV64I-NEXT: srlw a1, a1, a32315; RV64I-NEXT: or a0, a4, a02316; RV64I-NEXT: or a1, a2, a12317; RV64I-NEXT: addw a0, a0, a12318; RV64I-NEXT: ret2319;2320; RV32ZBB-LABEL: rotl_32_mask_multiple:2321; RV32ZBB: # %bb.0:2322; RV32ZBB-NEXT: rol a0, a0, a22323; RV32ZBB-NEXT: rol a1, a1, a22324; RV32ZBB-NEXT: add a0, a0, a12325; RV32ZBB-NEXT: ret2326;2327; RV64ZBB-LABEL: rotl_32_mask_multiple:2328; RV64ZBB: # %bb.0:2329; RV64ZBB-NEXT: rolw a0, a0, a22330; RV64ZBB-NEXT: rolw a1, a1, a22331; RV64ZBB-NEXT: addw a0, a0, a12332; RV64ZBB-NEXT: ret2333;2334; RV32XTHEADBB-LABEL: rotl_32_mask_multiple:2335; RV32XTHEADBB: # %bb.0:2336; RV32XTHEADBB-NEXT: andi a3, a2, 312337; RV32XTHEADBB-NEXT: sll a4, a0, a22338; RV32XTHEADBB-NEXT: sll a2, a1, a22339; RV32XTHEADBB-NEXT: neg a3, a32340; RV32XTHEADBB-NEXT: srl a0, a0, a32341; RV32XTHEADBB-NEXT: srl a1, a1, a32342; RV32XTHEADBB-NEXT: or a0, a4, a02343; RV32XTHEADBB-NEXT: or a1, a2, a12344; RV32XTHEADBB-NEXT: add a0, a0, a12345; RV32XTHEADBB-NEXT: ret2346;2347; RV64XTHEADBB-LABEL: rotl_32_mask_multiple:2348; RV64XTHEADBB: # %bb.0:2349; RV64XTHEADBB-NEXT: andi a3, a2, 312350; RV64XTHEADBB-NEXT: sllw a4, a0, a22351; RV64XTHEADBB-NEXT: sllw a2, a1, a22352; RV64XTHEADBB-NEXT: neg a5, a32353; RV64XTHEADBB-NEXT: neg a3, a32354; RV64XTHEADBB-NEXT: srlw a0, a0, a52355; RV64XTHEADBB-NEXT: srlw a1, a1, a32356; RV64XTHEADBB-NEXT: or a0, a4, a02357; RV64XTHEADBB-NEXT: or a1, a2, a12358; RV64XTHEADBB-NEXT: addw a0, a0, a12359; RV64XTHEADBB-NEXT: ret2360 %maskedamt = and i32 %amt, 312361 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)2362 %2 = tail call i32 @llvm.fshl.i32(i32 %b, i32 %b, i32 %maskedamt)2363 %3 = add i32 %1, %22364 ret i32 %32365}2366 2367define i64 @rotl_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {2368; RV32I-LABEL: rotl_64_mask_multiple:2369; RV32I: # %bb.0:2370; RV32I-NEXT: andi t1, a4, 632371; RV32I-NEXT: li a5, 322372; RV32I-NEXT: neg t3, t12373; RV32I-NEXT: bltu t1, a5, .LBB21_22374; RV32I-NEXT: # %bb.1:2375; RV32I-NEXT: li a6, 02376; RV32I-NEXT: sll t2, a0, t12377; RV32I-NEXT: j .LBB21_32378; RV32I-NEXT: .LBB21_2:2379; RV32I-NEXT: sll a6, a0, a42380; RV32I-NEXT: srl a7, a0, t32381; RV32I-NEXT: sll t0, a1, a42382; RV32I-NEXT: or t2, a7, t02383; RV32I-NEXT: .LBB21_3:2384; RV32I-NEXT: neg a7, t12385; RV32I-NEXT: mv t0, a12386; RV32I-NEXT: beqz t1, .LBB21_52387; RV32I-NEXT: # %bb.4:2388; RV32I-NEXT: mv t0, t22389; RV32I-NEXT: .LBB21_5:2390; RV32I-NEXT: andi t2, a7, 632391; RV32I-NEXT: neg t4, t22392; RV32I-NEXT: bltu t2, a5, .LBB21_72393; RV32I-NEXT: # %bb.6:2394; RV32I-NEXT: srl t5, a1, t22395; RV32I-NEXT: bnez t2, .LBB21_82396; RV32I-NEXT: j .LBB21_92397; RV32I-NEXT: .LBB21_7:2398; RV32I-NEXT: srl t5, a0, a72399; RV32I-NEXT: sll t6, a1, t42400; RV32I-NEXT: or t5, t5, t62401; RV32I-NEXT: beqz t2, .LBB21_92402; RV32I-NEXT: .LBB21_8:2403; RV32I-NEXT: mv a0, t52404; RV32I-NEXT: .LBB21_9:2405; RV32I-NEXT: bltu t2, a5, .LBB21_122406; RV32I-NEXT: # %bb.10:2407; RV32I-NEXT: li t5, 02408; RV32I-NEXT: bgeu t1, a5, .LBB21_132409; RV32I-NEXT: .LBB21_11:2410; RV32I-NEXT: sll a1, a2, a42411; RV32I-NEXT: srl t3, a2, t32412; RV32I-NEXT: sll a4, a3, a42413; RV32I-NEXT: or t3, t3, a42414; RV32I-NEXT: mv a4, a32415; RV32I-NEXT: bnez t1, .LBB21_142416; RV32I-NEXT: j .LBB21_152417; RV32I-NEXT: .LBB21_12:2418; RV32I-NEXT: srl t5, a1, a72419; RV32I-NEXT: bltu t1, a5, .LBB21_112420; RV32I-NEXT: .LBB21_13:2421; RV32I-NEXT: li a1, 02422; RV32I-NEXT: sll t3, a2, t12423; RV32I-NEXT: mv a4, a32424; RV32I-NEXT: beqz t1, .LBB21_152425; RV32I-NEXT: .LBB21_14:2426; RV32I-NEXT: mv a4, t32427; RV32I-NEXT: .LBB21_15:2428; RV32I-NEXT: bltu t2, a5, .LBB21_172429; RV32I-NEXT: # %bb.16:2430; RV32I-NEXT: srl t1, a3, t22431; RV32I-NEXT: bnez t2, .LBB21_182432; RV32I-NEXT: j .LBB21_192433; RV32I-NEXT: .LBB21_17:2434; RV32I-NEXT: srl t1, a2, a72435; RV32I-NEXT: sll t3, a3, t42436; RV32I-NEXT: or t1, t1, t32437; RV32I-NEXT: beqz t2, .LBB21_192438; RV32I-NEXT: .LBB21_18:2439; RV32I-NEXT: mv a2, t12440; RV32I-NEXT: .LBB21_19:2441; RV32I-NEXT: or a0, a6, a02442; RV32I-NEXT: or a6, t0, t52443; RV32I-NEXT: bltu t2, a5, .LBB21_212444; RV32I-NEXT: # %bb.20:2445; RV32I-NEXT: li a3, 02446; RV32I-NEXT: j .LBB21_222447; RV32I-NEXT: .LBB21_21:2448; RV32I-NEXT: srl a3, a3, a72449; RV32I-NEXT: .LBB21_22:2450; RV32I-NEXT: or a1, a1, a22451; RV32I-NEXT: or a3, a4, a32452; RV32I-NEXT: add a0, a0, a12453; RV32I-NEXT: sltu a1, a0, a12454; RV32I-NEXT: add a3, a6, a32455; RV32I-NEXT: add a1, a3, a12456; RV32I-NEXT: ret2457;2458; RV64I-LABEL: rotl_64_mask_multiple:2459; RV64I: # %bb.0:2460; RV64I-NEXT: andi a3, a2, 632461; RV64I-NEXT: sll a4, a0, a22462; RV64I-NEXT: sll a2, a1, a22463; RV64I-NEXT: neg a3, a32464; RV64I-NEXT: srl a0, a0, a32465; RV64I-NEXT: srl a1, a1, a32466; RV64I-NEXT: or a0, a4, a02467; RV64I-NEXT: or a1, a2, a12468; RV64I-NEXT: add a0, a0, a12469; RV64I-NEXT: ret2470;2471; RV32ZBB-LABEL: rotl_64_mask_multiple:2472; RV32ZBB: # %bb.0:2473; RV32ZBB-NEXT: andi t1, a4, 632474; RV32ZBB-NEXT: li a5, 322475; RV32ZBB-NEXT: neg t3, t12476; RV32ZBB-NEXT: bltu t1, a5, .LBB21_22477; RV32ZBB-NEXT: # %bb.1:2478; RV32ZBB-NEXT: li a6, 02479; RV32ZBB-NEXT: sll t2, a0, t12480; RV32ZBB-NEXT: j .LBB21_32481; RV32ZBB-NEXT: .LBB21_2:2482; RV32ZBB-NEXT: sll a6, a0, a42483; RV32ZBB-NEXT: srl a7, a0, t32484; RV32ZBB-NEXT: sll t0, a1, a42485; RV32ZBB-NEXT: or t2, a7, t02486; RV32ZBB-NEXT: .LBB21_3:2487; RV32ZBB-NEXT: neg a7, t12488; RV32ZBB-NEXT: mv t0, a12489; RV32ZBB-NEXT: beqz t1, .LBB21_52490; RV32ZBB-NEXT: # %bb.4:2491; RV32ZBB-NEXT: mv t0, t22492; RV32ZBB-NEXT: .LBB21_5:2493; RV32ZBB-NEXT: andi t2, a7, 632494; RV32ZBB-NEXT: neg t4, t22495; RV32ZBB-NEXT: bltu t2, a5, .LBB21_72496; RV32ZBB-NEXT: # %bb.6:2497; RV32ZBB-NEXT: srl t5, a1, t22498; RV32ZBB-NEXT: bnez t2, .LBB21_82499; RV32ZBB-NEXT: j .LBB21_92500; RV32ZBB-NEXT: .LBB21_7:2501; RV32ZBB-NEXT: srl t5, a0, a72502; RV32ZBB-NEXT: sll t6, a1, t42503; RV32ZBB-NEXT: or t5, t5, t62504; RV32ZBB-NEXT: beqz t2, .LBB21_92505; RV32ZBB-NEXT: .LBB21_8:2506; RV32ZBB-NEXT: mv a0, t52507; RV32ZBB-NEXT: .LBB21_9:2508; RV32ZBB-NEXT: bltu t2, a5, .LBB21_122509; RV32ZBB-NEXT: # %bb.10:2510; RV32ZBB-NEXT: li t5, 02511; RV32ZBB-NEXT: bgeu t1, a5, .LBB21_132512; RV32ZBB-NEXT: .LBB21_11:2513; RV32ZBB-NEXT: sll a1, a2, a42514; RV32ZBB-NEXT: srl t3, a2, t32515; RV32ZBB-NEXT: sll a4, a3, a42516; RV32ZBB-NEXT: or t3, t3, a42517; RV32ZBB-NEXT: mv a4, a32518; RV32ZBB-NEXT: bnez t1, .LBB21_142519; RV32ZBB-NEXT: j .LBB21_152520; RV32ZBB-NEXT: .LBB21_12:2521; RV32ZBB-NEXT: srl t5, a1, a72522; RV32ZBB-NEXT: bltu t1, a5, .LBB21_112523; RV32ZBB-NEXT: .LBB21_13:2524; RV32ZBB-NEXT: li a1, 02525; RV32ZBB-NEXT: sll t3, a2, t12526; RV32ZBB-NEXT: mv a4, a32527; RV32ZBB-NEXT: beqz t1, .LBB21_152528; RV32ZBB-NEXT: .LBB21_14:2529; RV32ZBB-NEXT: mv a4, t32530; RV32ZBB-NEXT: .LBB21_15:2531; RV32ZBB-NEXT: bltu t2, a5, .LBB21_172532; RV32ZBB-NEXT: # %bb.16:2533; RV32ZBB-NEXT: srl t1, a3, t22534; RV32ZBB-NEXT: bnez t2, .LBB21_182535; RV32ZBB-NEXT: j .LBB21_192536; RV32ZBB-NEXT: .LBB21_17:2537; RV32ZBB-NEXT: srl t1, a2, a72538; RV32ZBB-NEXT: sll t3, a3, t42539; RV32ZBB-NEXT: or t1, t1, t32540; RV32ZBB-NEXT: beqz t2, .LBB21_192541; RV32ZBB-NEXT: .LBB21_18:2542; RV32ZBB-NEXT: mv a2, t12543; RV32ZBB-NEXT: .LBB21_19:2544; RV32ZBB-NEXT: or a0, a6, a02545; RV32ZBB-NEXT: or a6, t0, t52546; RV32ZBB-NEXT: bltu t2, a5, .LBB21_212547; RV32ZBB-NEXT: # %bb.20:2548; RV32ZBB-NEXT: li a3, 02549; RV32ZBB-NEXT: j .LBB21_222550; RV32ZBB-NEXT: .LBB21_21:2551; RV32ZBB-NEXT: srl a3, a3, a72552; RV32ZBB-NEXT: .LBB21_22:2553; RV32ZBB-NEXT: or a1, a1, a22554; RV32ZBB-NEXT: or a3, a4, a32555; RV32ZBB-NEXT: add a0, a0, a12556; RV32ZBB-NEXT: sltu a1, a0, a12557; RV32ZBB-NEXT: add a3, a6, a32558; RV32ZBB-NEXT: add a1, a3, a12559; RV32ZBB-NEXT: ret2560;2561; RV64ZBB-LABEL: rotl_64_mask_multiple:2562; RV64ZBB: # %bb.0:2563; RV64ZBB-NEXT: rol a0, a0, a22564; RV64ZBB-NEXT: rol a1, a1, a22565; RV64ZBB-NEXT: add a0, a0, a12566; RV64ZBB-NEXT: ret2567;2568; RV32XTHEADBB-LABEL: rotl_64_mask_multiple:2569; RV32XTHEADBB: # %bb.0:2570; RV32XTHEADBB-NEXT: andi t1, a4, 632571; RV32XTHEADBB-NEXT: li a5, 322572; RV32XTHEADBB-NEXT: neg t3, t12573; RV32XTHEADBB-NEXT: bltu t1, a5, .LBB21_22574; RV32XTHEADBB-NEXT: # %bb.1:2575; RV32XTHEADBB-NEXT: li a6, 02576; RV32XTHEADBB-NEXT: sll t2, a0, t12577; RV32XTHEADBB-NEXT: j .LBB21_32578; RV32XTHEADBB-NEXT: .LBB21_2:2579; RV32XTHEADBB-NEXT: sll a6, a0, a42580; RV32XTHEADBB-NEXT: srl a7, a0, t32581; RV32XTHEADBB-NEXT: sll t0, a1, a42582; RV32XTHEADBB-NEXT: or t2, a7, t02583; RV32XTHEADBB-NEXT: .LBB21_3:2584; RV32XTHEADBB-NEXT: neg a7, t12585; RV32XTHEADBB-NEXT: mv t0, a12586; RV32XTHEADBB-NEXT: beqz t1, .LBB21_52587; RV32XTHEADBB-NEXT: # %bb.4:2588; RV32XTHEADBB-NEXT: mv t0, t22589; RV32XTHEADBB-NEXT: .LBB21_5:2590; RV32XTHEADBB-NEXT: andi t2, a7, 632591; RV32XTHEADBB-NEXT: neg t4, t22592; RV32XTHEADBB-NEXT: bltu t2, a5, .LBB21_72593; RV32XTHEADBB-NEXT: # %bb.6:2594; RV32XTHEADBB-NEXT: srl t5, a1, t22595; RV32XTHEADBB-NEXT: bnez t2, .LBB21_82596; RV32XTHEADBB-NEXT: j .LBB21_92597; RV32XTHEADBB-NEXT: .LBB21_7:2598; RV32XTHEADBB-NEXT: srl t5, a0, a72599; RV32XTHEADBB-NEXT: sll t6, a1, t42600; RV32XTHEADBB-NEXT: or t5, t5, t62601; RV32XTHEADBB-NEXT: beqz t2, .LBB21_92602; RV32XTHEADBB-NEXT: .LBB21_8:2603; RV32XTHEADBB-NEXT: mv a0, t52604; RV32XTHEADBB-NEXT: .LBB21_9:2605; RV32XTHEADBB-NEXT: bltu t2, a5, .LBB21_122606; RV32XTHEADBB-NEXT: # %bb.10:2607; RV32XTHEADBB-NEXT: li t5, 02608; RV32XTHEADBB-NEXT: bgeu t1, a5, .LBB21_132609; RV32XTHEADBB-NEXT: .LBB21_11:2610; RV32XTHEADBB-NEXT: sll a1, a2, a42611; RV32XTHEADBB-NEXT: srl t3, a2, t32612; RV32XTHEADBB-NEXT: sll a4, a3, a42613; RV32XTHEADBB-NEXT: or t3, t3, a42614; RV32XTHEADBB-NEXT: mv a4, a32615; RV32XTHEADBB-NEXT: bnez t1, .LBB21_142616; RV32XTHEADBB-NEXT: j .LBB21_152617; RV32XTHEADBB-NEXT: .LBB21_12:2618; RV32XTHEADBB-NEXT: srl t5, a1, a72619; RV32XTHEADBB-NEXT: bltu t1, a5, .LBB21_112620; RV32XTHEADBB-NEXT: .LBB21_13:2621; RV32XTHEADBB-NEXT: li a1, 02622; RV32XTHEADBB-NEXT: sll t3, a2, t12623; RV32XTHEADBB-NEXT: mv a4, a32624; RV32XTHEADBB-NEXT: beqz t1, .LBB21_152625; RV32XTHEADBB-NEXT: .LBB21_14:2626; RV32XTHEADBB-NEXT: mv a4, t32627; RV32XTHEADBB-NEXT: .LBB21_15:2628; RV32XTHEADBB-NEXT: bltu t2, a5, .LBB21_172629; RV32XTHEADBB-NEXT: # %bb.16:2630; RV32XTHEADBB-NEXT: srl t1, a3, t22631; RV32XTHEADBB-NEXT: bnez t2, .LBB21_182632; RV32XTHEADBB-NEXT: j .LBB21_192633; RV32XTHEADBB-NEXT: .LBB21_17:2634; RV32XTHEADBB-NEXT: srl t1, a2, a72635; RV32XTHEADBB-NEXT: sll t3, a3, t42636; RV32XTHEADBB-NEXT: or t1, t1, t32637; RV32XTHEADBB-NEXT: beqz t2, .LBB21_192638; RV32XTHEADBB-NEXT: .LBB21_18:2639; RV32XTHEADBB-NEXT: mv a2, t12640; RV32XTHEADBB-NEXT: .LBB21_19:2641; RV32XTHEADBB-NEXT: or a0, a6, a02642; RV32XTHEADBB-NEXT: or a6, t0, t52643; RV32XTHEADBB-NEXT: bltu t2, a5, .LBB21_212644; RV32XTHEADBB-NEXT: # %bb.20:2645; RV32XTHEADBB-NEXT: li a3, 02646; RV32XTHEADBB-NEXT: j .LBB21_222647; RV32XTHEADBB-NEXT: .LBB21_21:2648; RV32XTHEADBB-NEXT: srl a3, a3, a72649; RV32XTHEADBB-NEXT: .LBB21_22:2650; RV32XTHEADBB-NEXT: or a1, a1, a22651; RV32XTHEADBB-NEXT: or a3, a4, a32652; RV32XTHEADBB-NEXT: add a0, a0, a12653; RV32XTHEADBB-NEXT: sltu a1, a0, a12654; RV32XTHEADBB-NEXT: add a3, a6, a32655; RV32XTHEADBB-NEXT: add a1, a3, a12656; RV32XTHEADBB-NEXT: ret2657;2658; RV64XTHEADBB-LABEL: rotl_64_mask_multiple:2659; RV64XTHEADBB: # %bb.0:2660; RV64XTHEADBB-NEXT: andi a3, a2, 632661; RV64XTHEADBB-NEXT: sll a4, a0, a22662; RV64XTHEADBB-NEXT: sll a2, a1, a22663; RV64XTHEADBB-NEXT: neg a3, a32664; RV64XTHEADBB-NEXT: srl a0, a0, a32665; RV64XTHEADBB-NEXT: srl a1, a1, a32666; RV64XTHEADBB-NEXT: or a0, a4, a02667; RV64XTHEADBB-NEXT: or a1, a2, a12668; RV64XTHEADBB-NEXT: add a0, a0, a12669; RV64XTHEADBB-NEXT: ret2670 %maskedamt = and i64 %amt, 632671 %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %maskedamt)2672 %2 = tail call i64 @llvm.fshl.i64(i64 %b, i64 %b, i64 %maskedamt)2673 %3 = add i64 %1, %22674 ret i64 %32675}2676 2677define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {2678; RV32I-LABEL: rotr_32_mask_multiple:2679; RV32I: # %bb.0:2680; RV32I-NEXT: andi a3, a2, 312681; RV32I-NEXT: srl a4, a0, a22682; RV32I-NEXT: srl a2, a1, a22683; RV32I-NEXT: neg a3, a32684; RV32I-NEXT: sll a0, a0, a32685; RV32I-NEXT: sll a1, a1, a32686; RV32I-NEXT: or a0, a4, a02687; RV32I-NEXT: or a1, a2, a12688; RV32I-NEXT: add a0, a0, a12689; RV32I-NEXT: ret2690;2691; RV64I-LABEL: rotr_32_mask_multiple:2692; RV64I: # %bb.0:2693; RV64I-NEXT: andi a3, a2, 312694; RV64I-NEXT: srlw a4, a0, a22695; RV64I-NEXT: srlw a2, a1, a22696; RV64I-NEXT: neg a5, a32697; RV64I-NEXT: neg a3, a32698; RV64I-NEXT: sllw a0, a0, a52699; RV64I-NEXT: sllw a1, a1, a32700; RV64I-NEXT: or a0, a4, a02701; RV64I-NEXT: or a1, a2, a12702; RV64I-NEXT: addw a0, a0, a12703; RV64I-NEXT: ret2704;2705; RV32ZBB-LABEL: rotr_32_mask_multiple:2706; RV32ZBB: # %bb.0:2707; RV32ZBB-NEXT: ror a0, a0, a22708; RV32ZBB-NEXT: ror a1, a1, a22709; RV32ZBB-NEXT: add a0, a0, a12710; RV32ZBB-NEXT: ret2711;2712; RV64ZBB-LABEL: rotr_32_mask_multiple:2713; RV64ZBB: # %bb.0:2714; RV64ZBB-NEXT: rorw a0, a0, a22715; RV64ZBB-NEXT: rorw a1, a1, a22716; RV64ZBB-NEXT: addw a0, a0, a12717; RV64ZBB-NEXT: ret2718;2719; RV32XTHEADBB-LABEL: rotr_32_mask_multiple:2720; RV32XTHEADBB: # %bb.0:2721; RV32XTHEADBB-NEXT: andi a3, a2, 312722; RV32XTHEADBB-NEXT: srl a4, a0, a22723; RV32XTHEADBB-NEXT: srl a2, a1, a22724; RV32XTHEADBB-NEXT: neg a3, a32725; RV32XTHEADBB-NEXT: sll a0, a0, a32726; RV32XTHEADBB-NEXT: sll a1, a1, a32727; RV32XTHEADBB-NEXT: or a0, a4, a02728; RV32XTHEADBB-NEXT: or a1, a2, a12729; RV32XTHEADBB-NEXT: add a0, a0, a12730; RV32XTHEADBB-NEXT: ret2731;2732; RV64XTHEADBB-LABEL: rotr_32_mask_multiple:2733; RV64XTHEADBB: # %bb.0:2734; RV64XTHEADBB-NEXT: andi a3, a2, 312735; RV64XTHEADBB-NEXT: srlw a4, a0, a22736; RV64XTHEADBB-NEXT: srlw a2, a1, a22737; RV64XTHEADBB-NEXT: neg a5, a32738; RV64XTHEADBB-NEXT: neg a3, a32739; RV64XTHEADBB-NEXT: sllw a0, a0, a52740; RV64XTHEADBB-NEXT: sllw a1, a1, a32741; RV64XTHEADBB-NEXT: or a0, a4, a02742; RV64XTHEADBB-NEXT: or a1, a2, a12743; RV64XTHEADBB-NEXT: addw a0, a0, a12744; RV64XTHEADBB-NEXT: ret2745 %maskedamt = and i32 %amt, 312746 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)2747 %2 = tail call i32 @llvm.fshr.i32(i32 %b, i32 %b, i32 %maskedamt)2748 %3 = add i32 %1, %22749 ret i32 %32750}2751 2752define i64 @rotr_64_mask_multiple(i64 %a, i64 %b, i64 %amt) nounwind {2753; RV32I-LABEL: rotr_64_mask_multiple:2754; RV32I: # %bb.0:2755; RV32I-NEXT: andi t0, a4, 632756; RV32I-NEXT: li a6, 322757; RV32I-NEXT: neg t4, t02758; RV32I-NEXT: bltu t0, a6, .LBB23_22759; RV32I-NEXT: # %bb.1:2760; RV32I-NEXT: srl a7, a1, t02761; RV32I-NEXT: mv a5, a02762; RV32I-NEXT: bnez t0, .LBB23_32763; RV32I-NEXT: j .LBB23_42764; RV32I-NEXT: .LBB23_2:2765; RV32I-NEXT: srl a5, a0, a42766; RV32I-NEXT: sll a7, a1, t42767; RV32I-NEXT: or a7, a5, a72768; RV32I-NEXT: mv a5, a02769; RV32I-NEXT: beqz t0, .LBB23_42770; RV32I-NEXT: .LBB23_3:2771; RV32I-NEXT: mv a5, a72772; RV32I-NEXT: .LBB23_4:2773; RV32I-NEXT: neg t2, t02774; RV32I-NEXT: bltu t0, a6, .LBB23_62775; RV32I-NEXT: # %bb.5:2776; RV32I-NEXT: li a7, 02777; RV32I-NEXT: j .LBB23_72778; RV32I-NEXT: .LBB23_6:2779; RV32I-NEXT: srl a7, a1, a42780; RV32I-NEXT: .LBB23_7:2781; RV32I-NEXT: andi t1, t2, 632782; RV32I-NEXT: neg t5, t12783; RV32I-NEXT: bltu t1, a6, .LBB23_92784; RV32I-NEXT: # %bb.8:2785; RV32I-NEXT: li t3, 02786; RV32I-NEXT: sll a0, a0, t12787; RV32I-NEXT: bnez t1, .LBB23_102788; RV32I-NEXT: j .LBB23_112789; RV32I-NEXT: .LBB23_9:2790; RV32I-NEXT: sll t3, a0, t22791; RV32I-NEXT: srl a0, a0, t52792; RV32I-NEXT: sll t6, a1, t22793; RV32I-NEXT: or a0, a0, t62794; RV32I-NEXT: beqz t1, .LBB23_112795; RV32I-NEXT: .LBB23_10:2796; RV32I-NEXT: mv a1, a02797; RV32I-NEXT: .LBB23_11:2798; RV32I-NEXT: bltu t0, a6, .LBB23_132799; RV32I-NEXT: # %bb.12:2800; RV32I-NEXT: srl t4, a3, t02801; RV32I-NEXT: mv a0, a22802; RV32I-NEXT: bnez t0, .LBB23_142803; RV32I-NEXT: j .LBB23_152804; RV32I-NEXT: .LBB23_13:2805; RV32I-NEXT: srl a0, a2, a42806; RV32I-NEXT: sll t4, a3, t42807; RV32I-NEXT: or t4, a0, t42808; RV32I-NEXT: mv a0, a22809; RV32I-NEXT: beqz t0, .LBB23_152810; RV32I-NEXT: .LBB23_14:2811; RV32I-NEXT: mv a0, t42812; RV32I-NEXT: .LBB23_15:2813; RV32I-NEXT: bltu t0, a6, .LBB23_182814; RV32I-NEXT: # %bb.16:2815; RV32I-NEXT: li a4, 02816; RV32I-NEXT: bgeu t1, a6, .LBB23_192817; RV32I-NEXT: .LBB23_17:2818; RV32I-NEXT: sll a6, a2, t22819; RV32I-NEXT: srl a2, a2, t52820; RV32I-NEXT: sll t0, a3, t22821; RV32I-NEXT: or a2, a2, t02822; RV32I-NEXT: j .LBB23_202823; RV32I-NEXT: .LBB23_18:2824; RV32I-NEXT: srl a4, a3, a42825; RV32I-NEXT: bltu t1, a6, .LBB23_172826; RV32I-NEXT: .LBB23_19:2827; RV32I-NEXT: li a6, 02828; RV32I-NEXT: sll a2, a2, t12829; RV32I-NEXT: .LBB23_20:2830; RV32I-NEXT: or a5, a5, t32831; RV32I-NEXT: or a1, a7, a12832; RV32I-NEXT: beqz t1, .LBB23_222833; RV32I-NEXT: # %bb.21:2834; RV32I-NEXT: mv a3, a22835; RV32I-NEXT: .LBB23_22:2836; RV32I-NEXT: or a2, a0, a62837; RV32I-NEXT: or a3, a4, a32838; RV32I-NEXT: add a0, a5, a22839; RV32I-NEXT: sltu a2, a0, a22840; RV32I-NEXT: add a1, a1, a32841; RV32I-NEXT: add a1, a1, a22842; RV32I-NEXT: ret2843;2844; RV64I-LABEL: rotr_64_mask_multiple:2845; RV64I: # %bb.0:2846; RV64I-NEXT: andi a3, a2, 632847; RV64I-NEXT: srl a4, a0, a22848; RV64I-NEXT: srl a2, a1, a22849; RV64I-NEXT: neg a3, a32850; RV64I-NEXT: sll a0, a0, a32851; RV64I-NEXT: sll a1, a1, a32852; RV64I-NEXT: or a0, a4, a02853; RV64I-NEXT: or a1, a2, a12854; RV64I-NEXT: add a0, a0, a12855; RV64I-NEXT: ret2856;2857; RV32ZBB-LABEL: rotr_64_mask_multiple:2858; RV32ZBB: # %bb.0:2859; RV32ZBB-NEXT: andi t0, a4, 632860; RV32ZBB-NEXT: li a6, 322861; RV32ZBB-NEXT: neg t4, t02862; RV32ZBB-NEXT: bltu t0, a6, .LBB23_22863; RV32ZBB-NEXT: # %bb.1:2864; RV32ZBB-NEXT: srl a7, a1, t02865; RV32ZBB-NEXT: mv a5, a02866; RV32ZBB-NEXT: bnez t0, .LBB23_32867; RV32ZBB-NEXT: j .LBB23_42868; RV32ZBB-NEXT: .LBB23_2:2869; RV32ZBB-NEXT: srl a5, a0, a42870; RV32ZBB-NEXT: sll a7, a1, t42871; RV32ZBB-NEXT: or a7, a5, a72872; RV32ZBB-NEXT: mv a5, a02873; RV32ZBB-NEXT: beqz t0, .LBB23_42874; RV32ZBB-NEXT: .LBB23_3:2875; RV32ZBB-NEXT: mv a5, a72876; RV32ZBB-NEXT: .LBB23_4:2877; RV32ZBB-NEXT: neg t2, t02878; RV32ZBB-NEXT: bltu t0, a6, .LBB23_62879; RV32ZBB-NEXT: # %bb.5:2880; RV32ZBB-NEXT: li a7, 02881; RV32ZBB-NEXT: j .LBB23_72882; RV32ZBB-NEXT: .LBB23_6:2883; RV32ZBB-NEXT: srl a7, a1, a42884; RV32ZBB-NEXT: .LBB23_7:2885; RV32ZBB-NEXT: andi t1, t2, 632886; RV32ZBB-NEXT: neg t5, t12887; RV32ZBB-NEXT: bltu t1, a6, .LBB23_92888; RV32ZBB-NEXT: # %bb.8:2889; RV32ZBB-NEXT: li t3, 02890; RV32ZBB-NEXT: sll a0, a0, t12891; RV32ZBB-NEXT: bnez t1, .LBB23_102892; RV32ZBB-NEXT: j .LBB23_112893; RV32ZBB-NEXT: .LBB23_9:2894; RV32ZBB-NEXT: sll t3, a0, t22895; RV32ZBB-NEXT: srl a0, a0, t52896; RV32ZBB-NEXT: sll t6, a1, t22897; RV32ZBB-NEXT: or a0, a0, t62898; RV32ZBB-NEXT: beqz t1, .LBB23_112899; RV32ZBB-NEXT: .LBB23_10:2900; RV32ZBB-NEXT: mv a1, a02901; RV32ZBB-NEXT: .LBB23_11:2902; RV32ZBB-NEXT: bltu t0, a6, .LBB23_132903; RV32ZBB-NEXT: # %bb.12:2904; RV32ZBB-NEXT: srl t4, a3, t02905; RV32ZBB-NEXT: mv a0, a22906; RV32ZBB-NEXT: bnez t0, .LBB23_142907; RV32ZBB-NEXT: j .LBB23_152908; RV32ZBB-NEXT: .LBB23_13:2909; RV32ZBB-NEXT: srl a0, a2, a42910; RV32ZBB-NEXT: sll t4, a3, t42911; RV32ZBB-NEXT: or t4, a0, t42912; RV32ZBB-NEXT: mv a0, a22913; RV32ZBB-NEXT: beqz t0, .LBB23_152914; RV32ZBB-NEXT: .LBB23_14:2915; RV32ZBB-NEXT: mv a0, t42916; RV32ZBB-NEXT: .LBB23_15:2917; RV32ZBB-NEXT: bltu t0, a6, .LBB23_182918; RV32ZBB-NEXT: # %bb.16:2919; RV32ZBB-NEXT: li a4, 02920; RV32ZBB-NEXT: bgeu t1, a6, .LBB23_192921; RV32ZBB-NEXT: .LBB23_17:2922; RV32ZBB-NEXT: sll a6, a2, t22923; RV32ZBB-NEXT: srl a2, a2, t52924; RV32ZBB-NEXT: sll t0, a3, t22925; RV32ZBB-NEXT: or a2, a2, t02926; RV32ZBB-NEXT: j .LBB23_202927; RV32ZBB-NEXT: .LBB23_18:2928; RV32ZBB-NEXT: srl a4, a3, a42929; RV32ZBB-NEXT: bltu t1, a6, .LBB23_172930; RV32ZBB-NEXT: .LBB23_19:2931; RV32ZBB-NEXT: li a6, 02932; RV32ZBB-NEXT: sll a2, a2, t12933; RV32ZBB-NEXT: .LBB23_20:2934; RV32ZBB-NEXT: or a5, a5, t32935; RV32ZBB-NEXT: or a1, a7, a12936; RV32ZBB-NEXT: beqz t1, .LBB23_222937; RV32ZBB-NEXT: # %bb.21:2938; RV32ZBB-NEXT: mv a3, a22939; RV32ZBB-NEXT: .LBB23_22:2940; RV32ZBB-NEXT: or a2, a0, a62941; RV32ZBB-NEXT: or a3, a4, a32942; RV32ZBB-NEXT: add a0, a5, a22943; RV32ZBB-NEXT: sltu a2, a0, a22944; RV32ZBB-NEXT: add a1, a1, a32945; RV32ZBB-NEXT: add a1, a1, a22946; RV32ZBB-NEXT: ret2947;2948; RV64ZBB-LABEL: rotr_64_mask_multiple:2949; RV64ZBB: # %bb.0:2950; RV64ZBB-NEXT: ror a0, a0, a22951; RV64ZBB-NEXT: ror a1, a1, a22952; RV64ZBB-NEXT: add a0, a0, a12953; RV64ZBB-NEXT: ret2954;2955; RV32XTHEADBB-LABEL: rotr_64_mask_multiple:2956; RV32XTHEADBB: # %bb.0:2957; RV32XTHEADBB-NEXT: andi t0, a4, 632958; RV32XTHEADBB-NEXT: li a6, 322959; RV32XTHEADBB-NEXT: neg t4, t02960; RV32XTHEADBB-NEXT: bltu t0, a6, .LBB23_22961; RV32XTHEADBB-NEXT: # %bb.1:2962; RV32XTHEADBB-NEXT: srl a7, a1, t02963; RV32XTHEADBB-NEXT: mv a5, a02964; RV32XTHEADBB-NEXT: bnez t0, .LBB23_32965; RV32XTHEADBB-NEXT: j .LBB23_42966; RV32XTHEADBB-NEXT: .LBB23_2:2967; RV32XTHEADBB-NEXT: srl a5, a0, a42968; RV32XTHEADBB-NEXT: sll a7, a1, t42969; RV32XTHEADBB-NEXT: or a7, a5, a72970; RV32XTHEADBB-NEXT: mv a5, a02971; RV32XTHEADBB-NEXT: beqz t0, .LBB23_42972; RV32XTHEADBB-NEXT: .LBB23_3:2973; RV32XTHEADBB-NEXT: mv a5, a72974; RV32XTHEADBB-NEXT: .LBB23_4:2975; RV32XTHEADBB-NEXT: neg t2, t02976; RV32XTHEADBB-NEXT: bltu t0, a6, .LBB23_62977; RV32XTHEADBB-NEXT: # %bb.5:2978; RV32XTHEADBB-NEXT: li a7, 02979; RV32XTHEADBB-NEXT: j .LBB23_72980; RV32XTHEADBB-NEXT: .LBB23_6:2981; RV32XTHEADBB-NEXT: srl a7, a1, a42982; RV32XTHEADBB-NEXT: .LBB23_7:2983; RV32XTHEADBB-NEXT: andi t1, t2, 632984; RV32XTHEADBB-NEXT: neg t5, t12985; RV32XTHEADBB-NEXT: bltu t1, a6, .LBB23_92986; RV32XTHEADBB-NEXT: # %bb.8:2987; RV32XTHEADBB-NEXT: li t3, 02988; RV32XTHEADBB-NEXT: sll a0, a0, t12989; RV32XTHEADBB-NEXT: bnez t1, .LBB23_102990; RV32XTHEADBB-NEXT: j .LBB23_112991; RV32XTHEADBB-NEXT: .LBB23_9:2992; RV32XTHEADBB-NEXT: sll t3, a0, t22993; RV32XTHEADBB-NEXT: srl a0, a0, t52994; RV32XTHEADBB-NEXT: sll t6, a1, t22995; RV32XTHEADBB-NEXT: or a0, a0, t62996; RV32XTHEADBB-NEXT: beqz t1, .LBB23_112997; RV32XTHEADBB-NEXT: .LBB23_10:2998; RV32XTHEADBB-NEXT: mv a1, a02999; RV32XTHEADBB-NEXT: .LBB23_11:3000; RV32XTHEADBB-NEXT: bltu t0, a6, .LBB23_133001; RV32XTHEADBB-NEXT: # %bb.12:3002; RV32XTHEADBB-NEXT: srl t4, a3, t03003; RV32XTHEADBB-NEXT: mv a0, a23004; RV32XTHEADBB-NEXT: bnez t0, .LBB23_143005; RV32XTHEADBB-NEXT: j .LBB23_153006; RV32XTHEADBB-NEXT: .LBB23_13:3007; RV32XTHEADBB-NEXT: srl a0, a2, a43008; RV32XTHEADBB-NEXT: sll t4, a3, t43009; RV32XTHEADBB-NEXT: or t4, a0, t43010; RV32XTHEADBB-NEXT: mv a0, a23011; RV32XTHEADBB-NEXT: beqz t0, .LBB23_153012; RV32XTHEADBB-NEXT: .LBB23_14:3013; RV32XTHEADBB-NEXT: mv a0, t43014; RV32XTHEADBB-NEXT: .LBB23_15:3015; RV32XTHEADBB-NEXT: bltu t0, a6, .LBB23_183016; RV32XTHEADBB-NEXT: # %bb.16:3017; RV32XTHEADBB-NEXT: li a4, 03018; RV32XTHEADBB-NEXT: bgeu t1, a6, .LBB23_193019; RV32XTHEADBB-NEXT: .LBB23_17:3020; RV32XTHEADBB-NEXT: sll a6, a2, t23021; RV32XTHEADBB-NEXT: srl a2, a2, t53022; RV32XTHEADBB-NEXT: sll t0, a3, t23023; RV32XTHEADBB-NEXT: or a2, a2, t03024; RV32XTHEADBB-NEXT: j .LBB23_203025; RV32XTHEADBB-NEXT: .LBB23_18:3026; RV32XTHEADBB-NEXT: srl a4, a3, a43027; RV32XTHEADBB-NEXT: bltu t1, a6, .LBB23_173028; RV32XTHEADBB-NEXT: .LBB23_19:3029; RV32XTHEADBB-NEXT: li a6, 03030; RV32XTHEADBB-NEXT: sll a2, a2, t13031; RV32XTHEADBB-NEXT: .LBB23_20:3032; RV32XTHEADBB-NEXT: or a5, a5, t33033; RV32XTHEADBB-NEXT: or a1, a7, a13034; RV32XTHEADBB-NEXT: beqz t1, .LBB23_223035; RV32XTHEADBB-NEXT: # %bb.21:3036; RV32XTHEADBB-NEXT: mv a3, a23037; RV32XTHEADBB-NEXT: .LBB23_22:3038; RV32XTHEADBB-NEXT: or a2, a0, a63039; RV32XTHEADBB-NEXT: or a3, a4, a33040; RV32XTHEADBB-NEXT: add a0, a5, a23041; RV32XTHEADBB-NEXT: sltu a2, a0, a23042; RV32XTHEADBB-NEXT: add a1, a1, a33043; RV32XTHEADBB-NEXT: add a1, a1, a23044; RV32XTHEADBB-NEXT: ret3045;3046; RV64XTHEADBB-LABEL: rotr_64_mask_multiple:3047; RV64XTHEADBB: # %bb.0:3048; RV64XTHEADBB-NEXT: andi a3, a2, 633049; RV64XTHEADBB-NEXT: srl a4, a0, a23050; RV64XTHEADBB-NEXT: srl a2, a1, a23051; RV64XTHEADBB-NEXT: neg a3, a33052; RV64XTHEADBB-NEXT: sll a0, a0, a33053; RV64XTHEADBB-NEXT: sll a1, a1, a33054; RV64XTHEADBB-NEXT: or a0, a4, a03055; RV64XTHEADBB-NEXT: or a1, a2, a13056; RV64XTHEADBB-NEXT: add a0, a0, a13057; RV64XTHEADBB-NEXT: ret3058 %maskedamt = and i64 %amt, 633059 %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %maskedamt)3060 %2 = tail call i64 @llvm.fshr.i64(i64 %b, i64 %b, i64 %maskedamt)3061 %3 = add i64 %1, %23062 ret i64 %33063}3064 3065define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind {3066; RV32I-LABEL: rotl_64_zext:3067; RV32I: # %bb.0:3068; RV32I-NEXT: li a6, 643069; RV32I-NEXT: li a4, 323070; RV32I-NEXT: neg a5, a23071; RV32I-NEXT: srl a7, a0, a53072; RV32I-NEXT: bltu a2, a4, .LBB24_23073; RV32I-NEXT: # %bb.1:3074; RV32I-NEXT: li a3, 03075; RV32I-NEXT: sll t1, a0, a23076; RV32I-NEXT: j .LBB24_33077; RV32I-NEXT: .LBB24_2:3078; RV32I-NEXT: sll a3, a0, a23079; RV32I-NEXT: sll t0, a1, a23080; RV32I-NEXT: or t1, a7, t03081; RV32I-NEXT: .LBB24_3:3082; RV32I-NEXT: sub t0, a6, a23083; RV32I-NEXT: mv a6, a13084; RV32I-NEXT: beqz a2, .LBB24_53085; RV32I-NEXT: # %bb.4:3086; RV32I-NEXT: mv a6, t13087; RV32I-NEXT: .LBB24_5:3088; RV32I-NEXT: bltu t0, a4, .LBB24_73089; RV32I-NEXT: # %bb.6:3090; RV32I-NEXT: srl a2, a1, t03091; RV32I-NEXT: bnez t0, .LBB24_83092; RV32I-NEXT: j .LBB24_93093; RV32I-NEXT: .LBB24_7:3094; RV32I-NEXT: neg a2, t03095; RV32I-NEXT: sll a2, a1, a23096; RV32I-NEXT: or a2, a7, a23097; RV32I-NEXT: beqz t0, .LBB24_93098; RV32I-NEXT: .LBB24_8:3099; RV32I-NEXT: mv a0, a23100; RV32I-NEXT: .LBB24_9:3101; RV32I-NEXT: bltu t0, a4, .LBB24_113102; RV32I-NEXT: # %bb.10:3103; RV32I-NEXT: li a1, 03104; RV32I-NEXT: j .LBB24_123105; RV32I-NEXT: .LBB24_11:3106; RV32I-NEXT: srl a1, a1, a53107; RV32I-NEXT: .LBB24_12:3108; RV32I-NEXT: or a0, a3, a03109; RV32I-NEXT: or a1, a6, a13110; RV32I-NEXT: ret3111;3112; RV64I-LABEL: rotl_64_zext:3113; RV64I: # %bb.0:3114; RV64I-NEXT: li a2, 643115; RV64I-NEXT: sub a2, a2, a13116; RV64I-NEXT: sll a1, a0, a13117; RV64I-NEXT: srl a0, a0, a23118; RV64I-NEXT: or a0, a1, a03119; RV64I-NEXT: ret3120;3121; RV32ZBB-LABEL: rotl_64_zext:3122; RV32ZBB: # %bb.0:3123; RV32ZBB-NEXT: li a6, 643124; RV32ZBB-NEXT: li a4, 323125; RV32ZBB-NEXT: neg a5, a23126; RV32ZBB-NEXT: srl a7, a0, a53127; RV32ZBB-NEXT: bltu a2, a4, .LBB24_23128; RV32ZBB-NEXT: # %bb.1:3129; RV32ZBB-NEXT: li a3, 03130; RV32ZBB-NEXT: sll t1, a0, a23131; RV32ZBB-NEXT: j .LBB24_33132; RV32ZBB-NEXT: .LBB24_2:3133; RV32ZBB-NEXT: sll a3, a0, a23134; RV32ZBB-NEXT: sll t0, a1, a23135; RV32ZBB-NEXT: or t1, a7, t03136; RV32ZBB-NEXT: .LBB24_3:3137; RV32ZBB-NEXT: sub t0, a6, a23138; RV32ZBB-NEXT: mv a6, a13139; RV32ZBB-NEXT: beqz a2, .LBB24_53140; RV32ZBB-NEXT: # %bb.4:3141; RV32ZBB-NEXT: mv a6, t13142; RV32ZBB-NEXT: .LBB24_5:3143; RV32ZBB-NEXT: bltu t0, a4, .LBB24_73144; RV32ZBB-NEXT: # %bb.6:3145; RV32ZBB-NEXT: srl a2, a1, t03146; RV32ZBB-NEXT: bnez t0, .LBB24_83147; RV32ZBB-NEXT: j .LBB24_93148; RV32ZBB-NEXT: .LBB24_7:3149; RV32ZBB-NEXT: neg a2, t03150; RV32ZBB-NEXT: sll a2, a1, a23151; RV32ZBB-NEXT: or a2, a7, a23152; RV32ZBB-NEXT: beqz t0, .LBB24_93153; RV32ZBB-NEXT: .LBB24_8:3154; RV32ZBB-NEXT: mv a0, a23155; RV32ZBB-NEXT: .LBB24_9:3156; RV32ZBB-NEXT: bltu t0, a4, .LBB24_113157; RV32ZBB-NEXT: # %bb.10:3158; RV32ZBB-NEXT: li a1, 03159; RV32ZBB-NEXT: j .LBB24_123160; RV32ZBB-NEXT: .LBB24_11:3161; RV32ZBB-NEXT: srl a1, a1, a53162; RV32ZBB-NEXT: .LBB24_12:3163; RV32ZBB-NEXT: or a0, a3, a03164; RV32ZBB-NEXT: or a1, a6, a13165; RV32ZBB-NEXT: ret3166;3167; RV64ZBB-LABEL: rotl_64_zext:3168; RV64ZBB: # %bb.0:3169; RV64ZBB-NEXT: li a2, 643170; RV64ZBB-NEXT: sub a2, a2, a13171; RV64ZBB-NEXT: sll a1, a0, a13172; RV64ZBB-NEXT: srl a0, a0, a23173; RV64ZBB-NEXT: or a0, a1, a03174; RV64ZBB-NEXT: ret3175;3176; RV32XTHEADBB-LABEL: rotl_64_zext:3177; RV32XTHEADBB: # %bb.0:3178; RV32XTHEADBB-NEXT: li a6, 643179; RV32XTHEADBB-NEXT: li a4, 323180; RV32XTHEADBB-NEXT: neg a5, a23181; RV32XTHEADBB-NEXT: srl a7, a0, a53182; RV32XTHEADBB-NEXT: bltu a2, a4, .LBB24_23183; RV32XTHEADBB-NEXT: # %bb.1:3184; RV32XTHEADBB-NEXT: li a3, 03185; RV32XTHEADBB-NEXT: sll t1, a0, a23186; RV32XTHEADBB-NEXT: j .LBB24_33187; RV32XTHEADBB-NEXT: .LBB24_2:3188; RV32XTHEADBB-NEXT: sll a3, a0, a23189; RV32XTHEADBB-NEXT: sll t0, a1, a23190; RV32XTHEADBB-NEXT: or t1, a7, t03191; RV32XTHEADBB-NEXT: .LBB24_3:3192; RV32XTHEADBB-NEXT: sub t0, a6, a23193; RV32XTHEADBB-NEXT: mv a6, a13194; RV32XTHEADBB-NEXT: beqz a2, .LBB24_53195; RV32XTHEADBB-NEXT: # %bb.4:3196; RV32XTHEADBB-NEXT: mv a6, t13197; RV32XTHEADBB-NEXT: .LBB24_5:3198; RV32XTHEADBB-NEXT: bltu t0, a4, .LBB24_73199; RV32XTHEADBB-NEXT: # %bb.6:3200; RV32XTHEADBB-NEXT: srl a2, a1, t03201; RV32XTHEADBB-NEXT: bnez t0, .LBB24_83202; RV32XTHEADBB-NEXT: j .LBB24_93203; RV32XTHEADBB-NEXT: .LBB24_7:3204; RV32XTHEADBB-NEXT: neg a2, t03205; RV32XTHEADBB-NEXT: sll a2, a1, a23206; RV32XTHEADBB-NEXT: or a2, a7, a23207; RV32XTHEADBB-NEXT: beqz t0, .LBB24_93208; RV32XTHEADBB-NEXT: .LBB24_8:3209; RV32XTHEADBB-NEXT: mv a0, a23210; RV32XTHEADBB-NEXT: .LBB24_9:3211; RV32XTHEADBB-NEXT: bltu t0, a4, .LBB24_113212; RV32XTHEADBB-NEXT: # %bb.10:3213; RV32XTHEADBB-NEXT: li a1, 03214; RV32XTHEADBB-NEXT: j .LBB24_123215; RV32XTHEADBB-NEXT: .LBB24_11:3216; RV32XTHEADBB-NEXT: srl a1, a1, a53217; RV32XTHEADBB-NEXT: .LBB24_12:3218; RV32XTHEADBB-NEXT: or a0, a3, a03219; RV32XTHEADBB-NEXT: or a1, a6, a13220; RV32XTHEADBB-NEXT: ret3221;3222; RV64XTHEADBB-LABEL: rotl_64_zext:3223; RV64XTHEADBB: # %bb.0:3224; RV64XTHEADBB-NEXT: li a2, 643225; RV64XTHEADBB-NEXT: sub a2, a2, a13226; RV64XTHEADBB-NEXT: sll a1, a0, a13227; RV64XTHEADBB-NEXT: srl a0, a0, a23228; RV64XTHEADBB-NEXT: or a0, a1, a03229; RV64XTHEADBB-NEXT: ret3230 %z = sub i32 64, %y3231 %zext = zext i32 %z to i643232 %zexty = zext i32 %y to i643233 %b = shl i64 %x, %zexty3234 %c = lshr i64 %x, %zext3235 %d = or i64 %b, %c3236 ret i64 %d3237}3238 3239define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind {3240; RV32I-LABEL: rotr_64_zext:3241; RV32I: # %bb.0:3242; RV32I-NEXT: li a5, 323243; RV32I-NEXT: neg a6, a23244; RV32I-NEXT: sll a4, a1, a63245; RV32I-NEXT: bltu a2, a5, .LBB25_23246; RV32I-NEXT: # %bb.1:3247; RV32I-NEXT: srl a7, a1, a23248; RV32I-NEXT: j .LBB25_33249; RV32I-NEXT: .LBB25_2:3250; RV32I-NEXT: srl a3, a0, a23251; RV32I-NEXT: or a7, a3, a43252; RV32I-NEXT: .LBB25_3:3253; RV32I-NEXT: li t0, 643254; RV32I-NEXT: mv a3, a03255; RV32I-NEXT: beqz a2, .LBB25_53256; RV32I-NEXT: # %bb.4:3257; RV32I-NEXT: mv a3, a73258; RV32I-NEXT: .LBB25_5:3259; RV32I-NEXT: sub a7, t0, a23260; RV32I-NEXT: bltu a2, a5, .LBB25_83261; RV32I-NEXT: # %bb.6:3262; RV32I-NEXT: li a2, 03263; RV32I-NEXT: bgeu a7, a5, .LBB25_93264; RV32I-NEXT: .LBB25_7:3265; RV32I-NEXT: sll a5, a0, a63266; RV32I-NEXT: neg a6, a73267; RV32I-NEXT: srl a0, a0, a63268; RV32I-NEXT: or a0, a0, a43269; RV32I-NEXT: bnez a7, .LBB25_103270; RV32I-NEXT: j .LBB25_113271; RV32I-NEXT: .LBB25_8:3272; RV32I-NEXT: srl a2, a1, a23273; RV32I-NEXT: bltu a7, a5, .LBB25_73274; RV32I-NEXT: .LBB25_9:3275; RV32I-NEXT: li a5, 03276; RV32I-NEXT: sll a0, a0, a73277; RV32I-NEXT: beqz a7, .LBB25_113278; RV32I-NEXT: .LBB25_10:3279; RV32I-NEXT: mv a1, a03280; RV32I-NEXT: .LBB25_11:3281; RV32I-NEXT: or a0, a3, a53282; RV32I-NEXT: or a1, a2, a13283; RV32I-NEXT: ret3284;3285; RV64I-LABEL: rotr_64_zext:3286; RV64I: # %bb.0:3287; RV64I-NEXT: li a2, 643288; RV64I-NEXT: sub a2, a2, a13289; RV64I-NEXT: srl a1, a0, a13290; RV64I-NEXT: sll a0, a0, a23291; RV64I-NEXT: or a0, a1, a03292; RV64I-NEXT: ret3293;3294; RV32ZBB-LABEL: rotr_64_zext:3295; RV32ZBB: # %bb.0:3296; RV32ZBB-NEXT: li a5, 323297; RV32ZBB-NEXT: neg a6, a23298; RV32ZBB-NEXT: sll a4, a1, a63299; RV32ZBB-NEXT: bltu a2, a5, .LBB25_23300; RV32ZBB-NEXT: # %bb.1:3301; RV32ZBB-NEXT: srl a7, a1, a23302; RV32ZBB-NEXT: j .LBB25_33303; RV32ZBB-NEXT: .LBB25_2:3304; RV32ZBB-NEXT: srl a3, a0, a23305; RV32ZBB-NEXT: or a7, a3, a43306; RV32ZBB-NEXT: .LBB25_3:3307; RV32ZBB-NEXT: li t0, 643308; RV32ZBB-NEXT: mv a3, a03309; RV32ZBB-NEXT: beqz a2, .LBB25_53310; RV32ZBB-NEXT: # %bb.4:3311; RV32ZBB-NEXT: mv a3, a73312; RV32ZBB-NEXT: .LBB25_5:3313; RV32ZBB-NEXT: sub a7, t0, a23314; RV32ZBB-NEXT: bltu a2, a5, .LBB25_83315; RV32ZBB-NEXT: # %bb.6:3316; RV32ZBB-NEXT: li a2, 03317; RV32ZBB-NEXT: bgeu a7, a5, .LBB25_93318; RV32ZBB-NEXT: .LBB25_7:3319; RV32ZBB-NEXT: sll a5, a0, a63320; RV32ZBB-NEXT: neg a6, a73321; RV32ZBB-NEXT: srl a0, a0, a63322; RV32ZBB-NEXT: or a0, a0, a43323; RV32ZBB-NEXT: bnez a7, .LBB25_103324; RV32ZBB-NEXT: j .LBB25_113325; RV32ZBB-NEXT: .LBB25_8:3326; RV32ZBB-NEXT: srl a2, a1, a23327; RV32ZBB-NEXT: bltu a7, a5, .LBB25_73328; RV32ZBB-NEXT: .LBB25_9:3329; RV32ZBB-NEXT: li a5, 03330; RV32ZBB-NEXT: sll a0, a0, a73331; RV32ZBB-NEXT: beqz a7, .LBB25_113332; RV32ZBB-NEXT: .LBB25_10:3333; RV32ZBB-NEXT: mv a1, a03334; RV32ZBB-NEXT: .LBB25_11:3335; RV32ZBB-NEXT: or a0, a3, a53336; RV32ZBB-NEXT: or a1, a2, a13337; RV32ZBB-NEXT: ret3338;3339; RV64ZBB-LABEL: rotr_64_zext:3340; RV64ZBB: # %bb.0:3341; RV64ZBB-NEXT: li a2, 643342; RV64ZBB-NEXT: sub a2, a2, a13343; RV64ZBB-NEXT: srl a1, a0, a13344; RV64ZBB-NEXT: sll a0, a0, a23345; RV64ZBB-NEXT: or a0, a1, a03346; RV64ZBB-NEXT: ret3347;3348; RV32XTHEADBB-LABEL: rotr_64_zext:3349; RV32XTHEADBB: # %bb.0:3350; RV32XTHEADBB-NEXT: li a5, 323351; RV32XTHEADBB-NEXT: neg a6, a23352; RV32XTHEADBB-NEXT: sll a4, a1, a63353; RV32XTHEADBB-NEXT: bltu a2, a5, .LBB25_23354; RV32XTHEADBB-NEXT: # %bb.1:3355; RV32XTHEADBB-NEXT: srl a7, a1, a23356; RV32XTHEADBB-NEXT: j .LBB25_33357; RV32XTHEADBB-NEXT: .LBB25_2:3358; RV32XTHEADBB-NEXT: srl a3, a0, a23359; RV32XTHEADBB-NEXT: or a7, a3, a43360; RV32XTHEADBB-NEXT: .LBB25_3:3361; RV32XTHEADBB-NEXT: li t0, 643362; RV32XTHEADBB-NEXT: mv a3, a03363; RV32XTHEADBB-NEXT: beqz a2, .LBB25_53364; RV32XTHEADBB-NEXT: # %bb.4:3365; RV32XTHEADBB-NEXT: mv a3, a73366; RV32XTHEADBB-NEXT: .LBB25_5:3367; RV32XTHEADBB-NEXT: sub a7, t0, a23368; RV32XTHEADBB-NEXT: bltu a2, a5, .LBB25_83369; RV32XTHEADBB-NEXT: # %bb.6:3370; RV32XTHEADBB-NEXT: li a2, 03371; RV32XTHEADBB-NEXT: bgeu a7, a5, .LBB25_93372; RV32XTHEADBB-NEXT: .LBB25_7:3373; RV32XTHEADBB-NEXT: sll a5, a0, a63374; RV32XTHEADBB-NEXT: neg a6, a73375; RV32XTHEADBB-NEXT: srl a0, a0, a63376; RV32XTHEADBB-NEXT: or a0, a0, a43377; RV32XTHEADBB-NEXT: bnez a7, .LBB25_103378; RV32XTHEADBB-NEXT: j .LBB25_113379; RV32XTHEADBB-NEXT: .LBB25_8:3380; RV32XTHEADBB-NEXT: srl a2, a1, a23381; RV32XTHEADBB-NEXT: bltu a7, a5, .LBB25_73382; RV32XTHEADBB-NEXT: .LBB25_9:3383; RV32XTHEADBB-NEXT: li a5, 03384; RV32XTHEADBB-NEXT: sll a0, a0, a73385; RV32XTHEADBB-NEXT: beqz a7, .LBB25_113386; RV32XTHEADBB-NEXT: .LBB25_10:3387; RV32XTHEADBB-NEXT: mv a1, a03388; RV32XTHEADBB-NEXT: .LBB25_11:3389; RV32XTHEADBB-NEXT: or a0, a3, a53390; RV32XTHEADBB-NEXT: or a1, a2, a13391; RV32XTHEADBB-NEXT: ret3392;3393; RV64XTHEADBB-LABEL: rotr_64_zext:3394; RV64XTHEADBB: # %bb.0:3395; RV64XTHEADBB-NEXT: li a2, 643396; RV64XTHEADBB-NEXT: sub a2, a2, a13397; RV64XTHEADBB-NEXT: srl a1, a0, a13398; RV64XTHEADBB-NEXT: sll a0, a0, a23399; RV64XTHEADBB-NEXT: or a0, a1, a03400; RV64XTHEADBB-NEXT: ret3401 %z = sub i32 64, %y3402 %zext = zext i32 %z to i643403 %zexty = zext i32 %y to i643404 %b = lshr i64 %x, %zexty3405 %c = shl i64 %x, %zext3406 %d = or i64 %b, %c3407 ret i64 %d3408}3409