173 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -global-isel -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -global-isel -mattr=+m,+zba -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBA6 7define signext i16 @sh1add(i64 %0, ptr %1) {8; RV32I-LABEL: sh1add:9; RV32I: # %bb.0:10; RV32I-NEXT: slli a0, a0, 111; RV32I-NEXT: add a0, a2, a012; RV32I-NEXT: lh a0, 0(a0)13; RV32I-NEXT: ret14;15; RV32ZBA-LABEL: sh1add:16; RV32ZBA: # %bb.0:17; RV32ZBA-NEXT: sh1add a0, a0, a218; RV32ZBA-NEXT: lh a0, 0(a0)19; RV32ZBA-NEXT: ret20 %3 = getelementptr inbounds i16, ptr %1, i64 %021 %4 = load i16, ptr %322 ret i16 %423}24 25define i32 @sh2add(i64 %0, ptr %1) {26; RV32I-LABEL: sh2add:27; RV32I: # %bb.0:28; RV32I-NEXT: slli a0, a0, 229; RV32I-NEXT: add a0, a2, a030; RV32I-NEXT: lw a0, 0(a0)31; RV32I-NEXT: ret32;33; RV32ZBA-LABEL: sh2add:34; RV32ZBA: # %bb.0:35; RV32ZBA-NEXT: sh2add a0, a0, a236; RV32ZBA-NEXT: lw a0, 0(a0)37; RV32ZBA-NEXT: ret38 %3 = getelementptr inbounds i32, ptr %1, i64 %039 %4 = load i32, ptr %340 ret i32 %441}42 43define i64 @sh3add(i64 %0, ptr %1) {44; RV32I-LABEL: sh3add:45; RV32I: # %bb.0:46; RV32I-NEXT: slli a0, a0, 347; RV32I-NEXT: add a2, a2, a048; RV32I-NEXT: lw a0, 0(a2)49; RV32I-NEXT: lw a1, 4(a2)50; RV32I-NEXT: ret51;52; RV32ZBA-LABEL: sh3add:53; RV32ZBA: # %bb.0:54; RV32ZBA-NEXT: sh3add a1, a0, a255; RV32ZBA-NEXT: lw a0, 0(a1)56; RV32ZBA-NEXT: lw a1, 4(a1)57; RV32ZBA-NEXT: ret58 %3 = getelementptr inbounds i64, ptr %1, i64 %059 %4 = load i64, ptr %360 ret i64 %461}62 63define i32 @srli_1_sh2add(ptr %0, i32 %1) {64; RV32I-LABEL: srli_1_sh2add:65; RV32I: # %bb.0:66; RV32I-NEXT: srli a1, a1, 167; RV32I-NEXT: slli a1, a1, 268; RV32I-NEXT: add a0, a0, a169; RV32I-NEXT: lw a0, 0(a0)70; RV32I-NEXT: ret71;72; RV32ZBA-LABEL: srli_1_sh2add:73; RV32ZBA: # %bb.0:74; RV32ZBA-NEXT: srli a1, a1, 175; RV32ZBA-NEXT: sh2add a0, a1, a076; RV32ZBA-NEXT: lw a0, 0(a0)77; RV32ZBA-NEXT: ret78 %3 = lshr i32 %1, 179 %4 = getelementptr inbounds i32, ptr %0, i32 %380 %5 = load i32, ptr %4, align 481 ret i32 %582}83 84define i64 @srli_2_sh3add(ptr %0, i32 %1) {85; RV32I-LABEL: srli_2_sh3add:86; RV32I: # %bb.0:87; RV32I-NEXT: srli a1, a1, 288; RV32I-NEXT: slli a1, a1, 389; RV32I-NEXT: add a1, a0, a190; RV32I-NEXT: lw a0, 0(a1)91; RV32I-NEXT: lw a1, 4(a1)92; RV32I-NEXT: ret93;94; RV32ZBA-LABEL: srli_2_sh3add:95; RV32ZBA: # %bb.0:96; RV32ZBA-NEXT: srli a1, a1, 297; RV32ZBA-NEXT: sh3add a1, a1, a098; RV32ZBA-NEXT: lw a0, 0(a1)99; RV32ZBA-NEXT: lw a1, 4(a1)100; RV32ZBA-NEXT: ret101 %3 = lshr i32 %1, 2102 %4 = getelementptr inbounds i64, ptr %0, i32 %3103 %5 = load i64, ptr %4, align 8104 ret i64 %5105}106 107define signext i16 @srli_2_sh1add(ptr %0, i32 %1) {108; RV32I-LABEL: srli_2_sh1add:109; RV32I: # %bb.0:110; RV32I-NEXT: srli a1, a1, 2111; RV32I-NEXT: slli a1, a1, 1112; RV32I-NEXT: add a0, a0, a1113; RV32I-NEXT: lh a0, 0(a0)114; RV32I-NEXT: ret115;116; RV32ZBA-LABEL: srli_2_sh1add:117; RV32ZBA: # %bb.0:118; RV32ZBA-NEXT: srli a1, a1, 2119; RV32ZBA-NEXT: sh1add a0, a1, a0120; RV32ZBA-NEXT: lh a0, 0(a0)121; RV32ZBA-NEXT: ret122 %3 = lshr i32 %1, 2123 %4 = getelementptr inbounds i16, ptr %0, i32 %3124 %5 = load i16, ptr %4, align 2125 ret i16 %5126}127 128define i32 @srli_3_sh2add(ptr %0, i32 %1) {129; RV32I-LABEL: srli_3_sh2add:130; RV32I: # %bb.0:131; RV32I-NEXT: srli a1, a1, 3132; RV32I-NEXT: slli a1, a1, 2133; RV32I-NEXT: add a0, a0, a1134; RV32I-NEXT: lw a0, 0(a0)135; RV32I-NEXT: ret136;137; RV32ZBA-LABEL: srli_3_sh2add:138; RV32ZBA: # %bb.0:139; RV32ZBA-NEXT: srli a1, a1, 3140; RV32ZBA-NEXT: sh2add a0, a1, a0141; RV32ZBA-NEXT: lw a0, 0(a0)142; RV32ZBA-NEXT: ret143 %3 = lshr i32 %1, 3144 %4 = getelementptr inbounds i32, ptr %0, i32 %3145 %5 = load i32, ptr %4, align 4146 ret i32 %5147}148 149define i64 @srli_4_sh3add(ptr %0, i32 %1) {150; RV32I-LABEL: srli_4_sh3add:151; RV32I: # %bb.0:152; RV32I-NEXT: srli a1, a1, 4153; RV32I-NEXT: slli a1, a1, 3154; RV32I-NEXT: add a1, a0, a1155; RV32I-NEXT: lw a0, 0(a1)156; RV32I-NEXT: lw a1, 4(a1)157; RV32I-NEXT: ret158;159; RV32ZBA-LABEL: srli_4_sh3add:160; RV32ZBA: # %bb.0:161; RV32ZBA-NEXT: srli a1, a1, 4162; RV32ZBA-NEXT: sh3add a1, a1, a0163; RV32ZBA-NEXT: lw a0, 0(a1)164; RV32ZBA-NEXT: lw a1, 4(a1)165; RV32ZBA-NEXT: ret166 %3 = lshr i32 %1, 4167 %4 = getelementptr inbounds i64, ptr %0, i32 %3168 %5 = load i64, ptr %4, align 8169 ret i64 %5170}171;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:172; CHECK: {{.*}}173