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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I4; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB6 7define i32 @ctlz_i32(i32 %a) nounwind {8; RV32I-LABEL: ctlz_i32:9; RV32I: # %bb.0:10; RV32I-NEXT: beqz a0, .LBB0_211; RV32I-NEXT: # %bb.1: # %cond.false12; RV32I-NEXT: srli a1, a0, 113; RV32I-NEXT: lui a2, 34952514; RV32I-NEXT: or a0, a0, a115; RV32I-NEXT: addi a1, a2, 136516; RV32I-NEXT: srli a2, a0, 217; RV32I-NEXT: or a0, a0, a218; RV32I-NEXT: srli a2, a0, 419; RV32I-NEXT: or a0, a0, a220; RV32I-NEXT: srli a2, a0, 821; RV32I-NEXT: or a0, a0, a222; RV32I-NEXT: srli a2, a0, 1623; RV32I-NEXT: or a0, a0, a224; RV32I-NEXT: srli a2, a0, 125; RV32I-NEXT: and a1, a2, a126; RV32I-NEXT: lui a2, 20971527; RV32I-NEXT: addi a2, a2, 81928; RV32I-NEXT: sub a0, a0, a129; RV32I-NEXT: srli a1, a0, 230; RV32I-NEXT: and a0, a0, a231; RV32I-NEXT: and a1, a1, a232; RV32I-NEXT: lui a2, 6168133; RV32I-NEXT: addi a2, a2, -24134; RV32I-NEXT: add a0, a1, a035; RV32I-NEXT: srli a1, a0, 436; RV32I-NEXT: add a0, a1, a037; RV32I-NEXT: and a0, a0, a238; RV32I-NEXT: slli a1, a0, 839; RV32I-NEXT: add a0, a0, a140; RV32I-NEXT: slli a1, a0, 1641; RV32I-NEXT: add a0, a0, a142; RV32I-NEXT: srli a0, a0, 2443; RV32I-NEXT: li a1, 3244; RV32I-NEXT: sub a0, a1, a045; RV32I-NEXT: ret46; RV32I-NEXT: .LBB0_2:47; RV32I-NEXT: li a0, 3248; RV32I-NEXT: ret49;50; RV32ZBB-LABEL: ctlz_i32:51; RV32ZBB: # %bb.0:52; RV32ZBB-NEXT: clz a0, a053; RV32ZBB-NEXT: ret54 %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)55 ret i32 %156}57 58define i64 @ctlz_i64(i64 %a) nounwind {59; RV32I-LABEL: ctlz_i64:60; RV32I: # %bb.0:61; RV32I-NEXT: or a2, a0, a162; RV32I-NEXT: beqz a2, .LBB1_363; RV32I-NEXT: # %bb.1: # %cond.false64; RV32I-NEXT: lui a2, 34952565; RV32I-NEXT: lui a3, 20971566; RV32I-NEXT: lui a6, 6168167; RV32I-NEXT: addi a5, a2, 136568; RV32I-NEXT: addi a4, a3, 81969; RV32I-NEXT: addi a3, a6, -24170; RV32I-NEXT: li a2, 3271; RV32I-NEXT: beqz a1, .LBB1_472; RV32I-NEXT: # %bb.2: # %cond.false73; RV32I-NEXT: srli a0, a1, 174; RV32I-NEXT: or a0, a1, a075; RV32I-NEXT: srli a1, a0, 276; RV32I-NEXT: or a0, a0, a177; RV32I-NEXT: srli a1, a0, 478; RV32I-NEXT: or a0, a0, a179; RV32I-NEXT: srli a1, a0, 880; RV32I-NEXT: or a0, a0, a181; RV32I-NEXT: srli a1, a0, 1682; RV32I-NEXT: or a0, a0, a183; RV32I-NEXT: srli a1, a0, 184; RV32I-NEXT: and a1, a1, a585; RV32I-NEXT: sub a0, a0, a186; RV32I-NEXT: srli a1, a0, 287; RV32I-NEXT: and a1, a1, a488; RV32I-NEXT: and a0, a0, a489; RV32I-NEXT: add a0, a1, a090; RV32I-NEXT: srli a1, a0, 491; RV32I-NEXT: add a0, a1, a092; RV32I-NEXT: and a0, a0, a393; RV32I-NEXT: slli a1, a0, 894; RV32I-NEXT: add a0, a0, a195; RV32I-NEXT: slli a1, a0, 1696; RV32I-NEXT: add a0, a0, a197; RV32I-NEXT: srli a0, a0, 2498; RV32I-NEXT: sub a0, a2, a099; RV32I-NEXT: li a1, 0100; RV32I-NEXT: ret101; RV32I-NEXT: .LBB1_3:102; RV32I-NEXT: li a1, 0103; RV32I-NEXT: li a0, 64104; RV32I-NEXT: ret105; RV32I-NEXT: .LBB1_4:106; RV32I-NEXT: srli a1, a0, 1107; RV32I-NEXT: or a0, a0, a1108; RV32I-NEXT: srli a1, a0, 2109; RV32I-NEXT: or a0, a0, a1110; RV32I-NEXT: srli a1, a0, 4111; RV32I-NEXT: or a0, a0, a1112; RV32I-NEXT: srli a1, a0, 8113; RV32I-NEXT: or a0, a0, a1114; RV32I-NEXT: srli a1, a0, 16115; RV32I-NEXT: or a0, a0, a1116; RV32I-NEXT: srli a1, a0, 1117; RV32I-NEXT: and a1, a1, a5118; RV32I-NEXT: sub a0, a0, a1119; RV32I-NEXT: srli a1, a0, 2120; RV32I-NEXT: and a1, a1, a4121; RV32I-NEXT: and a0, a0, a4122; RV32I-NEXT: add a0, a1, a0123; RV32I-NEXT: srli a1, a0, 4124; RV32I-NEXT: add a0, a1, a0125; RV32I-NEXT: and a0, a0, a3126; RV32I-NEXT: slli a1, a0, 8127; RV32I-NEXT: add a0, a0, a1128; RV32I-NEXT: slli a1, a0, 16129; RV32I-NEXT: add a0, a0, a1130; RV32I-NEXT: srli a0, a0, 24131; RV32I-NEXT: sub a2, a2, a0132; RV32I-NEXT: addi a0, a2, 32133; RV32I-NEXT: li a1, 0134; RV32I-NEXT: ret135;136; RV32ZBB-LABEL: ctlz_i64:137; RV32ZBB: # %bb.0:138; RV32ZBB-NEXT: beqz a1, .LBB1_2139; RV32ZBB-NEXT: # %bb.1:140; RV32ZBB-NEXT: clz a0, a1141; RV32ZBB-NEXT: li a1, 0142; RV32ZBB-NEXT: ret143; RV32ZBB-NEXT: .LBB1_2:144; RV32ZBB-NEXT: clz a0, a0145; RV32ZBB-NEXT: addi a0, a0, 32146; RV32ZBB-NEXT: li a1, 0147; RV32ZBB-NEXT: ret148 %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)149 ret i64 %1150}151 152define i32 @cttz_i32(i32 %a) nounwind {153; RV32I-LABEL: cttz_i32:154; RV32I: # %bb.0:155; RV32I-NEXT: beqz a0, .LBB2_2156; RV32I-NEXT: # %bb.1: # %cond.false157; RV32I-NEXT: not a1, a0158; RV32I-NEXT: addi a0, a0, -1159; RV32I-NEXT: lui a2, 349525160; RV32I-NEXT: and a0, a1, a0161; RV32I-NEXT: addi a1, a2, 1365162; RV32I-NEXT: srli a2, a0, 1163; RV32I-NEXT: and a1, a2, a1164; RV32I-NEXT: lui a2, 209715165; RV32I-NEXT: addi a2, a2, 819166; RV32I-NEXT: sub a0, a0, a1167; RV32I-NEXT: srli a1, a0, 2168; RV32I-NEXT: and a0, a0, a2169; RV32I-NEXT: and a1, a1, a2170; RV32I-NEXT: lui a2, 61681171; RV32I-NEXT: add a0, a1, a0172; RV32I-NEXT: srli a1, a0, 4173; RV32I-NEXT: add a0, a1, a0174; RV32I-NEXT: addi a1, a2, -241175; RV32I-NEXT: and a0, a0, a1176; RV32I-NEXT: slli a1, a0, 8177; RV32I-NEXT: add a0, a0, a1178; RV32I-NEXT: slli a1, a0, 16179; RV32I-NEXT: add a0, a0, a1180; RV32I-NEXT: srli a0, a0, 24181; RV32I-NEXT: ret182; RV32I-NEXT: .LBB2_2:183; RV32I-NEXT: li a0, 32184; RV32I-NEXT: ret185;186; RV32ZBB-LABEL: cttz_i32:187; RV32ZBB: # %bb.0:188; RV32ZBB-NEXT: ctz a0, a0189; RV32ZBB-NEXT: ret190 %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false)191 ret i32 %1192}193 194define i64 @cttz_i64(i64 %a) nounwind {195; RV32I-LABEL: cttz_i64:196; RV32I: # %bb.0:197; RV32I-NEXT: or a2, a0, a1198; RV32I-NEXT: beqz a2, .LBB3_3199; RV32I-NEXT: # %bb.1: # %cond.false200; RV32I-NEXT: lui a2, 349525201; RV32I-NEXT: lui a3, 209715202; RV32I-NEXT: lui a5, 61681203; RV32I-NEXT: addi a4, a2, 1365204; RV32I-NEXT: addi a3, a3, 819205; RV32I-NEXT: addi a2, a5, -241206; RV32I-NEXT: beqz a0, .LBB3_4207; RV32I-NEXT: # %bb.2: # %cond.false208; RV32I-NEXT: not a1, a0209; RV32I-NEXT: addi a0, a0, -1210; RV32I-NEXT: and a0, a1, a0211; RV32I-NEXT: srli a1, a0, 1212; RV32I-NEXT: and a1, a1, a4213; RV32I-NEXT: sub a0, a0, a1214; RV32I-NEXT: srli a1, a0, 2215; RV32I-NEXT: and a1, a1, a3216; RV32I-NEXT: and a0, a0, a3217; RV32I-NEXT: add a0, a1, a0218; RV32I-NEXT: srli a1, a0, 4219; RV32I-NEXT: add a0, a1, a0220; RV32I-NEXT: and a0, a0, a2221; RV32I-NEXT: slli a1, a0, 8222; RV32I-NEXT: add a0, a0, a1223; RV32I-NEXT: slli a1, a0, 16224; RV32I-NEXT: add a0, a0, a1225; RV32I-NEXT: srli a0, a0, 24226; RV32I-NEXT: li a1, 0227; RV32I-NEXT: ret228; RV32I-NEXT: .LBB3_3:229; RV32I-NEXT: li a1, 0230; RV32I-NEXT: li a0, 64231; RV32I-NEXT: ret232; RV32I-NEXT: .LBB3_4:233; RV32I-NEXT: not a0, a1234; RV32I-NEXT: addi a1, a1, -1235; RV32I-NEXT: and a0, a0, a1236; RV32I-NEXT: srli a1, a0, 1237; RV32I-NEXT: and a1, a1, a4238; RV32I-NEXT: sub a0, a0, a1239; RV32I-NEXT: srli a1, a0, 2240; RV32I-NEXT: and a1, a1, a3241; RV32I-NEXT: and a0, a0, a3242; RV32I-NEXT: add a0, a1, a0243; RV32I-NEXT: srli a1, a0, 4244; RV32I-NEXT: add a0, a1, a0245; RV32I-NEXT: and a0, a0, a2246; RV32I-NEXT: slli a1, a0, 8247; RV32I-NEXT: add a0, a0, a1248; RV32I-NEXT: slli a1, a0, 16249; RV32I-NEXT: add a0, a0, a1250; RV32I-NEXT: srli a0, a0, 24251; RV32I-NEXT: addi a0, a0, 32252; RV32I-NEXT: li a1, 0253; RV32I-NEXT: ret254;255; RV32ZBB-LABEL: cttz_i64:256; RV32ZBB: # %bb.0:257; RV32ZBB-NEXT: beqz a0, .LBB3_2258; RV32ZBB-NEXT: # %bb.1:259; RV32ZBB-NEXT: ctz a0, a0260; RV32ZBB-NEXT: li a1, 0261; RV32ZBB-NEXT: ret262; RV32ZBB-NEXT: .LBB3_2:263; RV32ZBB-NEXT: ctz a0, a1264; RV32ZBB-NEXT: addi a0, a0, 32265; RV32ZBB-NEXT: li a1, 0266; RV32ZBB-NEXT: ret267 %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)268 ret i64 %1269}270 271define i32 @ctpop_i32(i32 %a) nounwind {272; RV32I-LABEL: ctpop_i32:273; RV32I: # %bb.0:274; RV32I-NEXT: srli a1, a0, 1275; RV32I-NEXT: lui a2, 349525276; RV32I-NEXT: addi a2, a2, 1365277; RV32I-NEXT: and a1, a1, a2278; RV32I-NEXT: lui a2, 209715279; RV32I-NEXT: addi a2, a2, 819280; RV32I-NEXT: sub a0, a0, a1281; RV32I-NEXT: srli a1, a0, 2282; RV32I-NEXT: and a0, a0, a2283; RV32I-NEXT: and a1, a1, a2284; RV32I-NEXT: lui a2, 61681285; RV32I-NEXT: add a0, a1, a0286; RV32I-NEXT: srli a1, a0, 4287; RV32I-NEXT: add a0, a1, a0288; RV32I-NEXT: addi a1, a2, -241289; RV32I-NEXT: and a0, a0, a1290; RV32I-NEXT: slli a1, a0, 8291; RV32I-NEXT: add a0, a0, a1292; RV32I-NEXT: slli a1, a0, 16293; RV32I-NEXT: add a0, a0, a1294; RV32I-NEXT: srli a0, a0, 24295; RV32I-NEXT: ret296;297; RV32ZBB-LABEL: ctpop_i32:298; RV32ZBB: # %bb.0:299; RV32ZBB-NEXT: cpop a0, a0300; RV32ZBB-NEXT: ret301 %1 = call i32 @llvm.ctpop.i32(i32 %a)302 ret i32 %1303}304 305define i64 @ctpop_i64(i64 %a) nounwind {306; RV32I-LABEL: ctpop_i64:307; RV32I: # %bb.0:308; RV32I-NEXT: srli a2, a0, 1309; RV32I-NEXT: lui a3, 349525310; RV32I-NEXT: lui a4, 209715311; RV32I-NEXT: srli a5, a1, 1312; RV32I-NEXT: addi a3, a3, 1365313; RV32I-NEXT: and a2, a2, a3314; RV32I-NEXT: and a3, a5, a3315; RV32I-NEXT: lui a5, 61681316; RV32I-NEXT: addi a4, a4, 819317; RV32I-NEXT: addi a5, a5, -241318; RV32I-NEXT: sub a0, a0, a2319; RV32I-NEXT: sub a1, a1, a3320; RV32I-NEXT: srli a2, a0, 2321; RV32I-NEXT: and a0, a0, a4322; RV32I-NEXT: srli a3, a1, 2323; RV32I-NEXT: and a1, a1, a4324; RV32I-NEXT: and a2, a2, a4325; RV32I-NEXT: and a3, a3, a4326; RV32I-NEXT: add a0, a2, a0327; RV32I-NEXT: add a1, a3, a1328; RV32I-NEXT: srli a2, a0, 4329; RV32I-NEXT: srli a3, a1, 4330; RV32I-NEXT: add a0, a2, a0331; RV32I-NEXT: add a1, a3, a1332; RV32I-NEXT: and a0, a0, a5333; RV32I-NEXT: and a1, a1, a5334; RV32I-NEXT: slli a2, a0, 8335; RV32I-NEXT: slli a3, a1, 8336; RV32I-NEXT: add a0, a0, a2337; RV32I-NEXT: add a1, a1, a3338; RV32I-NEXT: slli a2, a0, 16339; RV32I-NEXT: slli a3, a1, 16340; RV32I-NEXT: add a0, a0, a2341; RV32I-NEXT: add a1, a1, a3342; RV32I-NEXT: srli a0, a0, 24343; RV32I-NEXT: srli a1, a1, 24344; RV32I-NEXT: add a0, a1, a0345; RV32I-NEXT: li a1, 0346; RV32I-NEXT: ret347;348; RV32ZBB-LABEL: ctpop_i64:349; RV32ZBB: # %bb.0:350; RV32ZBB-NEXT: cpop a0, a0351; RV32ZBB-NEXT: cpop a1, a1352; RV32ZBB-NEXT: add a0, a1, a0353; RV32ZBB-NEXT: li a1, 0354; RV32ZBB-NEXT: ret355 %1 = call i64 @llvm.ctpop.i64(i64 %a)356 ret i64 %1357}358 359define i1 @ctpop_i64_ugt_two(i64 %a) nounwind {360; RV32I-LABEL: ctpop_i64_ugt_two:361; RV32I: # %bb.0:362; RV32I-NEXT: addi a2, a0, -1363; RV32I-NEXT: addi a3, a1, -1364; RV32I-NEXT: sltiu a4, a2, -1365; RV32I-NEXT: add a3, a3, a4366; RV32I-NEXT: and a0, a0, a2367; RV32I-NEXT: and a1, a1, a3368; RV32I-NEXT: or a0, a0, a1369; RV32I-NEXT: seqz a0, a0370; RV32I-NEXT: ret371;372; RV32ZBB-LABEL: ctpop_i64_ugt_two:373; RV32ZBB: # %bb.0:374; RV32ZBB-NEXT: j .LBB6_2375; RV32ZBB-NEXT: # %bb.1:376; RV32ZBB-NEXT: li a0, 0377; RV32ZBB-NEXT: ret378; RV32ZBB-NEXT: .LBB6_2:379; RV32ZBB-NEXT: cpop a0, a0380; RV32ZBB-NEXT: cpop a1, a1381; RV32ZBB-NEXT: add a0, a1, a0382; RV32ZBB-NEXT: sltiu a0, a0, 2383; RV32ZBB-NEXT: ret384 %1 = call i64 @llvm.ctpop.i64(i64 %a)385 %2 = icmp ult i64 %1, 2386 ret i1 %2387}388 389define i1 @ctpop_i64_ugt_one(i64 %a) nounwind {390; RV32I-LABEL: ctpop_i64_ugt_one:391; RV32I: # %bb.0:392; RV32I-NEXT: addi a2, a0, -1393; RV32I-NEXT: addi a3, a1, -1394; RV32I-NEXT: sltiu a4, a2, -1395; RV32I-NEXT: add a3, a3, a4396; RV32I-NEXT: and a0, a0, a2397; RV32I-NEXT: and a1, a1, a3398; RV32I-NEXT: or a0, a0, a1399; RV32I-NEXT: snez a0, a0400; RV32I-NEXT: ret401;402; RV32ZBB-LABEL: ctpop_i64_ugt_one:403; RV32ZBB: # %bb.0:404; RV32ZBB-NEXT: j .LBB7_2405; RV32ZBB-NEXT: # %bb.1:406; RV32ZBB-NEXT: li a0, 0407; RV32ZBB-NEXT: ret408; RV32ZBB-NEXT: .LBB7_2:409; RV32ZBB-NEXT: cpop a0, a0410; RV32ZBB-NEXT: cpop a1, a1411; RV32ZBB-NEXT: add a0, a1, a0412; RV32ZBB-NEXT: sltiu a0, a0, 2413; RV32ZBB-NEXT: xori a0, a0, 1414; RV32ZBB-NEXT: ret415 %1 = call i64 @llvm.ctpop.i64(i64 %a)416 %2 = icmp ugt i64 %1, 1417 ret i1 %2418}419 420define i1 @ctpop_i64_eq_one(i64 %a) nounwind {421; RV32I-LABEL: ctpop_i64_eq_one:422; RV32I: # %bb.0:423; RV32I-NEXT: addi a2, a0, -1424; RV32I-NEXT: sltiu a3, a2, -1425; RV32I-NEXT: addi a4, a1, -1426; RV32I-NEXT: add a3, a4, a3427; RV32I-NEXT: xor a1, a1, a3428; RV32I-NEXT: beq a1, a3, .LBB8_2429; RV32I-NEXT: # %bb.1:430; RV32I-NEXT: sltu a0, a3, a1431; RV32I-NEXT: ret432; RV32I-NEXT: .LBB8_2:433; RV32I-NEXT: xor a0, a0, a2434; RV32I-NEXT: sltu a0, a2, a0435; RV32I-NEXT: ret436;437; RV32ZBB-LABEL: ctpop_i64_eq_one:438; RV32ZBB: # %bb.0:439; RV32ZBB-NEXT: cpop a0, a0440; RV32ZBB-NEXT: cpop a1, a1441; RV32ZBB-NEXT: add a0, a1, a0442; RV32ZBB-NEXT: xori a0, a0, 1443; RV32ZBB-NEXT: seqz a0, a0444; RV32ZBB-NEXT: ret445 %1 = call i64 @llvm.ctpop.i64(i64 %a)446 %2 = icmp eq i64 %1, 1447 ret i1 %2448}449 450define i1 @ctpop_i64_ne_one(i64 %a) nounwind {451; RV32I-LABEL: ctpop_i64_ne_one:452; RV32I: # %bb.0:453; RV32I-NEXT: addi a2, a0, -1454; RV32I-NEXT: sltiu a3, a2, -1455; RV32I-NEXT: addi a4, a1, -1456; RV32I-NEXT: add a3, a4, a3457; RV32I-NEXT: xor a1, a1, a3458; RV32I-NEXT: beq a1, a3, .LBB9_2459; RV32I-NEXT: # %bb.1:460; RV32I-NEXT: sltu a0, a3, a1461; RV32I-NEXT: xori a0, a0, 1462; RV32I-NEXT: ret463; RV32I-NEXT: .LBB9_2:464; RV32I-NEXT: xor a0, a0, a2465; RV32I-NEXT: sltu a0, a2, a0466; RV32I-NEXT: xori a0, a0, 1467; RV32I-NEXT: ret468;469; RV32ZBB-LABEL: ctpop_i64_ne_one:470; RV32ZBB: # %bb.0:471; RV32ZBB-NEXT: cpop a0, a0472; RV32ZBB-NEXT: cpop a1, a1473; RV32ZBB-NEXT: add a0, a1, a0474; RV32ZBB-NEXT: xori a0, a0, 1475; RV32ZBB-NEXT: snez a0, a0476; RV32ZBB-NEXT: ret477 %1 = call i64 @llvm.ctpop.i64(i64 %a)478 %2 = icmp ne i64 %1, 1479 ret i1 %2480}481 482define i32 @sextb_i32(i32 %a) nounwind {483; RV32I-LABEL: sextb_i32:484; RV32I: # %bb.0:485; RV32I-NEXT: slli a0, a0, 24486; RV32I-NEXT: srai a0, a0, 24487; RV32I-NEXT: ret488;489; RV32ZBB-LABEL: sextb_i32:490; RV32ZBB: # %bb.0:491; RV32ZBB-NEXT: sext.b a0, a0492; RV32ZBB-NEXT: ret493 %shl = shl i32 %a, 24494 %shr = ashr exact i32 %shl, 24495 ret i32 %shr496}497 498; FIXME: Combine back to back srai.499define i64 @sextb_i64(i64 %a) nounwind {500; RV32I-LABEL: sextb_i64:501; RV32I: # %bb.0:502; RV32I-NEXT: slli a1, a0, 24503; RV32I-NEXT: srai a0, a1, 24504; RV32I-NEXT: srai a1, a1, 31505; RV32I-NEXT: ret506;507; RV32ZBB-LABEL: sextb_i64:508; RV32ZBB: # %bb.0:509; RV32ZBB-NEXT: sext.b a0, a0510; RV32ZBB-NEXT: srai a1, a0, 31511; RV32ZBB-NEXT: ret512 %shl = shl i64 %a, 56513 %shr = ashr exact i64 %shl, 56514 ret i64 %shr515}516 517define i32 @sexth_i32(i32 %a) nounwind {518; RV32I-LABEL: sexth_i32:519; RV32I: # %bb.0:520; RV32I-NEXT: slli a0, a0, 16521; RV32I-NEXT: srai a0, a0, 16522; RV32I-NEXT: ret523;524; RV32ZBB-LABEL: sexth_i32:525; RV32ZBB: # %bb.0:526; RV32ZBB-NEXT: sext.h a0, a0527; RV32ZBB-NEXT: ret528 %shl = shl i32 %a, 16529 %shr = ashr exact i32 %shl, 16530 ret i32 %shr531}532 533; FIXME: Combine back to back srai.534define i64 @sexth_i64(i64 %a) nounwind {535; RV32I-LABEL: sexth_i64:536; RV32I: # %bb.0:537; RV32I-NEXT: slli a1, a0, 16538; RV32I-NEXT: srai a0, a1, 16539; RV32I-NEXT: srai a1, a1, 31540; RV32I-NEXT: ret541;542; RV32ZBB-LABEL: sexth_i64:543; RV32ZBB: # %bb.0:544; RV32ZBB-NEXT: sext.h a0, a0545; RV32ZBB-NEXT: srai a1, a0, 31546; RV32ZBB-NEXT: ret547 %shl = shl i64 %a, 48548 %shr = ashr exact i64 %shl, 48549 ret i64 %shr550}551 552define i32 @min_i32(i32 %a, i32 %b) nounwind {553; RV32I-LABEL: min_i32:554; RV32I: # %bb.0:555; RV32I-NEXT: blt a0, a1, .LBB14_2556; RV32I-NEXT: # %bb.1:557; RV32I-NEXT: mv a0, a1558; RV32I-NEXT: .LBB14_2:559; RV32I-NEXT: ret560;561; RV32ZBB-LABEL: min_i32:562; RV32ZBB: # %bb.0:563; RV32ZBB-NEXT: min a0, a0, a1564; RV32ZBB-NEXT: ret565 %cmp = icmp slt i32 %a, %b566 %cond = select i1 %cmp, i32 %a, i32 %b567 ret i32 %cond568}569 570; As we are not matching directly i64 code patterns on RV32 some i64 patterns571; don't have yet any matching bit manipulation instructions on RV32.572; This test is presented here in case future expansions of the Bitmanip573; extensions introduce instructions suitable for this pattern.574 575define i64 @min_i64(i64 %a, i64 %b) nounwind {576; CHECK-LABEL: min_i64:577; CHECK: # %bb.0:578; CHECK-NEXT: beq a1, a3, .LBB15_2579; CHECK-NEXT: # %bb.1:580; CHECK-NEXT: slt a4, a1, a3581; CHECK-NEXT: beqz a4, .LBB15_3582; CHECK-NEXT: j .LBB15_4583; CHECK-NEXT: .LBB15_2:584; CHECK-NEXT: sltu a4, a0, a2585; CHECK-NEXT: bnez a4, .LBB15_4586; CHECK-NEXT: .LBB15_3:587; CHECK-NEXT: mv a0, a2588; CHECK-NEXT: mv a1, a3589; CHECK-NEXT: .LBB15_4:590; CHECK-NEXT: ret591 %cmp = icmp slt i64 %a, %b592 %cond = select i1 %cmp, i64 %a, i64 %b593 ret i64 %cond594}595 596define i32 @max_i32(i32 %a, i32 %b) nounwind {597; RV32I-LABEL: max_i32:598; RV32I: # %bb.0:599; RV32I-NEXT: blt a1, a0, .LBB16_2600; RV32I-NEXT: # %bb.1:601; RV32I-NEXT: mv a0, a1602; RV32I-NEXT: .LBB16_2:603; RV32I-NEXT: ret604;605; RV32ZBB-LABEL: max_i32:606; RV32ZBB: # %bb.0:607; RV32ZBB-NEXT: max a0, a0, a1608; RV32ZBB-NEXT: ret609 %cmp = icmp sgt i32 %a, %b610 %cond = select i1 %cmp, i32 %a, i32 %b611 ret i32 %cond612}613 614; As we are not matching directly i64 code patterns on RV32 some i64 patterns615; don't have yet any matching bit manipulation instructions on RV32.616; This test is presented here in case future expansions of the Bitmanip617; extensions introduce instructions suitable for this pattern.618 619define i64 @max_i64(i64 %a, i64 %b) nounwind {620; CHECK-LABEL: max_i64:621; CHECK: # %bb.0:622; CHECK-NEXT: beq a1, a3, .LBB17_2623; CHECK-NEXT: # %bb.1:624; CHECK-NEXT: slt a4, a3, a1625; CHECK-NEXT: beqz a4, .LBB17_3626; CHECK-NEXT: j .LBB17_4627; CHECK-NEXT: .LBB17_2:628; CHECK-NEXT: sltu a4, a2, a0629; CHECK-NEXT: bnez a4, .LBB17_4630; CHECK-NEXT: .LBB17_3:631; CHECK-NEXT: mv a0, a2632; CHECK-NEXT: mv a1, a3633; CHECK-NEXT: .LBB17_4:634; CHECK-NEXT: ret635 %cmp = icmp sgt i64 %a, %b636 %cond = select i1 %cmp, i64 %a, i64 %b637 ret i64 %cond638}639 640define i32 @minu_i32(i32 %a, i32 %b) nounwind {641; RV32I-LABEL: minu_i32:642; RV32I: # %bb.0:643; RV32I-NEXT: bltu a0, a1, .LBB18_2644; RV32I-NEXT: # %bb.1:645; RV32I-NEXT: mv a0, a1646; RV32I-NEXT: .LBB18_2:647; RV32I-NEXT: ret648;649; RV32ZBB-LABEL: minu_i32:650; RV32ZBB: # %bb.0:651; RV32ZBB-NEXT: minu a0, a0, a1652; RV32ZBB-NEXT: ret653 %cmp = icmp ult i32 %a, %b654 %cond = select i1 %cmp, i32 %a, i32 %b655 ret i32 %cond656}657 658; As we are not matching directly i64 code patterns on RV32 some i64 patterns659; don't have yet any matching bit manipulation instructions on RV32.660; This test is presented here in case future expansions of the Bitmanip661; extensions introduce instructions suitable for this pattern.662 663define i64 @minu_i64(i64 %a, i64 %b) nounwind {664; CHECK-LABEL: minu_i64:665; CHECK: # %bb.0:666; CHECK-NEXT: beq a1, a3, .LBB19_2667; CHECK-NEXT: # %bb.1:668; CHECK-NEXT: sltu a4, a1, a3669; CHECK-NEXT: beqz a4, .LBB19_3670; CHECK-NEXT: j .LBB19_4671; CHECK-NEXT: .LBB19_2:672; CHECK-NEXT: sltu a4, a0, a2673; CHECK-NEXT: bnez a4, .LBB19_4674; CHECK-NEXT: .LBB19_3:675; CHECK-NEXT: mv a0, a2676; CHECK-NEXT: mv a1, a3677; CHECK-NEXT: .LBB19_4:678; CHECK-NEXT: ret679 %cmp = icmp ult i64 %a, %b680 %cond = select i1 %cmp, i64 %a, i64 %b681 ret i64 %cond682}683 684define i32 @maxu_i32(i32 %a, i32 %b) nounwind {685; RV32I-LABEL: maxu_i32:686; RV32I: # %bb.0:687; RV32I-NEXT: bltu a1, a0, .LBB20_2688; RV32I-NEXT: # %bb.1:689; RV32I-NEXT: mv a0, a1690; RV32I-NEXT: .LBB20_2:691; RV32I-NEXT: ret692;693; RV32ZBB-LABEL: maxu_i32:694; RV32ZBB: # %bb.0:695; RV32ZBB-NEXT: maxu a0, a0, a1696; RV32ZBB-NEXT: ret697 %cmp = icmp ugt i32 %a, %b698 %cond = select i1 %cmp, i32 %a, i32 %b699 ret i32 %cond700}701 702; As we are not matching directly i64 code patterns on RV32 some i64 patterns703; don't have yet any matching bit manipulation instructions on RV32.704; This test is presented here in case future expansions of the Bitmanip705; extensions introduce instructions suitable for this pattern.706 707define i64 @maxu_i64(i64 %a, i64 %b) nounwind {708; CHECK-LABEL: maxu_i64:709; CHECK: # %bb.0:710; CHECK-NEXT: beq a1, a3, .LBB21_2711; CHECK-NEXT: # %bb.1:712; CHECK-NEXT: sltu a4, a3, a1713; CHECK-NEXT: beqz a4, .LBB21_3714; CHECK-NEXT: j .LBB21_4715; CHECK-NEXT: .LBB21_2:716; CHECK-NEXT: sltu a4, a2, a0717; CHECK-NEXT: bnez a4, .LBB21_4718; CHECK-NEXT: .LBB21_3:719; CHECK-NEXT: mv a0, a2720; CHECK-NEXT: mv a1, a3721; CHECK-NEXT: .LBB21_4:722; CHECK-NEXT: ret723 %cmp = icmp ugt i64 %a, %b724 %cond = select i1 %cmp, i64 %a, i64 %b725 ret i64 %cond726}727 728define i32 @abs_i32(i32 %x) {729; RV32I-LABEL: abs_i32:730; RV32I: # %bb.0:731; RV32I-NEXT: srai a1, a0, 31732; RV32I-NEXT: add a0, a0, a1733; RV32I-NEXT: xor a0, a0, a1734; RV32I-NEXT: ret735;736; RV32ZBB-LABEL: abs_i32:737; RV32ZBB: # %bb.0:738; RV32ZBB-NEXT: neg a1, a0739; RV32ZBB-NEXT: max a0, a0, a1740; RV32ZBB-NEXT: ret741 %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)742 ret i32 %abs743}744 745define i64 @abs_i64(i64 %x) {746; CHECK-LABEL: abs_i64:747; CHECK: # %bb.0:748; CHECK-NEXT: srai a2, a1, 31749; CHECK-NEXT: add a0, a0, a2750; CHECK-NEXT: add a1, a1, a2751; CHECK-NEXT: sltu a3, a0, a2752; CHECK-NEXT: add a1, a1, a3753; CHECK-NEXT: xor a0, a0, a2754; CHECK-NEXT: xor a1, a1, a2755; CHECK-NEXT: ret756 %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)757 ret i64 %abs758}759 760define i32 @zexth_i32(i32 %a) nounwind {761; RV32I-LABEL: zexth_i32:762; RV32I: # %bb.0:763; RV32I-NEXT: slli a0, a0, 16764; RV32I-NEXT: srli a0, a0, 16765; RV32I-NEXT: ret766;767; RV32ZBB-LABEL: zexth_i32:768; RV32ZBB: # %bb.0:769; RV32ZBB-NEXT: zext.h a0, a0770; RV32ZBB-NEXT: ret771 %and = and i32 %a, 65535772 ret i32 %and773}774 775define i64 @zexth_i64(i64 %a) nounwind {776; RV32I-LABEL: zexth_i64:777; RV32I: # %bb.0:778; RV32I-NEXT: slli a0, a0, 16779; RV32I-NEXT: srli a0, a0, 16780; RV32I-NEXT: li a1, 0781; RV32I-NEXT: ret782;783; RV32ZBB-LABEL: zexth_i64:784; RV32ZBB: # %bb.0:785; RV32ZBB-NEXT: zext.h a0, a0786; RV32ZBB-NEXT: li a1, 0787; RV32ZBB-NEXT: ret788 %and = and i64 %a, 65535789 ret i64 %and790}791 792define i32 @bswap_i32(i32 %a) nounwind {793; RV32I-LABEL: bswap_i32:794; RV32I: # %bb.0:795; RV32I-NEXT: slli a1, a0, 24796; RV32I-NEXT: srli a2, a0, 24797; RV32I-NEXT: lui a3, 16798; RV32I-NEXT: or a1, a2, a1799; RV32I-NEXT: srli a2, a0, 8800; RV32I-NEXT: addi a3, a3, -256801; RV32I-NEXT: and a0, a0, a3802; RV32I-NEXT: and a2, a2, a3803; RV32I-NEXT: slli a0, a0, 8804; RV32I-NEXT: or a1, a1, a2805; RV32I-NEXT: or a0, a1, a0806; RV32I-NEXT: ret807;808; RV32ZBB-LABEL: bswap_i32:809; RV32ZBB: # %bb.0:810; RV32ZBB-NEXT: rev8 a0, a0811; RV32ZBB-NEXT: ret812 %1 = tail call i32 @llvm.bswap.i32(i32 %a)813 ret i32 %1814}815 816define i64 @bswap_i64(i64 %a) {817; RV32I-LABEL: bswap_i64:818; RV32I: # %bb.0:819; RV32I-NEXT: slli a2, a1, 24820; RV32I-NEXT: srli a3, a1, 24821; RV32I-NEXT: lui a4, 16822; RV32I-NEXT: srli a5, a1, 8823; RV32I-NEXT: slli a6, a0, 24824; RV32I-NEXT: or a2, a3, a2825; RV32I-NEXT: srli a3, a0, 24826; RV32I-NEXT: or a3, a3, a6827; RV32I-NEXT: srli a6, a0, 8828; RV32I-NEXT: addi a4, a4, -256829; RV32I-NEXT: and a1, a1, a4830; RV32I-NEXT: and a5, a5, a4831; RV32I-NEXT: and a0, a0, a4832; RV32I-NEXT: and a4, a6, a4833; RV32I-NEXT: or a2, a2, a5834; RV32I-NEXT: slli a1, a1, 8835; RV32I-NEXT: slli a5, a0, 8836; RV32I-NEXT: or a3, a3, a4837; RV32I-NEXT: or a0, a2, a1838; RV32I-NEXT: or a1, a3, a5839; RV32I-NEXT: ret840;841; RV32ZBB-LABEL: bswap_i64:842; RV32ZBB: # %bb.0:843; RV32ZBB-NEXT: rev8 a2, a1844; RV32ZBB-NEXT: rev8 a1, a0845; RV32ZBB-NEXT: mv a0, a2846; RV32ZBB-NEXT: ret847 %1 = call i64 @llvm.bswap.i64(i64 %a)848 ret i64 %1849}850