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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -global-isel -mattr=+m -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I4; RUN: llc -mtriple=riscv64 -global-isel -mattr=+m,+zba -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBA,RV64ZBANOZBB6; RUN: llc -mtriple=riscv64 -global-isel -mattr=+m,+zba,+zbb -verify-machineinstrs < %s \7; RUN: | FileCheck %s -check-prefixes=CHECK,RV64ZBA,RV64ZBAZBB8 9define i64 @slliuw(i64 %a) nounwind {10; RV64I-LABEL: slliuw:11; RV64I: # %bb.0:12; RV64I-NEXT: li a1, 113; RV64I-NEXT: slli a1, a1, 3314; RV64I-NEXT: addi a1, a1, -215; RV64I-NEXT: slli a0, a0, 116; RV64I-NEXT: and a0, a0, a117; RV64I-NEXT: ret18;19; RV64ZBA-LABEL: slliuw:20; RV64ZBA: # %bb.0:21; RV64ZBA-NEXT: slli a0, a0, 122; RV64ZBA-NEXT: srli a0, a0, 123; RV64ZBA-NEXT: slli.uw a0, a0, 124; RV64ZBA-NEXT: ret25 %conv1 = shl i64 %a, 126 %shl = and i64 %conv1, 858993459027 ret i64 %shl28}29 30define i128 @slliuw_2(i32 signext %0, ptr %1) {31; RV64I-LABEL: slliuw_2:32; RV64I: # %bb.0:33; RV64I-NEXT: slli a0, a0, 3234; RV64I-NEXT: srli a0, a0, 2835; RV64I-NEXT: add a1, a1, a036; RV64I-NEXT: ld a0, 0(a1)37; RV64I-NEXT: ld a1, 8(a1)38; RV64I-NEXT: ret39;40; RV64ZBA-LABEL: slliuw_2:41; RV64ZBA: # %bb.0:42; RV64ZBA-NEXT: slli.uw a0, a0, 443; RV64ZBA-NEXT: add a1, a1, a044; RV64ZBA-NEXT: ld a0, 0(a1)45; RV64ZBA-NEXT: ld a1, 8(a1)46; RV64ZBA-NEXT: ret47 %3 = zext i32 %0 to i6448 %4 = getelementptr inbounds i128, ptr %1, i64 %349 %5 = load i128, ptr %450 ret i128 %551}52 53define i64 @adduw(i64 %a, i64 %b) nounwind {54; RV64I-LABEL: adduw:55; RV64I: # %bb.0:56; RV64I-NEXT: slli a1, a1, 3257; RV64I-NEXT: srli a1, a1, 3258; RV64I-NEXT: add a0, a1, a059; RV64I-NEXT: ret60;61; RV64ZBA-LABEL: adduw:62; RV64ZBA: # %bb.0:63; RV64ZBA-NEXT: add.uw a0, a1, a064; RV64ZBA-NEXT: ret65 %and = and i64 %b, 429496729566 %add = add i64 %and, %a67 ret i64 %add68}69 70define signext i8 @adduw_2(i32 signext %0, ptr %1) {71; RV64I-LABEL: adduw_2:72; RV64I: # %bb.0:73; RV64I-NEXT: slli a0, a0, 3274; RV64I-NEXT: srli a0, a0, 3275; RV64I-NEXT: add a0, a1, a076; RV64I-NEXT: lb a0, 0(a0)77; RV64I-NEXT: ret78;79; RV64ZBA-LABEL: adduw_2:80; RV64ZBA: # %bb.0:81; RV64ZBA-NEXT: add.uw a0, a0, a182; RV64ZBA-NEXT: lb a0, 0(a0)83; RV64ZBA-NEXT: ret84 %3 = zext i32 %0 to i6485 %4 = getelementptr inbounds i8, ptr %1, i64 %386 %5 = load i8, ptr %487 ret i8 %588}89 90define i64 @zextw_i64(i64 %a) nounwind {91; RV64I-LABEL: zextw_i64:92; RV64I: # %bb.0:93; RV64I-NEXT: slli a0, a0, 3294; RV64I-NEXT: srli a0, a0, 3295; RV64I-NEXT: ret96;97; RV64ZBA-LABEL: zextw_i64:98; RV64ZBA: # %bb.0:99; RV64ZBA-NEXT: zext.w a0, a0100; RV64ZBA-NEXT: ret101 %and = and i64 %a, 4294967295102 ret i64 %and103}104 105; This makes sure targetShrinkDemandedConstant changes the and immmediate to106; allow zext.w or slli+srli.107define i64 @zextw_demandedbits_i64(i64 %0) {108; CHECK-LABEL: zextw_demandedbits_i64:109; CHECK: # %bb.0:110; CHECK-NEXT: srliw a0, a0, 1111; CHECK-NEXT: slli a0, a0, 1112; CHECK-NEXT: ori a0, a0, 1113; CHECK-NEXT: ret114 %2 = and i64 %0, 4294967294115 %3 = or i64 %2, 1116 ret i64 %3117}118 119define signext i16 @sh1add(i64 %0, ptr %1) {120; RV64I-LABEL: sh1add:121; RV64I: # %bb.0:122; RV64I-NEXT: slli a0, a0, 1123; RV64I-NEXT: add a0, a1, a0124; RV64I-NEXT: lh a0, 0(a0)125; RV64I-NEXT: ret126;127; RV64ZBA-LABEL: sh1add:128; RV64ZBA: # %bb.0:129; RV64ZBA-NEXT: sh1add a0, a0, a1130; RV64ZBA-NEXT: lh a0, 0(a0)131; RV64ZBA-NEXT: ret132 %3 = getelementptr inbounds i16, ptr %1, i64 %0133 %4 = load i16, ptr %3134 ret i16 %4135}136 137define signext i32 @sh2add(i64 %0, ptr %1) {138; RV64I-LABEL: sh2add:139; RV64I: # %bb.0:140; RV64I-NEXT: slli a0, a0, 2141; RV64I-NEXT: add a0, a1, a0142; RV64I-NEXT: lw a0, 0(a0)143; RV64I-NEXT: ret144;145; RV64ZBA-LABEL: sh2add:146; RV64ZBA: # %bb.0:147; RV64ZBA-NEXT: sh2add a0, a0, a1148; RV64ZBA-NEXT: lw a0, 0(a0)149; RV64ZBA-NEXT: ret150 %3 = getelementptr inbounds i32, ptr %1, i64 %0151 %4 = load i32, ptr %3152 ret i32 %4153}154 155define i64 @sh3add(i64 %0, ptr %1) {156; RV64I-LABEL: sh3add:157; RV64I: # %bb.0:158; RV64I-NEXT: slli a0, a0, 3159; RV64I-NEXT: add a0, a1, a0160; RV64I-NEXT: ld a0, 0(a0)161; RV64I-NEXT: ret162;163; RV64ZBA-LABEL: sh3add:164; RV64ZBA: # %bb.0:165; RV64ZBA-NEXT: sh3add a0, a0, a1166; RV64ZBA-NEXT: ld a0, 0(a0)167; RV64ZBA-NEXT: ret168 %3 = getelementptr inbounds i64, ptr %1, i64 %0169 %4 = load i64, ptr %3170 ret i64 %4171}172 173define signext i16 @sh1adduw(i32 signext %0, ptr %1) {174; RV64I-LABEL: sh1adduw:175; RV64I: # %bb.0:176; RV64I-NEXT: slli a0, a0, 32177; RV64I-NEXT: srli a0, a0, 31178; RV64I-NEXT: add a0, a1, a0179; RV64I-NEXT: lh a0, 0(a0)180; RV64I-NEXT: ret181;182; RV64ZBA-LABEL: sh1adduw:183; RV64ZBA: # %bb.0:184; RV64ZBA-NEXT: sh1add.uw a0, a0, a1185; RV64ZBA-NEXT: lh a0, 0(a0)186; RV64ZBA-NEXT: ret187 %3 = zext i32 %0 to i64188 %4 = getelementptr inbounds i16, ptr %1, i64 %3189 %5 = load i16, ptr %4190 ret i16 %5191}192 193define i64 @sh1adduw_2(i64 %0, i64 %1) {194; RV64I-LABEL: sh1adduw_2:195; RV64I: # %bb.0:196; RV64I-NEXT: li a2, 1197; RV64I-NEXT: slli a2, a2, 33198; RV64I-NEXT: addi a2, a2, -2199; RV64I-NEXT: slli a0, a0, 1200; RV64I-NEXT: and a0, a0, a2201; RV64I-NEXT: add a0, a0, a1202; RV64I-NEXT: ret203;204; RV64ZBA-LABEL: sh1adduw_2:205; RV64ZBA: # %bb.0:206; RV64ZBA-NEXT: slli a0, a0, 1207; RV64ZBA-NEXT: srli a0, a0, 1208; RV64ZBA-NEXT: sh1add.uw a0, a0, a1209; RV64ZBA-NEXT: ret210 %3 = shl i64 %0, 1211 %4 = and i64 %3, 8589934590212 %5 = add i64 %4, %1213 ret i64 %5214}215 216define i64 @sh1adduw_3(i64 %0, i64 %1) {217; RV64I-LABEL: sh1adduw_3:218; RV64I: # %bb.0:219; RV64I-NEXT: li a2, 1220; RV64I-NEXT: slli a2, a2, 33221; RV64I-NEXT: addi a2, a2, -2222; RV64I-NEXT: slli a0, a0, 1223; RV64I-NEXT: and a0, a0, a2224; RV64I-NEXT: or a0, a0, a1225; RV64I-NEXT: ret226;227; RV64ZBA-LABEL: sh1adduw_3:228; RV64ZBA: # %bb.0:229; RV64ZBA-NEXT: slli a0, a0, 1230; RV64ZBA-NEXT: srli a0, a0, 1231; RV64ZBA-NEXT: slli.uw a0, a0, 1232; RV64ZBA-NEXT: or a0, a0, a1233; RV64ZBA-NEXT: ret234 %3 = shl i64 %0, 1235 %4 = and i64 %3, 8589934590236 %5 = or disjoint i64 %4, %1237 ret i64 %5238}239 240define signext i32 @sh2adduw(i32 signext %0, ptr %1) {241; RV64I-LABEL: sh2adduw:242; RV64I: # %bb.0:243; RV64I-NEXT: slli a0, a0, 32244; RV64I-NEXT: srli a0, a0, 30245; RV64I-NEXT: add a0, a1, a0246; RV64I-NEXT: lw a0, 0(a0)247; RV64I-NEXT: ret248;249; RV64ZBA-LABEL: sh2adduw:250; RV64ZBA: # %bb.0:251; RV64ZBA-NEXT: sh2add.uw a0, a0, a1252; RV64ZBA-NEXT: lw a0, 0(a0)253; RV64ZBA-NEXT: ret254 %3 = zext i32 %0 to i64255 %4 = getelementptr inbounds i32, ptr %1, i64 %3256 %5 = load i32, ptr %4257 ret i32 %5258}259 260define i64 @sh2adduw_2(i64 %0, i64 %1) {261; RV64I-LABEL: sh2adduw_2:262; RV64I: # %bb.0:263; RV64I-NEXT: li a2, 1264; RV64I-NEXT: slli a2, a2, 34265; RV64I-NEXT: addi a2, a2, -4266; RV64I-NEXT: slli a0, a0, 2267; RV64I-NEXT: and a0, a0, a2268; RV64I-NEXT: add a0, a0, a1269; RV64I-NEXT: ret270;271; RV64ZBA-LABEL: sh2adduw_2:272; RV64ZBA: # %bb.0:273; RV64ZBA-NEXT: slli a0, a0, 2274; RV64ZBA-NEXT: srli a0, a0, 2275; RV64ZBA-NEXT: sh2add.uw a0, a0, a1276; RV64ZBA-NEXT: ret277 %3 = shl i64 %0, 2278 %4 = and i64 %3, 17179869180279 %5 = add i64 %4, %1280 ret i64 %5281}282 283define i64 @sh2adduw_3(i64 %0, i64 %1) {284; RV64I-LABEL: sh2adduw_3:285; RV64I: # %bb.0:286; RV64I-NEXT: li a2, 1287; RV64I-NEXT: slli a2, a2, 34288; RV64I-NEXT: addi a2, a2, -4289; RV64I-NEXT: slli a0, a0, 2290; RV64I-NEXT: and a0, a0, a2291; RV64I-NEXT: or a0, a0, a1292; RV64I-NEXT: ret293;294; RV64ZBA-LABEL: sh2adduw_3:295; RV64ZBA: # %bb.0:296; RV64ZBA-NEXT: slli a0, a0, 2297; RV64ZBA-NEXT: srli a0, a0, 2298; RV64ZBA-NEXT: slli.uw a0, a0, 2299; RV64ZBA-NEXT: or a0, a0, a1300; RV64ZBA-NEXT: ret301 %3 = shl i64 %0, 2302 %4 = and i64 %3, 17179869180303 %5 = or disjoint i64 %4, %1304 ret i64 %5305}306 307define i64 @sh3adduw(i32 signext %0, ptr %1) {308; RV64I-LABEL: sh3adduw:309; RV64I: # %bb.0:310; RV64I-NEXT: slli a0, a0, 32311; RV64I-NEXT: srli a0, a0, 29312; RV64I-NEXT: add a0, a1, a0313; RV64I-NEXT: ld a0, 0(a0)314; RV64I-NEXT: ret315;316; RV64ZBA-LABEL: sh3adduw:317; RV64ZBA: # %bb.0:318; RV64ZBA-NEXT: sh3add.uw a0, a0, a1319; RV64ZBA-NEXT: ld a0, 0(a0)320; RV64ZBA-NEXT: ret321 %3 = zext i32 %0 to i64322 %4 = getelementptr inbounds i64, ptr %1, i64 %3323 %5 = load i64, ptr %4324 ret i64 %5325}326 327define i64 @sh3adduw_2(i64 %0, i64 %1) {328; RV64I-LABEL: sh3adduw_2:329; RV64I: # %bb.0:330; RV64I-NEXT: li a2, 1331; RV64I-NEXT: slli a2, a2, 35332; RV64I-NEXT: addi a2, a2, -8333; RV64I-NEXT: slli a0, a0, 3334; RV64I-NEXT: and a0, a0, a2335; RV64I-NEXT: add a0, a0, a1336; RV64I-NEXT: ret337;338; RV64ZBA-LABEL: sh3adduw_2:339; RV64ZBA: # %bb.0:340; RV64ZBA-NEXT: slli a0, a0, 3341; RV64ZBA-NEXT: srli a0, a0, 3342; RV64ZBA-NEXT: sh3add.uw a0, a0, a1343; RV64ZBA-NEXT: ret344 %3 = shl i64 %0, 3345 %4 = and i64 %3, 34359738360346 %5 = add i64 %4, %1347 ret i64 %5348}349 350define i64 @sh3adduw_3(i64 %0, i64 %1) {351; RV64I-LABEL: sh3adduw_3:352; RV64I: # %bb.0:353; RV64I-NEXT: li a2, 1354; RV64I-NEXT: slli a2, a2, 35355; RV64I-NEXT: addi a2, a2, -8356; RV64I-NEXT: slli a0, a0, 3357; RV64I-NEXT: and a0, a0, a2358; RV64I-NEXT: or a0, a0, a1359; RV64I-NEXT: ret360;361; RV64ZBA-LABEL: sh3adduw_3:362; RV64ZBA: # %bb.0:363; RV64ZBA-NEXT: slli a0, a0, 3364; RV64ZBA-NEXT: srli a0, a0, 3365; RV64ZBA-NEXT: slli.uw a0, a0, 3366; RV64ZBA-NEXT: or a0, a0, a1367; RV64ZBA-NEXT: ret368 %3 = shl i64 %0, 3369 %4 = and i64 %3, 34359738360370 %5 = or disjoint i64 %4, %1371 ret i64 %5372}373 374; Make sure we use sext.b+slli+srli for Zba+Zbb.375; FIXME: The RV64I and Zba only cases can be done with only 3 shifts.376define zeroext i32 @sext_ashr_zext_i8(i8 %a) nounwind {377; RV64I-LABEL: sext_ashr_zext_i8:378; RV64I: # %bb.0:379; RV64I-NEXT: slli a0, a0, 56380; RV64I-NEXT: srai a0, a0, 63381; RV64I-NEXT: slli a0, a0, 32382; RV64I-NEXT: srli a0, a0, 32383; RV64I-NEXT: ret384;385; RV64ZBANOZBB-LABEL: sext_ashr_zext_i8:386; RV64ZBANOZBB: # %bb.0:387; RV64ZBANOZBB-NEXT: slli a0, a0, 56388; RV64ZBANOZBB-NEXT: srai a0, a0, 63389; RV64ZBANOZBB-NEXT: zext.w a0, a0390; RV64ZBANOZBB-NEXT: ret391;392; RV64ZBAZBB-LABEL: sext_ashr_zext_i8:393; RV64ZBAZBB: # %bb.0:394; RV64ZBAZBB-NEXT: sext.b a0, a0395; RV64ZBAZBB-NEXT: srai a0, a0, 9396; RV64ZBAZBB-NEXT: zext.w a0, a0397; RV64ZBAZBB-NEXT: ret398 %ext = sext i8 %a to i32399 %1 = ashr i32 %ext, 9400 ret i32 %1401}402 403define i64 @sh6_sh3_add1(i64 noundef %x, i64 noundef %y, i64 noundef %z) {404; RV64I-LABEL: sh6_sh3_add1:405; RV64I: # %bb.0: # %entry406; RV64I-NEXT: slli a2, a2, 3407; RV64I-NEXT: slli a1, a1, 6408; RV64I-NEXT: add a1, a1, a2409; RV64I-NEXT: add a0, a1, a0410; RV64I-NEXT: ret411;412; RV64ZBA-LABEL: sh6_sh3_add1:413; RV64ZBA: # %bb.0: # %entry414; RV64ZBA-NEXT: slli a1, a1, 6415; RV64ZBA-NEXT: sh3add a1, a2, a1416; RV64ZBA-NEXT: add a0, a1, a0417; RV64ZBA-NEXT: ret418entry:419 %shl = shl i64 %z, 3420 %shl1 = shl i64 %y, 6421 %add = add nsw i64 %shl1, %shl422 %add2 = add nsw i64 %add, %x423 ret i64 %add2424}425 426define i64 @sh6_sh3_add2(i64 noundef %x, i64 noundef %y, i64 noundef %z) {427; RV64I-LABEL: sh6_sh3_add2:428; RV64I: # %bb.0: # %entry429; RV64I-NEXT: slli a2, a2, 3430; RV64I-NEXT: slli a1, a1, 6431; RV64I-NEXT: add a0, a1, a0432; RV64I-NEXT: add a0, a0, a2433; RV64I-NEXT: ret434;435; RV64ZBA-LABEL: sh6_sh3_add2:436; RV64ZBA: # %bb.0: # %entry437; RV64ZBA-NEXT: sh3add a1, a1, a2438; RV64ZBA-NEXT: sh3add a0, a1, a0439; RV64ZBA-NEXT: ret440entry:441 %shl = shl i64 %z, 3442 %shl1 = shl i64 %y, 6443 %add = add nsw i64 %shl1, %x444 %add2 = add nsw i64 %add, %shl445 ret i64 %add2446}447 448define i64 @sh6_sh3_add3(i64 noundef %x, i64 noundef %y, i64 noundef %z) {449; RV64I-LABEL: sh6_sh3_add3:450; RV64I: # %bb.0: # %entry451; RV64I-NEXT: slli a2, a2, 3452; RV64I-NEXT: slli a1, a1, 6453; RV64I-NEXT: add a1, a1, a2454; RV64I-NEXT: add a0, a0, a1455; RV64I-NEXT: ret456;457; RV64ZBA-LABEL: sh6_sh3_add3:458; RV64ZBA: # %bb.0: # %entry459; RV64ZBA-NEXT: slli a1, a1, 6460; RV64ZBA-NEXT: sh3add a1, a2, a1461; RV64ZBA-NEXT: add a0, a0, a1462; RV64ZBA-NEXT: ret463entry:464 %shl = shl i64 %z, 3465 %shl1 = shl i64 %y, 6466 %add = add nsw i64 %shl1, %shl467 %add2 = add nsw i64 %x, %add468 ret i64 %add2469}470 471define i64 @sh6_sh3_add4(i64 noundef %x, i64 noundef %y, i64 noundef %z) {472; RV64I-LABEL: sh6_sh3_add4:473; RV64I: # %bb.0: # %entry474; RV64I-NEXT: slli a2, a2, 3475; RV64I-NEXT: slli a1, a1, 6476; RV64I-NEXT: add a0, a0, a2477; RV64I-NEXT: add a0, a0, a1478; RV64I-NEXT: ret479;480; RV64ZBA-LABEL: sh6_sh3_add4:481; RV64ZBA: # %bb.0: # %entry482; RV64ZBA-NEXT: slli a1, a1, 6483; RV64ZBA-NEXT: sh3add a0, a2, a0484; RV64ZBA-NEXT: add a0, a0, a1485; RV64ZBA-NEXT: ret486entry:487 %shl = shl i64 %z, 3488 %shl1 = shl i64 %y, 6489 %add = add nsw i64 %x, %shl490 %add2 = add nsw i64 %add, %shl1491 ret i64 %add2492}493 494; Make sure we use sext.h+slli+srli for Zba+Zbb.495; FIXME: The RV64I and Zba only cases can be done with only 3 shifts.496define zeroext i32 @sext_ashr_zext_i16(i16 %a) nounwind {497; RV64I-LABEL: sext_ashr_zext_i16:498; RV64I: # %bb.0:499; RV64I-NEXT: slli a0, a0, 48500; RV64I-NEXT: srai a0, a0, 57501; RV64I-NEXT: slli a0, a0, 32502; RV64I-NEXT: srli a0, a0, 32503; RV64I-NEXT: ret504;505; RV64ZBANOZBB-LABEL: sext_ashr_zext_i16:506; RV64ZBANOZBB: # %bb.0:507; RV64ZBANOZBB-NEXT: slli a0, a0, 48508; RV64ZBANOZBB-NEXT: srai a0, a0, 57509; RV64ZBANOZBB-NEXT: zext.w a0, a0510; RV64ZBANOZBB-NEXT: ret511;512; RV64ZBAZBB-LABEL: sext_ashr_zext_i16:513; RV64ZBAZBB: # %bb.0:514; RV64ZBAZBB-NEXT: sext.h a0, a0515; RV64ZBAZBB-NEXT: srai a0, a0, 9516; RV64ZBAZBB-NEXT: zext.w a0, a0517; RV64ZBAZBB-NEXT: ret518 %ext = sext i16 %a to i32519 %1 = ashr i32 %ext, 9520 ret i32 %1521}522 523; This the IR you get from InstCombine if take the difference of 2 pointers and524; cast is to unsigned before using as an index.525define signext i16 @sh1adduw_ptrdiff(i64 %diff, ptr %baseptr) {526; RV64I-LABEL: sh1adduw_ptrdiff:527; RV64I: # %bb.0:528; RV64I-NEXT: srli a0, a0, 1529; RV64I-NEXT: slli a0, a0, 32530; RV64I-NEXT: srli a0, a0, 31531; RV64I-NEXT: add a0, a1, a0532; RV64I-NEXT: lh a0, 0(a0)533; RV64I-NEXT: ret534;535; RV64ZBA-LABEL: sh1adduw_ptrdiff:536; RV64ZBA: # %bb.0:537; RV64ZBA-NEXT: srli a0, a0, 1538; RV64ZBA-NEXT: sh1add.uw a0, a0, a1539; RV64ZBA-NEXT: lh a0, 0(a0)540; RV64ZBA-NEXT: ret541 %ptrdiff = lshr exact i64 %diff, 1542 %cast = and i64 %ptrdiff, 4294967295543 %ptr = getelementptr inbounds i16, ptr %baseptr, i64 %cast544 %res = load i16, ptr %ptr545 ret i16 %res546}547 548define signext i32 @sh2adduw_ptrdiff(i64 %diff, ptr %baseptr) {549; RV64I-LABEL: sh2adduw_ptrdiff:550; RV64I: # %bb.0:551; RV64I-NEXT: srli a0, a0, 2552; RV64I-NEXT: slli a0, a0, 32553; RV64I-NEXT: srli a0, a0, 30554; RV64I-NEXT: add a0, a1, a0555; RV64I-NEXT: lw a0, 0(a0)556; RV64I-NEXT: ret557;558; RV64ZBA-LABEL: sh2adduw_ptrdiff:559; RV64ZBA: # %bb.0:560; RV64ZBA-NEXT: srli a0, a0, 2561; RV64ZBA-NEXT: sh2add.uw a0, a0, a1562; RV64ZBA-NEXT: lw a0, 0(a0)563; RV64ZBA-NEXT: ret564 %ptrdiff = lshr exact i64 %diff, 2565 %cast = and i64 %ptrdiff, 4294967295566 %ptr = getelementptr inbounds i32, ptr %baseptr, i64 %cast567 %res = load i32, ptr %ptr568 ret i32 %res569}570 571define i64 @sh3adduw_ptrdiff(i64 %diff, ptr %baseptr) {572; RV64I-LABEL: sh3adduw_ptrdiff:573; RV64I: # %bb.0:574; RV64I-NEXT: srli a0, a0, 3575; RV64I-NEXT: slli a0, a0, 32576; RV64I-NEXT: srli a0, a0, 29577; RV64I-NEXT: add a0, a1, a0578; RV64I-NEXT: ld a0, 0(a0)579; RV64I-NEXT: ret580;581; RV64ZBA-LABEL: sh3adduw_ptrdiff:582; RV64ZBA: # %bb.0:583; RV64ZBA-NEXT: srli a0, a0, 3584; RV64ZBA-NEXT: sh3add.uw a0, a0, a1585; RV64ZBA-NEXT: ld a0, 0(a0)586; RV64ZBA-NEXT: ret587 %ptrdiff = lshr exact i64 %diff, 3588 %cast = and i64 %ptrdiff, 4294967295589 %ptr = getelementptr inbounds i64, ptr %baseptr, i64 %cast590 %res = load i64, ptr %ptr591 ret i64 %res592}593 594define signext i16 @srliw_1_sh1add(ptr %0, i32 signext %1) {595; RV64I-LABEL: srliw_1_sh1add:596; RV64I: # %bb.0:597; RV64I-NEXT: srliw a1, a1, 1598; RV64I-NEXT: slli a1, a1, 1599; RV64I-NEXT: add a0, a0, a1600; RV64I-NEXT: lh a0, 0(a0)601; RV64I-NEXT: ret602;603; RV64ZBA-LABEL: srliw_1_sh1add:604; RV64ZBA: # %bb.0:605; RV64ZBA-NEXT: srliw a1, a1, 1606; RV64ZBA-NEXT: sh1add a0, a1, a0607; RV64ZBA-NEXT: lh a0, 0(a0)608; RV64ZBA-NEXT: ret609 %3 = lshr i32 %1, 1610 %4 = zext i32 %3 to i64611 %5 = getelementptr inbounds i16, ptr %0, i64 %4612 %6 = load i16, ptr %5, align 2613 ret i16 %6614}615 616define i128 @slliuw_ptrdiff(i64 %diff, ptr %baseptr) {617; RV64I-LABEL: slliuw_ptrdiff:618; RV64I: # %bb.0:619; RV64I-NEXT: srli a0, a0, 4620; RV64I-NEXT: slli a0, a0, 32621; RV64I-NEXT: srli a0, a0, 28622; RV64I-NEXT: add a1, a1, a0623; RV64I-NEXT: ld a0, 0(a1)624; RV64I-NEXT: ld a1, 8(a1)625; RV64I-NEXT: ret626;627; RV64ZBA-LABEL: slliuw_ptrdiff:628; RV64ZBA: # %bb.0:629; RV64ZBA-NEXT: srli a0, a0, 4630; RV64ZBA-NEXT: slli.uw a0, a0, 4631; RV64ZBA-NEXT: add a1, a1, a0632; RV64ZBA-NEXT: ld a0, 0(a1)633; RV64ZBA-NEXT: ld a1, 8(a1)634; RV64ZBA-NEXT: ret635 %ptrdiff = lshr exact i64 %diff, 4636 %cast = and i64 %ptrdiff, 4294967295637 %ptr = getelementptr inbounds i128, ptr %baseptr, i64 %cast638 %res = load i128, ptr %ptr639 ret i128 %res640}641 642define signext i32 @srliw_2_sh2add(ptr %0, i32 signext %1) {643; RV64I-LABEL: srliw_2_sh2add:644; RV64I: # %bb.0:645; RV64I-NEXT: srliw a1, a1, 2646; RV64I-NEXT: slli a1, a1, 2647; RV64I-NEXT: add a0, a0, a1648; RV64I-NEXT: lw a0, 0(a0)649; RV64I-NEXT: ret650;651; RV64ZBA-LABEL: srliw_2_sh2add:652; RV64ZBA: # %bb.0:653; RV64ZBA-NEXT: srliw a1, a1, 2654; RV64ZBA-NEXT: sh2add a0, a1, a0655; RV64ZBA-NEXT: lw a0, 0(a0)656; RV64ZBA-NEXT: ret657 %3 = lshr i32 %1, 2658 %4 = zext i32 %3 to i64659 %5 = getelementptr inbounds i32, ptr %0, i64 %4660 %6 = load i32, ptr %5, align 4661 ret i32 %6662}663 664define i64 @srliw_3_sh3add(ptr %0, i32 signext %1) {665; RV64I-LABEL: srliw_3_sh3add:666; RV64I: # %bb.0:667; RV64I-NEXT: srliw a1, a1, 3668; RV64I-NEXT: slli a1, a1, 3669; RV64I-NEXT: add a0, a0, a1670; RV64I-NEXT: ld a0, 0(a0)671; RV64I-NEXT: ret672;673; RV64ZBA-LABEL: srliw_3_sh3add:674; RV64ZBA: # %bb.0:675; RV64ZBA-NEXT: srliw a1, a1, 3676; RV64ZBA-NEXT: sh3add a0, a1, a0677; RV64ZBA-NEXT: ld a0, 0(a0)678; RV64ZBA-NEXT: ret679 %3 = lshr i32 %1, 3680 %4 = zext i32 %3 to i64681 %5 = getelementptr inbounds i64, ptr %0, i64 %4682 %6 = load i64, ptr %5, align 8683 ret i64 %6684}685 686define signext i32 @srliw_1_sh2add(ptr %0, i32 signext %1) {687; RV64I-LABEL: srliw_1_sh2add:688; RV64I: # %bb.0:689; RV64I-NEXT: srliw a1, a1, 1690; RV64I-NEXT: slli a1, a1, 2691; RV64I-NEXT: add a0, a0, a1692; RV64I-NEXT: lw a0, 0(a0)693; RV64I-NEXT: ret694;695; RV64ZBA-LABEL: srliw_1_sh2add:696; RV64ZBA: # %bb.0:697; RV64ZBA-NEXT: srliw a1, a1, 1698; RV64ZBA-NEXT: sh2add a0, a1, a0699; RV64ZBA-NEXT: lw a0, 0(a0)700; RV64ZBA-NEXT: ret701 %3 = lshr i32 %1, 1702 %4 = zext i32 %3 to i64703 %5 = getelementptr inbounds i32, ptr %0, i64 %4704 %6 = load i32, ptr %5, align 4705 ret i32 %6706}707 708define i64 @srliw_1_sh3add(ptr %0, i32 signext %1) {709; RV64I-LABEL: srliw_1_sh3add:710; RV64I: # %bb.0:711; RV64I-NEXT: srliw a1, a1, 1712; RV64I-NEXT: slli a1, a1, 3713; RV64I-NEXT: add a0, a0, a1714; RV64I-NEXT: ld a0, 0(a0)715; RV64I-NEXT: ret716;717; RV64ZBA-LABEL: srliw_1_sh3add:718; RV64ZBA: # %bb.0:719; RV64ZBA-NEXT: srliw a1, a1, 1720; RV64ZBA-NEXT: sh3add a0, a1, a0721; RV64ZBA-NEXT: ld a0, 0(a0)722; RV64ZBA-NEXT: ret723 %3 = lshr i32 %1, 1724 %4 = zext i32 %3 to i64725 %5 = getelementptr inbounds i64, ptr %0, i64 %4726 %6 = load i64, ptr %5, align 8727 ret i64 %6728}729 730define i64 @srliw_2_sh3add(ptr %0, i32 signext %1) {731; RV64I-LABEL: srliw_2_sh3add:732; RV64I: # %bb.0:733; RV64I-NEXT: srliw a1, a1, 2734; RV64I-NEXT: slli a1, a1, 3735; RV64I-NEXT: add a0, a0, a1736; RV64I-NEXT: ld a0, 0(a0)737; RV64I-NEXT: ret738;739; RV64ZBA-LABEL: srliw_2_sh3add:740; RV64ZBA: # %bb.0:741; RV64ZBA-NEXT: srliw a1, a1, 2742; RV64ZBA-NEXT: sh3add a0, a1, a0743; RV64ZBA-NEXT: ld a0, 0(a0)744; RV64ZBA-NEXT: ret745 %3 = lshr i32 %1, 2746 %4 = zext i32 %3 to i64747 %5 = getelementptr inbounds i64, ptr %0, i64 %4748 %6 = load i64, ptr %5, align 8749 ret i64 %6750}751 752define signext i16 @srliw_2_sh1add(ptr %0, i32 signext %1) {753; RV64I-LABEL: srliw_2_sh1add:754; RV64I: # %bb.0:755; RV64I-NEXT: srliw a1, a1, 2756; RV64I-NEXT: slli a1, a1, 1757; RV64I-NEXT: add a0, a0, a1758; RV64I-NEXT: lh a0, 0(a0)759; RV64I-NEXT: ret760;761; RV64ZBA-LABEL: srliw_2_sh1add:762; RV64ZBA: # %bb.0:763; RV64ZBA-NEXT: srliw a1, a1, 2764; RV64ZBA-NEXT: sh1add a0, a1, a0765; RV64ZBA-NEXT: lh a0, 0(a0)766; RV64ZBA-NEXT: ret767 %3 = lshr i32 %1, 2768 %4 = zext i32 %3 to i64769 %5 = getelementptr inbounds i16, ptr %0, i64 %4770 %6 = load i16, ptr %5, align 2771 ret i16 %6772}773 774 775define signext i32 @srliw_3_sh2add(ptr %0, i32 signext %1) {776; RV64I-LABEL: srliw_3_sh2add:777; RV64I: # %bb.0:778; RV64I-NEXT: srliw a1, a1, 3779; RV64I-NEXT: slli a1, a1, 2780; RV64I-NEXT: add a0, a0, a1781; RV64I-NEXT: lw a0, 0(a0)782; RV64I-NEXT: ret783;784; RV64ZBA-LABEL: srliw_3_sh2add:785; RV64ZBA: # %bb.0:786; RV64ZBA-NEXT: srliw a1, a1, 3787; RV64ZBA-NEXT: sh2add a0, a1, a0788; RV64ZBA-NEXT: lw a0, 0(a0)789; RV64ZBA-NEXT: ret790 %3 = lshr i32 %1, 3791 %4 = zext i32 %3 to i64792 %5 = getelementptr inbounds i32, ptr %0, i64 %4793 %6 = load i32, ptr %5, align 4794 ret i32 %6795}796 797define i64 @srliw_4_sh3add(ptr %0, i32 signext %1) {798; RV64I-LABEL: srliw_4_sh3add:799; RV64I: # %bb.0:800; RV64I-NEXT: srliw a1, a1, 4801; RV64I-NEXT: slli a1, a1, 3802; RV64I-NEXT: add a0, a0, a1803; RV64I-NEXT: ld a0, 0(a0)804; RV64I-NEXT: ret805;806; RV64ZBA-LABEL: srliw_4_sh3add:807; RV64ZBA: # %bb.0:808; RV64ZBA-NEXT: srliw a1, a1, 4809; RV64ZBA-NEXT: sh3add a0, a1, a0810; RV64ZBA-NEXT: ld a0, 0(a0)811; RV64ZBA-NEXT: ret812 %3 = lshr i32 %1, 4813 %4 = zext i32 %3 to i64814 %5 = getelementptr inbounds i64, ptr %0, i64 %4815 %6 = load i64, ptr %5, align 8816 ret i64 %6817}818 819define signext i32 @srli_1_sh2add(ptr %0, i64 %1) {820; RV64I-LABEL: srli_1_sh2add:821; RV64I: # %bb.0:822; RV64I-NEXT: srli a1, a1, 1823; RV64I-NEXT: slli a1, a1, 2824; RV64I-NEXT: add a0, a0, a1825; RV64I-NEXT: lw a0, 0(a0)826; RV64I-NEXT: ret827;828; RV64ZBA-LABEL: srli_1_sh2add:829; RV64ZBA: # %bb.0:830; RV64ZBA-NEXT: srli a1, a1, 1831; RV64ZBA-NEXT: sh2add a0, a1, a0832; RV64ZBA-NEXT: lw a0, 0(a0)833; RV64ZBA-NEXT: ret834 %3 = lshr i64 %1, 1835 %4 = getelementptr inbounds i32, ptr %0, i64 %3836 %5 = load i32, ptr %4, align 4837 ret i32 %5838}839 840define i64 @srli_2_sh3add(ptr %0, i64 %1) {841; RV64I-LABEL: srli_2_sh3add:842; RV64I: # %bb.0:843; RV64I-NEXT: srli a1, a1, 2844; RV64I-NEXT: slli a1, a1, 3845; RV64I-NEXT: add a0, a0, a1846; RV64I-NEXT: ld a0, 0(a0)847; RV64I-NEXT: ret848;849; RV64ZBA-LABEL: srli_2_sh3add:850; RV64ZBA: # %bb.0:851; RV64ZBA-NEXT: srli a1, a1, 2852; RV64ZBA-NEXT: sh3add a0, a1, a0853; RV64ZBA-NEXT: ld a0, 0(a0)854; RV64ZBA-NEXT: ret855 %3 = lshr i64 %1, 2856 %4 = getelementptr inbounds i64, ptr %0, i64 %3857 %5 = load i64, ptr %4, align 8858 ret i64 %5859}860 861define signext i16 @srli_2_sh1add(ptr %0, i64 %1) {862; RV64I-LABEL: srli_2_sh1add:863; RV64I: # %bb.0:864; RV64I-NEXT: srli a1, a1, 2865; RV64I-NEXT: slli a1, a1, 1866; RV64I-NEXT: add a0, a0, a1867; RV64I-NEXT: lh a0, 0(a0)868; RV64I-NEXT: ret869;870; RV64ZBA-LABEL: srli_2_sh1add:871; RV64ZBA: # %bb.0:872; RV64ZBA-NEXT: srli a1, a1, 2873; RV64ZBA-NEXT: sh1add a0, a1, a0874; RV64ZBA-NEXT: lh a0, 0(a0)875; RV64ZBA-NEXT: ret876 %3 = lshr i64 %1, 2877 %4 = getelementptr inbounds i16, ptr %0, i64 %3878 %5 = load i16, ptr %4, align 2879 ret i16 %5880}881 882define signext i32 @srli_3_sh2add(ptr %0, i64 %1) {883; RV64I-LABEL: srli_3_sh2add:884; RV64I: # %bb.0:885; RV64I-NEXT: srli a1, a1, 3886; RV64I-NEXT: slli a1, a1, 2887; RV64I-NEXT: add a0, a0, a1888; RV64I-NEXT: lw a0, 0(a0)889; RV64I-NEXT: ret890;891; RV64ZBA-LABEL: srli_3_sh2add:892; RV64ZBA: # %bb.0:893; RV64ZBA-NEXT: srli a1, a1, 3894; RV64ZBA-NEXT: sh2add a0, a1, a0895; RV64ZBA-NEXT: lw a0, 0(a0)896; RV64ZBA-NEXT: ret897 %3 = lshr i64 %1, 3898 %4 = getelementptr inbounds i32, ptr %0, i64 %3899 %5 = load i32, ptr %4, align 4900 ret i32 %5901}902 903define i64 @srli_4_sh3add(ptr %0, i64 %1) {904; RV64I-LABEL: srli_4_sh3add:905; RV64I: # %bb.0:906; RV64I-NEXT: srli a1, a1, 4907; RV64I-NEXT: slli a1, a1, 3908; RV64I-NEXT: add a0, a0, a1909; RV64I-NEXT: ld a0, 0(a0)910; RV64I-NEXT: ret911;912; RV64ZBA-LABEL: srli_4_sh3add:913; RV64ZBA: # %bb.0:914; RV64ZBA-NEXT: srli a1, a1, 4915; RV64ZBA-NEXT: sh3add a0, a1, a0916; RV64ZBA-NEXT: ld a0, 0(a0)917; RV64ZBA-NEXT: ret918 %3 = lshr i64 %1, 4919 %4 = getelementptr inbounds i64, ptr %0, i64 %3920 %5 = load i64, ptr %4, align 8921 ret i64 %5922}923 924define signext i16 @shl_2_sh1adduw(ptr %0, i32 signext %1) {925; RV64I-LABEL: shl_2_sh1adduw:926; RV64I: # %bb.0:927; RV64I-NEXT: slli a1, a1, 2928; RV64I-NEXT: slli a1, a1, 32929; RV64I-NEXT: srli a1, a1, 31930; RV64I-NEXT: add a0, a0, a1931; RV64I-NEXT: lh a0, 0(a0)932; RV64I-NEXT: ret933;934; RV64ZBA-LABEL: shl_2_sh1adduw:935; RV64ZBA: # %bb.0:936; RV64ZBA-NEXT: slli a1, a1, 2937; RV64ZBA-NEXT: sh1add.uw a0, a1, a0938; RV64ZBA-NEXT: lh a0, 0(a0)939; RV64ZBA-NEXT: ret940 %3 = shl i32 %1, 2941 %4 = zext i32 %3 to i64942 %5 = getelementptr inbounds i16, ptr %0, i64 %4943 %6 = load i16, ptr %5, align 2944 ret i16 %6945}946 947define signext i32 @shl_16_sh2adduw(ptr %0, i32 signext %1) {948; RV64I-LABEL: shl_16_sh2adduw:949; RV64I: # %bb.0:950; RV64I-NEXT: slli a1, a1, 16951; RV64I-NEXT: slli a1, a1, 32952; RV64I-NEXT: srli a1, a1, 30953; RV64I-NEXT: add a0, a0, a1954; RV64I-NEXT: lw a0, 0(a0)955; RV64I-NEXT: ret956;957; RV64ZBA-LABEL: shl_16_sh2adduw:958; RV64ZBA: # %bb.0:959; RV64ZBA-NEXT: slli a1, a1, 16960; RV64ZBA-NEXT: sh2add.uw a0, a1, a0961; RV64ZBA-NEXT: lw a0, 0(a0)962; RV64ZBA-NEXT: ret963 %3 = shl i32 %1, 16964 %4 = zext i32 %3 to i64965 %5 = getelementptr inbounds i32, ptr %0, i64 %4966 %6 = load i32, ptr %5, align 4967 ret i32 %6968}969 970define i64 @shl_31_sh3adduw(ptr %0, i32 signext %1) {971; RV64I-LABEL: shl_31_sh3adduw:972; RV64I: # %bb.0:973; RV64I-NEXT: slli a1, a1, 31974; RV64I-NEXT: slli a1, a1, 32975; RV64I-NEXT: srli a1, a1, 29976; RV64I-NEXT: add a0, a0, a1977; RV64I-NEXT: ld a0, 0(a0)978; RV64I-NEXT: ret979;980; RV64ZBA-LABEL: shl_31_sh3adduw:981; RV64ZBA: # %bb.0:982; RV64ZBA-NEXT: slli a1, a1, 31983; RV64ZBA-NEXT: sh3add.uw a0, a1, a0984; RV64ZBA-NEXT: ld a0, 0(a0)985; RV64ZBA-NEXT: ret986 %3 = shl i32 %1, 31987 %4 = zext i32 %3 to i64988 %5 = getelementptr inbounds i64, ptr %0, i64 %4989 %6 = load i64, ptr %5, align 8990 ret i64 %6991}992 993define i64 @pack_i64(i64 %a, i64 %b) nounwind {994; RV64I-LABEL: pack_i64:995; RV64I: # %bb.0:996; RV64I-NEXT: slli a0, a0, 32997; RV64I-NEXT: srli a0, a0, 32998; RV64I-NEXT: slli a1, a1, 32999; RV64I-NEXT: or a0, a1, a01000; RV64I-NEXT: ret1001;1002; RV64ZBA-LABEL: pack_i64:1003; RV64ZBA: # %bb.0:1004; RV64ZBA-NEXT: zext.w a0, a01005; RV64ZBA-NEXT: slli a1, a1, 321006; RV64ZBA-NEXT: or a0, a1, a01007; RV64ZBA-NEXT: ret1008 %shl = and i64 %a, 42949672951009 %shl1 = shl i64 %b, 321010 %or = or i64 %shl1, %shl1011 ret i64 %or1012}1013 1014define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {1015; RV64I-LABEL: pack_i64_2:1016; RV64I: # %bb.0:1017; RV64I-NEXT: slli a0, a0, 321018; RV64I-NEXT: slli a1, a1, 321019; RV64I-NEXT: srli a0, a0, 321020; RV64I-NEXT: srli a1, a1, 321021; RV64I-NEXT: slli a1, a1, 321022; RV64I-NEXT: or a0, a1, a01023; RV64I-NEXT: ret1024;1025; RV64ZBA-LABEL: pack_i64_2:1026; RV64ZBA: # %bb.0:1027; RV64ZBA-NEXT: zext.w a0, a01028; RV64ZBA-NEXT: zext.w a1, a11029; RV64ZBA-NEXT: slli a1, a1, 321030; RV64ZBA-NEXT: or a0, a1, a01031; RV64ZBA-NEXT: ret1032 %zexta = zext i32 %a to i641033 %zextb = zext i32 %b to i641034 %shl1 = shl i64 %zextb, 321035 %or = or i64 %shl1, %zexta1036 ret i64 %or1037}1038 1039define i64 @pack_i64_disjoint(i64 %a, i64 %b) nounwind {1040; RV64I-LABEL: pack_i64_disjoint:1041; RV64I: # %bb.0:1042; RV64I-NEXT: slli a0, a0, 321043; RV64I-NEXT: srli a0, a0, 321044; RV64I-NEXT: or a0, a1, a01045; RV64I-NEXT: ret1046;1047; RV64ZBA-LABEL: pack_i64_disjoint:1048; RV64ZBA: # %bb.0:1049; RV64ZBA-NEXT: zext.w a0, a01050; RV64ZBA-NEXT: or a0, a1, a01051; RV64ZBA-NEXT: ret1052 %shl = and i64 %a, 42949672951053 %or = or disjoint i64 %b, %shl1054 ret i64 %or1055}1056 1057define i64 @pack_i64_disjoint_2(i32 signext %a, i64 %b) nounwind {1058; RV64I-LABEL: pack_i64_disjoint_2:1059; RV64I: # %bb.0:1060; RV64I-NEXT: slli a0, a0, 321061; RV64I-NEXT: srli a0, a0, 321062; RV64I-NEXT: or a0, a1, a01063; RV64I-NEXT: ret1064;1065; RV64ZBA-LABEL: pack_i64_disjoint_2:1066; RV64ZBA: # %bb.0:1067; RV64ZBA-NEXT: zext.w a0, a01068; RV64ZBA-NEXT: or a0, a1, a01069; RV64ZBA-NEXT: ret1070 %zexta = zext i32 %a to i641071 %or = or disjoint i64 %b, %zexta1072 ret i64 %or1073}1074 1075define i8 @array_index_sh1_sh0(ptr %p, i64 %idx1, i64 %idx2) {1076; RV64I-LABEL: array_index_sh1_sh0:1077; RV64I: # %bb.0:1078; RV64I-NEXT: slli a1, a1, 11079; RV64I-NEXT: add a0, a0, a21080; RV64I-NEXT: add a0, a0, a11081; RV64I-NEXT: lbu a0, 0(a0)1082; RV64I-NEXT: ret1083;1084; RV64ZBA-LABEL: array_index_sh1_sh0:1085; RV64ZBA: # %bb.0:1086; RV64ZBA-NEXT: sh1add a0, a1, a01087; RV64ZBA-NEXT: add a0, a0, a21088; RV64ZBA-NEXT: lbu a0, 0(a0)1089; RV64ZBA-NEXT: ret1090 %a = getelementptr inbounds [2 x i8], ptr %p, i64 %idx1, i64 %idx21091 %b = load i8, ptr %a, align 11092 ret i8 %b1093}1094 1095define i16 @array_index_sh1_sh1(ptr %p, i64 %idx1, i64 %idx2) {1096; RV64I-LABEL: array_index_sh1_sh1:1097; RV64I: # %bb.0:1098; RV64I-NEXT: slli a1, a1, 21099; RV64I-NEXT: add a0, a0, a11100; RV64I-NEXT: slli a2, a2, 11101; RV64I-NEXT: add a0, a0, a21102; RV64I-NEXT: lh a0, 0(a0)1103; RV64I-NEXT: ret1104;1105; RV64ZBA-LABEL: array_index_sh1_sh1:1106; RV64ZBA: # %bb.0:1107; RV64ZBA-NEXT: sh2add a0, a1, a01108; RV64ZBA-NEXT: sh1add a0, a2, a01109; RV64ZBA-NEXT: lh a0, 0(a0)1110; RV64ZBA-NEXT: ret1111 %a = getelementptr inbounds [2 x i16], ptr %p, i64 %idx1, i64 %idx21112 %b = load i16, ptr %a, align 21113 ret i16 %b1114}1115 1116define i32 @array_index_sh1_sh2(ptr %p, i64 %idx1, i64 %idx2) {1117; RV64I-LABEL: array_index_sh1_sh2:1118; RV64I: # %bb.0:1119; RV64I-NEXT: slli a1, a1, 31120; RV64I-NEXT: add a0, a0, a11121; RV64I-NEXT: slli a2, a2, 21122; RV64I-NEXT: add a0, a0, a21123; RV64I-NEXT: lw a0, 0(a0)1124; RV64I-NEXT: ret1125;1126; RV64ZBA-LABEL: array_index_sh1_sh2:1127; RV64ZBA: # %bb.0:1128; RV64ZBA-NEXT: sh3add a0, a1, a01129; RV64ZBA-NEXT: sh2add a0, a2, a01130; RV64ZBA-NEXT: lw a0, 0(a0)1131; RV64ZBA-NEXT: ret1132 %a = getelementptr inbounds [2 x i32], ptr %p, i64 %idx1, i64 %idx21133 %b = load i32, ptr %a, align 41134 ret i32 %b1135}1136 1137define i64 @array_index_sh1_sh3(ptr %p, i64 %idx1, i64 %idx2) {1138; RV64I-LABEL: array_index_sh1_sh3:1139; RV64I: # %bb.0:1140; RV64I-NEXT: slli a1, a1, 41141; RV64I-NEXT: add a0, a0, a11142; RV64I-NEXT: slli a2, a2, 31143; RV64I-NEXT: add a0, a0, a21144; RV64I-NEXT: ld a0, 0(a0)1145; RV64I-NEXT: ret1146;1147; RV64ZBA-LABEL: array_index_sh1_sh3:1148; RV64ZBA: # %bb.0:1149; RV64ZBA-NEXT: sh1add a1, a1, a21150; RV64ZBA-NEXT: sh3add a0, a1, a01151; RV64ZBA-NEXT: ld a0, 0(a0)1152; RV64ZBA-NEXT: ret1153 %a = getelementptr inbounds [2 x i64], ptr %p, i64 %idx1, i64 %idx21154 %b = load i64, ptr %a, align 81155 ret i64 %b1156}1157 1158define i8 @array_index_sh2_sh0(ptr %p, i64 %idx1, i64 %idx2) {1159; RV64I-LABEL: array_index_sh2_sh0:1160; RV64I: # %bb.0:1161; RV64I-NEXT: slli a1, a1, 21162; RV64I-NEXT: add a0, a0, a21163; RV64I-NEXT: add a0, a0, a11164; RV64I-NEXT: lbu a0, 0(a0)1165; RV64I-NEXT: ret1166;1167; RV64ZBA-LABEL: array_index_sh2_sh0:1168; RV64ZBA: # %bb.0:1169; RV64ZBA-NEXT: sh2add a0, a1, a01170; RV64ZBA-NEXT: add a0, a0, a21171; RV64ZBA-NEXT: lbu a0, 0(a0)1172; RV64ZBA-NEXT: ret1173 %a = getelementptr inbounds [4 x i8], ptr %p, i64 %idx1, i64 %idx21174 %b = load i8, ptr %a, align 11175 ret i8 %b1176}1177 1178define i16 @array_index_sh2_sh1(ptr %p, i64 %idx1, i64 %idx2) {1179; RV64I-LABEL: array_index_sh2_sh1:1180; RV64I: # %bb.0:1181; RV64I-NEXT: slli a1, a1, 31182; RV64I-NEXT: add a0, a0, a11183; RV64I-NEXT: slli a2, a2, 11184; RV64I-NEXT: add a0, a0, a21185; RV64I-NEXT: lh a0, 0(a0)1186; RV64I-NEXT: ret1187;1188; RV64ZBA-LABEL: array_index_sh2_sh1:1189; RV64ZBA: # %bb.0:1190; RV64ZBA-NEXT: sh3add a0, a1, a01191; RV64ZBA-NEXT: sh1add a0, a2, a01192; RV64ZBA-NEXT: lh a0, 0(a0)1193; RV64ZBA-NEXT: ret1194 %a = getelementptr inbounds [4 x i16], ptr %p, i64 %idx1, i64 %idx21195 %b = load i16, ptr %a, align 21196 ret i16 %b1197}1198 1199define i32 @array_index_sh2_sh2(ptr %p, i64 %idx1, i64 %idx2) {1200; RV64I-LABEL: array_index_sh2_sh2:1201; RV64I: # %bb.0:1202; RV64I-NEXT: slli a1, a1, 41203; RV64I-NEXT: add a0, a0, a11204; RV64I-NEXT: slli a2, a2, 21205; RV64I-NEXT: add a0, a0, a21206; RV64I-NEXT: lw a0, 0(a0)1207; RV64I-NEXT: ret1208;1209; RV64ZBA-LABEL: array_index_sh2_sh2:1210; RV64ZBA: # %bb.0:1211; RV64ZBA-NEXT: sh2add a1, a1, a21212; RV64ZBA-NEXT: sh2add a0, a1, a01213; RV64ZBA-NEXT: lw a0, 0(a0)1214; RV64ZBA-NEXT: ret1215 %a = getelementptr inbounds [4 x i32], ptr %p, i64 %idx1, i64 %idx21216 %b = load i32, ptr %a, align 41217 ret i32 %b1218}1219 1220define i64 @array_index_sh2_sh3(ptr %p, i64 %idx1, i64 %idx2) {1221; RV64I-LABEL: array_index_sh2_sh3:1222; RV64I: # %bb.0:1223; RV64I-NEXT: slli a1, a1, 51224; RV64I-NEXT: add a0, a0, a11225; RV64I-NEXT: slli a2, a2, 31226; RV64I-NEXT: add a0, a0, a21227; RV64I-NEXT: ld a0, 0(a0)1228; RV64I-NEXT: ret1229;1230; RV64ZBA-LABEL: array_index_sh2_sh3:1231; RV64ZBA: # %bb.0:1232; RV64ZBA-NEXT: sh2add a1, a1, a21233; RV64ZBA-NEXT: sh3add a0, a1, a01234; RV64ZBA-NEXT: ld a0, 0(a0)1235; RV64ZBA-NEXT: ret1236 %a = getelementptr inbounds [4 x i64], ptr %p, i64 %idx1, i64 %idx21237 %b = load i64, ptr %a, align 81238 ret i64 %b1239}1240 1241define i8 @array_index_sh3_sh0(ptr %p, i64 %idx1, i64 %idx2) {1242; RV64I-LABEL: array_index_sh3_sh0:1243; RV64I: # %bb.0:1244; RV64I-NEXT: slli a1, a1, 31245; RV64I-NEXT: add a0, a0, a21246; RV64I-NEXT: add a0, a0, a11247; RV64I-NEXT: lbu a0, 0(a0)1248; RV64I-NEXT: ret1249;1250; RV64ZBA-LABEL: array_index_sh3_sh0:1251; RV64ZBA: # %bb.0:1252; RV64ZBA-NEXT: sh3add a0, a1, a01253; RV64ZBA-NEXT: add a0, a0, a21254; RV64ZBA-NEXT: lbu a0, 0(a0)1255; RV64ZBA-NEXT: ret1256 %a = getelementptr inbounds [8 x i8], ptr %p, i64 %idx1, i64 %idx21257 %b = load i8, ptr %a, align 11258 ret i8 %b1259}1260 1261define i16 @array_index_sh3_sh1(ptr %p, i64 %idx1, i64 %idx2) {1262; RV64I-LABEL: array_index_sh3_sh1:1263; RV64I: # %bb.0:1264; RV64I-NEXT: slli a1, a1, 41265; RV64I-NEXT: add a0, a0, a11266; RV64I-NEXT: slli a2, a2, 11267; RV64I-NEXT: add a0, a0, a21268; RV64I-NEXT: lh a0, 0(a0)1269; RV64I-NEXT: ret1270;1271; RV64ZBA-LABEL: array_index_sh3_sh1:1272; RV64ZBA: # %bb.0:1273; RV64ZBA-NEXT: sh3add a1, a1, a21274; RV64ZBA-NEXT: sh1add a0, a1, a01275; RV64ZBA-NEXT: lh a0, 0(a0)1276; RV64ZBA-NEXT: ret1277 %a = getelementptr inbounds [8 x i16], ptr %p, i64 %idx1, i64 %idx21278 %b = load i16, ptr %a, align 21279 ret i16 %b1280}1281 1282define i32 @array_index_sh3_sh2(ptr %p, i64 %idx1, i64 %idx2) {1283; RV64I-LABEL: array_index_sh3_sh2:1284; RV64I: # %bb.0:1285; RV64I-NEXT: slli a1, a1, 51286; RV64I-NEXT: add a0, a0, a11287; RV64I-NEXT: slli a2, a2, 21288; RV64I-NEXT: add a0, a0, a21289; RV64I-NEXT: lw a0, 0(a0)1290; RV64I-NEXT: ret1291;1292; RV64ZBA-LABEL: array_index_sh3_sh2:1293; RV64ZBA: # %bb.0:1294; RV64ZBA-NEXT: sh3add a1, a1, a21295; RV64ZBA-NEXT: sh2add a0, a1, a01296; RV64ZBA-NEXT: lw a0, 0(a0)1297; RV64ZBA-NEXT: ret1298 %a = getelementptr inbounds [8 x i32], ptr %p, i64 %idx1, i64 %idx21299 %b = load i32, ptr %a, align 41300 ret i32 %b1301}1302 1303define i64 @array_index_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) {1304; RV64I-LABEL: array_index_sh3_sh3:1305; RV64I: # %bb.0:1306; RV64I-NEXT: slli a1, a1, 61307; RV64I-NEXT: add a0, a0, a11308; RV64I-NEXT: slli a2, a2, 31309; RV64I-NEXT: add a0, a0, a21310; RV64I-NEXT: ld a0, 0(a0)1311; RV64I-NEXT: ret1312;1313; RV64ZBA-LABEL: array_index_sh3_sh3:1314; RV64ZBA: # %bb.0:1315; RV64ZBA-NEXT: sh3add a1, a1, a21316; RV64ZBA-NEXT: sh3add a0, a1, a01317; RV64ZBA-NEXT: ld a0, 0(a0)1318; RV64ZBA-NEXT: ret1319 %a = getelementptr inbounds [8 x i64], ptr %p, i64 %idx1, i64 %idx21320 %b = load i64, ptr %a, align 81321 ret i64 %b1322}1323 1324; Similar to above, but with a lshr on one of the indices. This requires1325; special handling during isel to form a shift pair.1326define i64 @array_index_lshr_sh3_sh3(ptr %p, i64 %idx1, i64 %idx2) {1327; RV64I-LABEL: array_index_lshr_sh3_sh3:1328; RV64I: # %bb.0:1329; RV64I-NEXT: srli a1, a1, 581330; RV64I-NEXT: slli a2, a2, 31331; RV64I-NEXT: slli a1, a1, 61332; RV64I-NEXT: add a0, a0, a21333; RV64I-NEXT: add a0, a0, a11334; RV64I-NEXT: ld a0, 0(a0)1335; RV64I-NEXT: ret1336;1337; RV64ZBA-LABEL: array_index_lshr_sh3_sh3:1338; RV64ZBA: # %bb.0:1339; RV64ZBA-NEXT: srli a1, a1, 581340; RV64ZBA-NEXT: sh3add a1, a1, a21341; RV64ZBA-NEXT: sh3add a0, a1, a01342; RV64ZBA-NEXT: ld a0, 0(a0)1343; RV64ZBA-NEXT: ret1344 %shr = lshr i64 %idx1, 581345 %a = getelementptr inbounds [8 x i64], ptr %p, i64 %shr, i64 %idx21346 %b = load i64, ptr %a, align 81347 ret i64 %b1348}1349 1350define i8 @array_index_sh4_sh0(ptr %p, i64 %idx1, i64 %idx2) {1351; CHECK-LABEL: array_index_sh4_sh0:1352; CHECK: # %bb.0:1353; CHECK-NEXT: slli a1, a1, 41354; CHECK-NEXT: add a0, a0, a21355; CHECK-NEXT: add a0, a0, a11356; CHECK-NEXT: lbu a0, 0(a0)1357; CHECK-NEXT: ret1358 %a = getelementptr inbounds [16 x i8], ptr %p, i64 %idx1, i64 %idx21359 %b = load i8, ptr %a, align 11360 ret i8 %b1361}1362 1363define i16 @array_index_sh4_sh1(ptr %p, i64 %idx1, i64 %idx2) {1364; RV64I-LABEL: array_index_sh4_sh1:1365; RV64I: # %bb.0:1366; RV64I-NEXT: slli a1, a1, 51367; RV64I-NEXT: add a0, a0, a11368; RV64I-NEXT: slli a2, a2, 11369; RV64I-NEXT: add a0, a0, a21370; RV64I-NEXT: lh a0, 0(a0)1371; RV64I-NEXT: ret1372;1373; RV64ZBA-LABEL: array_index_sh4_sh1:1374; RV64ZBA: # %bb.0:1375; RV64ZBA-NEXT: slli a1, a1, 51376; RV64ZBA-NEXT: add a0, a0, a11377; RV64ZBA-NEXT: sh1add a0, a2, a01378; RV64ZBA-NEXT: lh a0, 0(a0)1379; RV64ZBA-NEXT: ret1380 %a = getelementptr inbounds [16 x i16], ptr %p, i64 %idx1, i64 %idx21381 %b = load i16, ptr %a, align 21382 ret i16 %b1383}1384 1385define i32 @array_index_sh4_sh2(ptr %p, i64 %idx1, i64 %idx2) {1386; RV64I-LABEL: array_index_sh4_sh2:1387; RV64I: # %bb.0:1388; RV64I-NEXT: slli a1, a1, 61389; RV64I-NEXT: add a0, a0, a11390; RV64I-NEXT: slli a2, a2, 21391; RV64I-NEXT: add a0, a0, a21392; RV64I-NEXT: lw a0, 0(a0)1393; RV64I-NEXT: ret1394;1395; RV64ZBA-LABEL: array_index_sh4_sh2:1396; RV64ZBA: # %bb.0:1397; RV64ZBA-NEXT: slli a1, a1, 61398; RV64ZBA-NEXT: add a0, a0, a11399; RV64ZBA-NEXT: sh2add a0, a2, a01400; RV64ZBA-NEXT: lw a0, 0(a0)1401; RV64ZBA-NEXT: ret1402 %a = getelementptr inbounds [16 x i32], ptr %p, i64 %idx1, i64 %idx21403 %b = load i32, ptr %a, align 41404 ret i32 %b1405}1406 1407define i64 @array_index_sh4_sh3(ptr %p, i64 %idx1, i64 %idx2) {1408; RV64I-LABEL: array_index_sh4_sh3:1409; RV64I: # %bb.0:1410; RV64I-NEXT: slli a1, a1, 71411; RV64I-NEXT: add a0, a0, a11412; RV64I-NEXT: slli a2, a2, 31413; RV64I-NEXT: add a0, a0, a21414; RV64I-NEXT: ld a0, 0(a0)1415; RV64I-NEXT: ret1416;1417; RV64ZBA-LABEL: array_index_sh4_sh3:1418; RV64ZBA: # %bb.0:1419; RV64ZBA-NEXT: slli a1, a1, 71420; RV64ZBA-NEXT: add a0, a0, a11421; RV64ZBA-NEXT: sh3add a0, a2, a01422; RV64ZBA-NEXT: ld a0, 0(a0)1423; RV64ZBA-NEXT: ret1424 %a = getelementptr inbounds [16 x i64], ptr %p, i64 %idx1, i64 %idx21425 %b = load i64, ptr %a, align 81426 ret i64 %b1427}1428 1429define ptr @gep_lshr_i32(ptr %0, i64 %1) {1430; RV64I-LABEL: gep_lshr_i32:1431; RV64I: # %bb.0: # %entry1432; RV64I-NEXT: srli a1, a1, 21433; RV64I-NEXT: slli a1, a1, 321434; RV64I-NEXT: srli a1, a1, 321435; RV64I-NEXT: li a2, 801436; RV64I-NEXT: mul a1, a1, a21437; RV64I-NEXT: add a0, a0, a11438; RV64I-NEXT: ret1439;1440; RV64ZBA-LABEL: gep_lshr_i32:1441; RV64ZBA: # %bb.0: # %entry1442; RV64ZBA-NEXT: srli a1, a1, 21443; RV64ZBA-NEXT: zext.w a1, a11444; RV64ZBA-NEXT: li a2, 801445; RV64ZBA-NEXT: mul a1, a1, a21446; RV64ZBA-NEXT: add a0, a0, a11447; RV64ZBA-NEXT: ret1448entry:1449 %2 = lshr exact i64 %1, 21450 %3 = and i64 %2, 42949672951451 %5 = getelementptr [80 x i8], ptr %0, i64 %31452 ret ptr %51453}1454 1455define i64 @srli_slliuw(i64 %1) {1456; RV64I-LABEL: srli_slliuw:1457; RV64I: # %bb.0: # %entry1458; RV64I-NEXT: srli a0, a0, 21459; RV64I-NEXT: slli a0, a0, 321460; RV64I-NEXT: srli a0, a0, 281461; RV64I-NEXT: ret1462;1463; RV64ZBA-LABEL: srli_slliuw:1464; RV64ZBA: # %bb.0: # %entry1465; RV64ZBA-NEXT: srli a0, a0, 21466; RV64ZBA-NEXT: slli.uw a0, a0, 41467; RV64ZBA-NEXT: ret1468entry:1469 %2 = lshr exact i64 %1, 21470 %3 = and i64 %2, 42949672951471 %4 = shl i64 %3, 41472 ret i64 %41473}1474 1475define i64 @srli_slliuw_canonical(i64 %0) {1476; RV64I-LABEL: srli_slliuw_canonical:1477; RV64I: # %bb.0: # %entry1478; RV64I-NEXT: li a1, 11479; RV64I-NEXT: slli a1, a1, 361480; RV64I-NEXT: addi a1, a1, -161481; RV64I-NEXT: slli a0, a0, 21482; RV64I-NEXT: and a0, a0, a11483; RV64I-NEXT: ret1484;1485; RV64ZBA-LABEL: srli_slliuw_canonical:1486; RV64ZBA: # %bb.0: # %entry1487; RV64ZBA-NEXT: slli a0, a0, 21488; RV64ZBA-NEXT: srli a0, a0, 41489; RV64ZBA-NEXT: slli.uw a0, a0, 41490; RV64ZBA-NEXT: ret1491entry:1492 %1 = shl i64 %0, 21493 %2 = and i64 %1, 687194767201494 ret i64 %21495}1496 1497; Make sure we don't accidentally use slli.uw with a shift of 32.1498define i64 @srli_slliuw_negative_test(i64 %0) {1499; CHECK-LABEL: srli_slliuw_negative_test:1500; CHECK: # %bb.0: # %entry1501; CHECK-NEXT: srli a0, a0, 61502; CHECK-NEXT: slli a0, a0, 321503; CHECK-NEXT: ret1504entry:1505 %1 = lshr i64 %0, 61506 %2 = shl i64 %1, 321507 ret i64 %21508}1509 1510define i64 @srli_slli_i16(i64 %1) {1511; RV64I-LABEL: srli_slli_i16:1512; RV64I: # %bb.0: # %entry1513; RV64I-NEXT: srli a0, a0, 21514; RV64I-NEXT: slli a0, a0, 481515; RV64I-NEXT: srli a0, a0, 481516; RV64I-NEXT: slli a0, a0, 41517; RV64I-NEXT: ret1518;1519; RV64ZBANOZBB-LABEL: srli_slli_i16:1520; RV64ZBANOZBB: # %bb.0: # %entry1521; RV64ZBANOZBB-NEXT: srli a0, a0, 21522; RV64ZBANOZBB-NEXT: slli a0, a0, 481523; RV64ZBANOZBB-NEXT: srli a0, a0, 481524; RV64ZBANOZBB-NEXT: slli a0, a0, 41525; RV64ZBANOZBB-NEXT: ret1526;1527; RV64ZBAZBB-LABEL: srli_slli_i16:1528; RV64ZBAZBB: # %bb.0: # %entry1529; RV64ZBAZBB-NEXT: srli a0, a0, 21530; RV64ZBAZBB-NEXT: zext.h a0, a01531; RV64ZBAZBB-NEXT: slli a0, a0, 41532; RV64ZBAZBB-NEXT: ret1533entry:1534 %2 = lshr exact i64 %1, 21535 %3 = and i64 %2, 655351536 %4 = shl i64 %3, 41537 ret i64 %41538}1539 1540define i64 @srli_slliuw_2(i64 %1) {1541; RV64I-LABEL: srli_slliuw_2:1542; RV64I: # %bb.0: # %entry1543; RV64I-NEXT: srli a0, a0, 181544; RV64I-NEXT: slli a0, a0, 321545; RV64I-NEXT: srli a0, a0, 291546; RV64I-NEXT: ret1547;1548; RV64ZBA-LABEL: srli_slliuw_2:1549; RV64ZBA: # %bb.0: # %entry1550; RV64ZBA-NEXT: srli a0, a0, 181551; RV64ZBA-NEXT: slli.uw a0, a0, 31552; RV64ZBA-NEXT: ret1553entry:1554 %2 = lshr i64 %1, 181555 %3 = and i64 %2, 42949672951556 %4 = shl i64 %3, 31557 ret i64 %41558}1559 1560define i64 @srli_slliuw_canonical_2(i64 %0) {1561; RV64I-LABEL: srli_slliuw_canonical_2:1562; RV64I: # %bb.0: # %entry1563; RV64I-NEXT: li a1, 11564; RV64I-NEXT: slli a1, a1, 351565; RV64I-NEXT: addi a1, a1, -81566; RV64I-NEXT: srli a0, a0, 151567; RV64I-NEXT: and a0, a0, a11568; RV64I-NEXT: ret1569;1570; RV64ZBA-LABEL: srli_slliuw_canonical_2:1571; RV64ZBA: # %bb.0: # %entry1572; RV64ZBA-NEXT: srli a0, a0, 151573; RV64ZBA-NEXT: srli a0, a0, 31574; RV64ZBA-NEXT: slli.uw a0, a0, 31575; RV64ZBA-NEXT: ret1576entry:1577 %1 = lshr i64 %0, 151578 %2 = and i64 %1, 343597383601579 ret i64 %21580}1581 1582define ptr @srai_srli_sh3add(ptr %0, i64 %1) nounwind {1583; RV64I-LABEL: srai_srli_sh3add:1584; RV64I: # %bb.0: # %entry1585; RV64I-NEXT: srai a1, a1, 321586; RV64I-NEXT: srli a1, a1, 61587; RV64I-NEXT: slli a1, a1, 31588; RV64I-NEXT: add a0, a0, a11589; RV64I-NEXT: ret1590;1591; RV64ZBA-LABEL: srai_srli_sh3add:1592; RV64ZBA: # %bb.0: # %entry1593; RV64ZBA-NEXT: srai a1, a1, 321594; RV64ZBA-NEXT: srli a1, a1, 61595; RV64ZBA-NEXT: sh3add a0, a1, a01596; RV64ZBA-NEXT: ret1597entry:1598 %2 = ashr i64 %1, 321599 %3 = lshr i64 %2, 61600 %4 = getelementptr i64, ptr %0, i64 %31601 ret ptr %41602}1603 1604define ptr @srai_srli_slli(ptr %0, i64 %1) nounwind {1605; CHECK-LABEL: srai_srli_slli:1606; CHECK: # %bb.0: # %entry1607; CHECK-NEXT: srai a1, a1, 321608; CHECK-NEXT: srli a1, a1, 61609; CHECK-NEXT: slli a1, a1, 41610; CHECK-NEXT: add a0, a0, a11611; CHECK-NEXT: ret1612entry:1613 %2 = ashr i64 %1, 321614 %3 = lshr i64 %2, 61615 %4 = getelementptr i128, ptr %0, i64 %31616 ret ptr %41617}1618 1619; Negative to make sure the peephole added for srai_srli_slli and1620; srai_srli_sh3add doesn't break this.1621define i64 @srai_andi(i64 %x) nounwind {1622; CHECK-LABEL: srai_andi:1623; CHECK: # %bb.0: # %entry1624; CHECK-NEXT: srai a0, a0, 81625; CHECK-NEXT: andi a0, a0, -81626; CHECK-NEXT: ret1627entry:1628 %y = ashr i64 %x, 81629 %z = and i64 %y, -81630 ret i64 %z1631}1632 1633; Negative to make sure the peephole added for srai_srli_slli and1634; srai_srli_sh3add doesn't break this.1635define i64 @srai_lui_and(i64 %x) nounwind {1636; CHECK-LABEL: srai_lui_and:1637; CHECK: # %bb.0: # %entry1638; CHECK-NEXT: lui a1, 10485741639; CHECK-NEXT: srai a0, a0, 81640; CHECK-NEXT: and a0, a0, a11641; CHECK-NEXT: ret1642entry:1643 %y = ashr i64 %x, 81644 %z = and i64 %y, -81921645 ret i64 %z1646}1647 1648define i64 @add_u32simm32_zextw(i64 %x) nounwind {1649; RV64I-LABEL: add_u32simm32_zextw:1650; RV64I: # %bb.0: # %entry1651; RV64I-NEXT: li a1, 11652; RV64I-NEXT: slli a1, a1, 321653; RV64I-NEXT: addi a1, a1, -21654; RV64I-NEXT: add a0, a0, a11655; RV64I-NEXT: addi a1, a1, 11656; RV64I-NEXT: and a0, a0, a11657; RV64I-NEXT: ret1658;1659; RV64ZBA-LABEL: add_u32simm32_zextw:1660; RV64ZBA: # %bb.0: # %entry1661; RV64ZBA-NEXT: li a1, -21662; RV64ZBA-NEXT: zext.w a1, a11663; RV64ZBA-NEXT: add a0, a0, a11664; RV64ZBA-NEXT: zext.w a0, a01665; RV64ZBA-NEXT: ret1666entry:1667 %add = add i64 %x, 42949672941668 %and = and i64 %add, 42949672951669 ret i64 %and1670}1671