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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \3; RUN: | FileCheck %s -check-prefix=RV64I4; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbkb -verify-machineinstrs < %s \5; RUN: | FileCheck %s -check-prefix=RV64ZBKB6 7; FIXME: Use packw8define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {9; RV64I-LABEL: pack_i32:10; RV64I: # %bb.0:11; RV64I-NEXT: slli a0, a0, 4812; RV64I-NEXT: srli a0, a0, 4813; RV64I-NEXT: slliw a1, a1, 1614; RV64I-NEXT: or a0, a1, a015; RV64I-NEXT: ret16;17; RV64ZBKB-LABEL: pack_i32:18; RV64ZBKB: # %bb.0:19; RV64ZBKB-NEXT: packw a0, a0, a120; RV64ZBKB-NEXT: ret21 %shl = and i32 %a, 6553522 %shl1 = shl i32 %b, 1623 %or = or i32 %shl1, %shl24 ret i32 %or25}26 27; FIXME: Use packw28define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {29; RV64I-LABEL: pack_i32_2:30; RV64I: # %bb.0:31; RV64I-NEXT: slli a1, a1, 1632; RV64I-NEXT: or a0, a1, a033; RV64I-NEXT: sext.w a0, a034; RV64I-NEXT: ret35;36; RV64ZBKB-LABEL: pack_i32_2:37; RV64ZBKB: # %bb.0:38; RV64ZBKB-NEXT: packw a0, a0, a139; RV64ZBKB-NEXT: ret40 %zexta = zext i16 %a to i3241 %zextb = zext i16 %b to i3242 %shl1 = shl i32 %zextb, 1643 %or = or i32 %shl1, %zexta44 ret i32 %or45}46 47; Test case where we don't have a sign_extend_inreg after the or.48; FIXME: Use packw49define signext i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 signext %2) {50; RV64I-LABEL: pack_i32_3:51; RV64I: # %bb.0:52; RV64I-NEXT: slli a0, a0, 1653; RV64I-NEXT: or a0, a0, a154; RV64I-NEXT: addw a0, a0, a255; RV64I-NEXT: ret56;57; RV64ZBKB-LABEL: pack_i32_3:58; RV64ZBKB: # %bb.0:59; RV64ZBKB-NEXT: packw a0, a1, a060; RV64ZBKB-NEXT: addw a0, a0, a261; RV64ZBKB-NEXT: ret62 %4 = zext i16 %0 to i3263 %5 = shl nuw i32 %4, 1664 %6 = zext i16 %1 to i3265 %7 = or i32 %5, %666 %8 = add i32 %7, %267 ret i32 %868}69 70define i64 @pack_i64(i64 %a, i64 %b) nounwind {71; RV64I-LABEL: pack_i64:72; RV64I: # %bb.0:73; RV64I-NEXT: slli a0, a0, 3274; RV64I-NEXT: srli a0, a0, 3275; RV64I-NEXT: slli a1, a1, 3276; RV64I-NEXT: or a0, a1, a077; RV64I-NEXT: ret78;79; RV64ZBKB-LABEL: pack_i64:80; RV64ZBKB: # %bb.0:81; RV64ZBKB-NEXT: pack a0, a0, a182; RV64ZBKB-NEXT: ret83 %shl = and i64 %a, 429496729584 %shl1 = shl i64 %b, 3285 %or = or i64 %shl1, %shl86 ret i64 %or87}88 89; FIXME: The slli+srli isn't needed with pack.90define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {91; RV64I-LABEL: pack_i64_2:92; RV64I: # %bb.0:93; RV64I-NEXT: slli a0, a0, 3294; RV64I-NEXT: slli a1, a1, 3295; RV64I-NEXT: srli a0, a0, 3296; RV64I-NEXT: srli a1, a1, 3297; RV64I-NEXT: slli a1, a1, 3298; RV64I-NEXT: or a0, a1, a099; RV64I-NEXT: ret100;101; RV64ZBKB-LABEL: pack_i64_2:102; RV64ZBKB: # %bb.0:103; RV64ZBKB-NEXT: slli a1, a1, 32104; RV64ZBKB-NEXT: srli a1, a1, 32105; RV64ZBKB-NEXT: pack a0, a0, a1106; RV64ZBKB-NEXT: ret107 %zexta = zext i32 %a to i64108 %zextb = zext i32 %b to i64109 %shl1 = shl i64 %zextb, 32110 %or = or i64 %shl1, %zexta111 ret i64 %or112}113 114define i64 @pack_i64_3(ptr %0, ptr %1) {115; RV64I-LABEL: pack_i64_3:116; RV64I: # %bb.0:117; RV64I-NEXT: lw a0, 0(a0)118; RV64I-NEXT: lwu a1, 0(a1)119; RV64I-NEXT: slli a0, a0, 32120; RV64I-NEXT: or a0, a0, a1121; RV64I-NEXT: ret122;123; RV64ZBKB-LABEL: pack_i64_3:124; RV64ZBKB: # %bb.0:125; RV64ZBKB-NEXT: lw a0, 0(a0)126; RV64ZBKB-NEXT: lw a1, 0(a1)127; RV64ZBKB-NEXT: pack a0, a1, a0128; RV64ZBKB-NEXT: ret129 %3 = load i32, ptr %0, align 4130 %4 = zext i32 %3 to i64131 %5 = shl i64 %4, 32132 %6 = load i32, ptr %1, align 4133 %7 = zext i32 %6 to i64134 %8 = or i64 %5, %7135 ret i64 %8136}137 138; FIXME: Use packh139define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {140; RV64I-LABEL: packh_i32:141; RV64I: # %bb.0:142; RV64I-NEXT: lui a2, 16143; RV64I-NEXT: zext.b a0, a0144; RV64I-NEXT: addi a2, a2, -256145; RV64I-NEXT: slli a1, a1, 8146; RV64I-NEXT: and a1, a1, a2147; RV64I-NEXT: or a0, a1, a0148; RV64I-NEXT: ret149;150; RV64ZBKB-LABEL: packh_i32:151; RV64ZBKB: # %bb.0:152; RV64ZBKB-NEXT: lui a2, 16153; RV64ZBKB-NEXT: zext.b a0, a0154; RV64ZBKB-NEXT: addi a2, a2, -256155; RV64ZBKB-NEXT: slli a1, a1, 8156; RV64ZBKB-NEXT: and a1, a1, a2157; RV64ZBKB-NEXT: or a0, a1, a0158; RV64ZBKB-NEXT: ret159 %and = and i32 %a, 255160 %and1 = shl i32 %b, 8161 %shl = and i32 %and1, 65280162 %or = or i32 %shl, %and163 ret i32 %or164}165 166define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {167; RV64I-LABEL: packh_i32_2:168; RV64I: # %bb.0:169; RV64I-NEXT: zext.b a0, a0170; RV64I-NEXT: zext.b a1, a1171; RV64I-NEXT: slli a1, a1, 8172; RV64I-NEXT: or a0, a1, a0173; RV64I-NEXT: ret174;175; RV64ZBKB-LABEL: packh_i32_2:176; RV64ZBKB: # %bb.0:177; RV64ZBKB-NEXT: packh a0, a0, a1178; RV64ZBKB-NEXT: ret179 %and = and i32 %a, 255180 %and1 = and i32 %b, 255181 %shl = shl i32 %and1, 8182 %or = or i32 %shl, %and183 ret i32 %or184}185 186; FIXME: Use packh187define i64 @packh_i64(i64 %a, i64 %b) nounwind {188; RV64I-LABEL: packh_i64:189; RV64I: # %bb.0:190; RV64I-NEXT: lui a2, 16191; RV64I-NEXT: zext.b a0, a0192; RV64I-NEXT: addi a2, a2, -256193; RV64I-NEXT: slli a1, a1, 8194; RV64I-NEXT: and a1, a1, a2195; RV64I-NEXT: or a0, a1, a0196; RV64I-NEXT: ret197;198; RV64ZBKB-LABEL: packh_i64:199; RV64ZBKB: # %bb.0:200; RV64ZBKB-NEXT: lui a2, 16201; RV64ZBKB-NEXT: zext.b a0, a0202; RV64ZBKB-NEXT: addi a2, a2, -256203; RV64ZBKB-NEXT: slli a1, a1, 8204; RV64ZBKB-NEXT: and a1, a1, a2205; RV64ZBKB-NEXT: or a0, a1, a0206; RV64ZBKB-NEXT: ret207 %and = and i64 %a, 255208 %and1 = shl i64 %b, 8209 %shl = and i64 %and1, 65280210 %or = or i64 %shl, %and211 ret i64 %or212}213 214define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {215; RV64I-LABEL: packh_i64_2:216; RV64I: # %bb.0:217; RV64I-NEXT: zext.b a0, a0218; RV64I-NEXT: zext.b a1, a1219; RV64I-NEXT: slli a1, a1, 8220; RV64I-NEXT: or a0, a1, a0221; RV64I-NEXT: ret222;223; RV64ZBKB-LABEL: packh_i64_2:224; RV64ZBKB: # %bb.0:225; RV64ZBKB-NEXT: packh a0, a0, a1226; RV64ZBKB-NEXT: ret227 %and = and i64 %a, 255228 %and1 = and i64 %b, 255229 %shl = shl i64 %and1, 8230 %or = or i64 %shl, %and231 ret i64 %or232}233 234define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {235; RV64I-LABEL: packh_i16:236; RV64I: # %bb.0:237; RV64I-NEXT: slli a1, a1, 8238; RV64I-NEXT: or a0, a1, a0239; RV64I-NEXT: ret240;241; RV64ZBKB-LABEL: packh_i16:242; RV64ZBKB: # %bb.0:243; RV64ZBKB-NEXT: packh a0, a0, a1244; RV64ZBKB-NEXT: ret245 %zext = zext i8 %a to i16246 %zext1 = zext i8 %b to i16247 %shl = shl i16 %zext1, 8248 %or = or i16 %shl, %zext249 ret i16 %or250}251 252define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {253; RV64I-LABEL: packh_i16_2:254; RV64I: # %bb.0:255; RV64I-NEXT: add a0, a1, a0256; RV64I-NEXT: zext.b a0, a0257; RV64I-NEXT: slli a0, a0, 8258; RV64I-NEXT: or a0, a0, a2259; RV64I-NEXT: ret260;261; RV64ZBKB-LABEL: packh_i16_2:262; RV64ZBKB: # %bb.0:263; RV64ZBKB-NEXT: add a0, a1, a0264; RV64ZBKB-NEXT: packh a0, a2, a0265; RV64ZBKB-NEXT: ret266 %4 = add i8 %1, %0267 %5 = zext i8 %4 to i16268 %6 = shl i16 %5, 8269 %7 = zext i8 %2 to i16270 %8 = or i16 %6, %7271 ret i16 %8272}273 274define void @packh_i16_3(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, ptr %p) {275; RV64I-LABEL: packh_i16_3:276; RV64I: # %bb.0:277; RV64I-NEXT: add a0, a1, a0278; RV64I-NEXT: zext.b a0, a0279; RV64I-NEXT: slli a0, a0, 8280; RV64I-NEXT: or a0, a0, a2281; RV64I-NEXT: sh a0, 0(a3)282; RV64I-NEXT: ret283;284; RV64ZBKB-LABEL: packh_i16_3:285; RV64ZBKB: # %bb.0:286; RV64ZBKB-NEXT: add a0, a1, a0287; RV64ZBKB-NEXT: packh a0, a2, a0288; RV64ZBKB-NEXT: sh a0, 0(a3)289; RV64ZBKB-NEXT: ret290 %4 = add i8 %1, %0291 %5 = zext i8 %4 to i16292 %6 = shl i16 %5, 8293 %7 = zext i8 %2 to i16294 %8 = or i16 %6, %7295 store i16 %8, ptr %p296 ret void297}298 299define i64 @pack_i64_allWUsers(i32 signext %0, i32 signext %1, i32 signext %2) {300; RV64I-LABEL: pack_i64_allWUsers:301; RV64I: # %bb.0:302; RV64I-NEXT: add a0, a1, a0303; RV64I-NEXT: slli a2, a2, 32304; RV64I-NEXT: slli a0, a0, 32305; RV64I-NEXT: srli a0, a0, 32306; RV64I-NEXT: slli a0, a0, 32307; RV64I-NEXT: srli a2, a2, 32308; RV64I-NEXT: or a0, a0, a2309; RV64I-NEXT: ret310;311; RV64ZBKB-LABEL: pack_i64_allWUsers:312; RV64ZBKB: # %bb.0:313; RV64ZBKB-NEXT: add a0, a1, a0314; RV64ZBKB-NEXT: slli a0, a0, 32315; RV64ZBKB-NEXT: srli a0, a0, 32316; RV64ZBKB-NEXT: pack a0, a2, a0317; RV64ZBKB-NEXT: ret318 %4 = add i32 %1, %0319 %5 = zext i32 %4 to i64320 %6 = shl i64 %5, 32321 %7 = zext i32 %2 to i64322 %8 = or i64 %6, %7323 ret i64 %8324}325 326define signext i32 @pack_i32_allWUsers(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2) {327; RV64I-LABEL: pack_i32_allWUsers:328; RV64I: # %bb.0:329; RV64I-NEXT: add a0, a1, a0330; RV64I-NEXT: slli a0, a0, 48331; RV64I-NEXT: srli a0, a0, 48332; RV64I-NEXT: slli a0, a0, 16333; RV64I-NEXT: or a0, a0, a2334; RV64I-NEXT: sext.w a0, a0335; RV64I-NEXT: ret336;337; RV64ZBKB-LABEL: pack_i32_allWUsers:338; RV64ZBKB: # %bb.0:339; RV64ZBKB-NEXT: add a0, a1, a0340; RV64ZBKB-NEXT: zext.h a0, a0341; RV64ZBKB-NEXT: packw a0, a2, a0342; RV64ZBKB-NEXT: ret343 %4 = add i16 %1, %0344 %5 = zext i16 %4 to i32345 %6 = shl i32 %5, 16346 %7 = zext i16 %2 to i32347 %8 = or i32 %6, %7348 ret i32 %8349}350 351define i64 @pack_i64_imm() {352; RV64I-LABEL: pack_i64_imm:353; RV64I: # %bb.0:354; RV64I-NEXT: lui a0, 65793355; RV64I-NEXT: slli a0, a0, 4356; RV64I-NEXT: addi a0, a0, 257357; RV64I-NEXT: slli a0, a0, 16358; RV64I-NEXT: addi a0, a0, 257359; RV64I-NEXT: slli a0, a0, 12360; RV64I-NEXT: addi a0, a0, 16361; RV64I-NEXT: ret362;363; RV64ZBKB-LABEL: pack_i64_imm:364; RV64ZBKB: # %bb.0:365; RV64ZBKB-NEXT: lui a0, 65793366; RV64ZBKB-NEXT: addi a0, a0, 16367; RV64ZBKB-NEXT: pack a0, a0, a0368; RV64ZBKB-NEXT: ret369 ret i64 1157442765409226768 ; 0x0101010101010101370}371 372define i32 @zexth_i32(i32 %a) nounwind {373; RV64I-LABEL: zexth_i32:374; RV64I: # %bb.0:375; RV64I-NEXT: slli a0, a0, 48376; RV64I-NEXT: srli a0, a0, 48377; RV64I-NEXT: ret378;379; RV64ZBKB-LABEL: zexth_i32:380; RV64ZBKB: # %bb.0:381; RV64ZBKB-NEXT: zext.h a0, a0382; RV64ZBKB-NEXT: ret383 %and = and i32 %a, 65535384 ret i32 %and385}386 387define i64 @zexth_i64(i64 %a) nounwind {388; RV64I-LABEL: zexth_i64:389; RV64I: # %bb.0:390; RV64I-NEXT: slli a0, a0, 48391; RV64I-NEXT: srli a0, a0, 48392; RV64I-NEXT: ret393;394; RV64ZBKB-LABEL: zexth_i64:395; RV64ZBKB: # %bb.0:396; RV64ZBKB-NEXT: zext.h a0, a0397; RV64ZBKB-NEXT: ret398 %and = and i64 %a, 65535399 ret i64 %and400}401 402define i32 @zext_i16_to_i32(i16 %a) nounwind {403; RV64I-LABEL: zext_i16_to_i32:404; RV64I: # %bb.0:405; RV64I-NEXT: slli a0, a0, 48406; RV64I-NEXT: srli a0, a0, 48407; RV64I-NEXT: ret408;409; RV64ZBKB-LABEL: zext_i16_to_i32:410; RV64ZBKB: # %bb.0:411; RV64ZBKB-NEXT: zext.h a0, a0412; RV64ZBKB-NEXT: ret413 %1 = zext i16 %a to i32414 ret i32 %1415}416 417define i64 @zext_i16_to_i64(i16 %a) nounwind {418; RV64I-LABEL: zext_i16_to_i64:419; RV64I: # %bb.0:420; RV64I-NEXT: slli a0, a0, 48421; RV64I-NEXT: srli a0, a0, 48422; RV64I-NEXT: ret423;424; RV64ZBKB-LABEL: zext_i16_to_i64:425; RV64ZBKB: # %bb.0:426; RV64ZBKB-NEXT: zext.h a0, a0427; RV64ZBKB-NEXT: ret428 %1 = zext i16 %a to i64429 ret i64 %1430}431 432; This creates a i16->i32 G_ZEXT that we need to be able to select433define i32 @zext_i16_i32_2(i1 %z, ptr %x, i32 %y) {434; RV64I-LABEL: zext_i16_i32_2:435; RV64I: # %bb.0:436; RV64I-NEXT: andi a3, a0, 1437; RV64I-NEXT: bnez a3, .LBB20_2438; RV64I-NEXT: # %bb.1:439; RV64I-NEXT: mv a0, a2440; RV64I-NEXT: ret441; RV64I-NEXT: .LBB20_2:442; RV64I-NEXT: lh a0, 0(a1)443; RV64I-NEXT: slli a0, a0, 48444; RV64I-NEXT: srli a0, a0, 48445; RV64I-NEXT: ret446;447; RV64ZBKB-LABEL: zext_i16_i32_2:448; RV64ZBKB: # %bb.0:449; RV64ZBKB-NEXT: andi a3, a0, 1450; RV64ZBKB-NEXT: bnez a3, .LBB20_2451; RV64ZBKB-NEXT: # %bb.1:452; RV64ZBKB-NEXT: mv a0, a2453; RV64ZBKB-NEXT: ret454; RV64ZBKB-NEXT: .LBB20_2:455; RV64ZBKB-NEXT: lh a0, 0(a1)456; RV64ZBKB-NEXT: zext.h a0, a0457; RV64ZBKB-NEXT: ret458 %w = load i16, ptr %x459 %a = freeze i16 %w460 %b = zext i16 %a to i32461 %c = select i1 %z, i32 %b, i32 %y462 ret i32 %c463}464 465; This creates a i16->i32 G_SEXT that we need to be able to select466define i32 @sext_i16_i32(i1 %z, ptr %x, i32 %y) {467; RV64I-LABEL: sext_i16_i32:468; RV64I: # %bb.0:469; RV64I-NEXT: andi a3, a0, 1470; RV64I-NEXT: bnez a3, .LBB21_2471; RV64I-NEXT: # %bb.1:472; RV64I-NEXT: mv a0, a2473; RV64I-NEXT: ret474; RV64I-NEXT: .LBB21_2:475; RV64I-NEXT: lh a0, 0(a1)476; RV64I-NEXT: slli a0, a0, 48477; RV64I-NEXT: srai a0, a0, 48478; RV64I-NEXT: ret479;480; RV64ZBKB-LABEL: sext_i16_i32:481; RV64ZBKB: # %bb.0:482; RV64ZBKB-NEXT: andi a3, a0, 1483; RV64ZBKB-NEXT: bnez a3, .LBB21_2484; RV64ZBKB-NEXT: # %bb.1:485; RV64ZBKB-NEXT: mv a0, a2486; RV64ZBKB-NEXT: ret487; RV64ZBKB-NEXT: .LBB21_2:488; RV64ZBKB-NEXT: lh a0, 0(a1)489; RV64ZBKB-NEXT: slli a0, a0, 48490; RV64ZBKB-NEXT: srai a0, a0, 48491; RV64ZBKB-NEXT: ret492 %w = load i16, ptr %x493 %a = freeze i16 %w494 %b = sext i16 %a to i32495 %c = select i1 %z, i32 %b, i32 %y496 ret i32 %c497}498