1125 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \3; RUN: -verify-machineinstrs -target-abi=ilp32d -global-isel | FileCheck %s4; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \5; RUN: -verify-machineinstrs -target-abi=ilp32d -global-isel | FileCheck %s6; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \7; RUN: -verify-machineinstrs -target-abi=lp64d -global-isel | FileCheck %s8; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfhmin,+zvfh \9; RUN: -verify-machineinstrs -target-abi=ilp32d -global-isel | FileCheck %s10; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfhmin,+zvfh \11; RUN: -verify-machineinstrs -target-abi=lp64d -global-isel | FileCheck %s12 13define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {14; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: fsrmi a1, 017; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma18; CHECK-NEXT: vfadd.vv v8, v8, v919; CHECK-NEXT: fsrm a120; CHECK-NEXT: ret21entry:22 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(23 <vscale x 1 x half> poison,24 <vscale x 1 x half> %0,25 <vscale x 1 x half> %1,26 iXLen 0, iXLen %2)27 28 ret <vscale x 1 x half> %a29}30 31define <vscale x 1 x half> @intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {32; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: fsrmi a1, 035; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu36; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t37; CHECK-NEXT: fsrm a138; CHECK-NEXT: ret39entry:40 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16(41 <vscale x 1 x half> %0,42 <vscale x 1 x half> %1,43 <vscale x 1 x half> %2,44 <vscale x 1 x i1> %3,45 iXLen 0, iXLen %4, iXLen 1)46 47 ret <vscale x 1 x half> %a48}49 50define <vscale x 2 x half> @intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {51; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16:52; CHECK: # %bb.0: # %entry53; CHECK-NEXT: fsrmi a1, 054; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma55; CHECK-NEXT: vfadd.vv v8, v8, v956; CHECK-NEXT: fsrm a157; CHECK-NEXT: ret58entry:59 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.nxv2f16(60 <vscale x 2 x half> poison,61 <vscale x 2 x half> %0,62 <vscale x 2 x half> %1,63 iXLen 0, iXLen %2)64 65 ret <vscale x 2 x half> %a66}67 68define <vscale x 2 x half> @intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {69; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: fsrmi a1, 072; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu73; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t74; CHECK-NEXT: fsrm a175; CHECK-NEXT: ret76entry:77 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16(78 <vscale x 2 x half> %0,79 <vscale x 2 x half> %1,80 <vscale x 2 x half> %2,81 <vscale x 2 x i1> %3,82 iXLen 0, iXLen %4, iXLen 1)83 84 ret <vscale x 2 x half> %a85}86 87define <vscale x 4 x half> @intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {88; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: fsrmi a1, 091; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma92; CHECK-NEXT: vfadd.vv v8, v8, v993; CHECK-NEXT: fsrm a194; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.nxv4f16(97 <vscale x 4 x half> poison,98 <vscale x 4 x half> %0,99 <vscale x 4 x half> %1,100 iXLen 0, iXLen %2)101 102 ret <vscale x 4 x half> %a103}104 105define <vscale x 4 x half> @intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {106; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:107; CHECK: # %bb.0: # %entry108; CHECK-NEXT: fsrmi a1, 0109; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu110; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t111; CHECK-NEXT: fsrm a1112; CHECK-NEXT: ret113entry:114 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16(115 <vscale x 4 x half> %0,116 <vscale x 4 x half> %1,117 <vscale x 4 x half> %2,118 <vscale x 4 x i1> %3,119 iXLen 0, iXLen %4, iXLen 1)120 121 ret <vscale x 4 x half> %a122}123 124define <vscale x 8 x half> @intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {125; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16:126; CHECK: # %bb.0: # %entry127; CHECK-NEXT: fsrmi a1, 0128; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma129; CHECK-NEXT: vfadd.vv v8, v8, v10130; CHECK-NEXT: fsrm a1131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.nxv8f16(134 <vscale x 8 x half> poison,135 <vscale x 8 x half> %0,136 <vscale x 8 x half> %1,137 iXLen 0, iXLen %2)138 139 ret <vscale x 8 x half> %a140}141 142define <vscale x 8 x half> @intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {143; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:144; CHECK: # %bb.0: # %entry145; CHECK-NEXT: fsrmi a1, 0146; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu147; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t148; CHECK-NEXT: fsrm a1149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16(152 <vscale x 8 x half> %0,153 <vscale x 8 x half> %1,154 <vscale x 8 x half> %2,155 <vscale x 8 x i1> %3,156 iXLen 0, iXLen %4, iXLen 1)157 158 ret <vscale x 8 x half> %a159}160 161define <vscale x 16 x half> @intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {162; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16:163; CHECK: # %bb.0: # %entry164; CHECK-NEXT: fsrmi a1, 0165; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma166; CHECK-NEXT: vfadd.vv v8, v8, v12167; CHECK-NEXT: fsrm a1168; CHECK-NEXT: ret169entry:170 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.nxv16f16(171 <vscale x 16 x half> poison,172 <vscale x 16 x half> %0,173 <vscale x 16 x half> %1,174 iXLen 0, iXLen %2)175 176 ret <vscale x 16 x half> %a177}178 179define <vscale x 16 x half> @intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {180; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:181; CHECK: # %bb.0: # %entry182; CHECK-NEXT: fsrmi a1, 0183; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu184; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t185; CHECK-NEXT: fsrm a1186; CHECK-NEXT: ret187entry:188 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16(189 <vscale x 16 x half> %0,190 <vscale x 16 x half> %1,191 <vscale x 16 x half> %2,192 <vscale x 16 x i1> %3,193 iXLen 0, iXLen %4, iXLen 1)194 195 ret <vscale x 16 x half> %a196}197 198define <vscale x 32 x half> @intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, iXLen %2) nounwind {199; CHECK-LABEL: intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16:200; CHECK: # %bb.0: # %entry201; CHECK-NEXT: fsrmi a1, 0202; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma203; CHECK-NEXT: vfadd.vv v8, v8, v16204; CHECK-NEXT: fsrm a1205; CHECK-NEXT: ret206entry:207 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.nxv32f16.nxv32f16(208 <vscale x 32 x half> poison,209 <vscale x 32 x half> %0,210 <vscale x 32 x half> %1,211 iXLen 0, iXLen %2)212 213 ret <vscale x 32 x half> %a214}215 216define <vscale x 32 x half> @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {217; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16:218; CHECK: # %bb.0: # %entry219; CHECK-NEXT: vl8re16.v v24, (a0)220; CHECK-NEXT: fsrmi a0, 0221; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu222; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t223; CHECK-NEXT: fsrm a0224; CHECK-NEXT: ret225entry:226 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.nxv32f16(227 <vscale x 32 x half> %0,228 <vscale x 32 x half> %1,229 <vscale x 32 x half> %2,230 <vscale x 32 x i1> %3,231 iXLen 0, iXLen %4, iXLen 1)232 233 ret <vscale x 32 x half> %a234}235 236define <vscale x 1 x float> @intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {237; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32:238; CHECK: # %bb.0: # %entry239; CHECK-NEXT: fsrmi a1, 0240; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma241; CHECK-NEXT: vfadd.vv v8, v8, v9242; CHECK-NEXT: fsrm a1243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.nxv1f32.nxv1f32(246 <vscale x 1 x float> poison,247 <vscale x 1 x float> %0,248 <vscale x 1 x float> %1,249 iXLen 0, iXLen %2)250 251 ret <vscale x 1 x float> %a252}253 254define <vscale x 1 x float> @intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: fsrmi a1, 0258; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu259; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t260; CHECK-NEXT: fsrm a1261; CHECK-NEXT: ret262entry:263 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32(264 <vscale x 1 x float> %0,265 <vscale x 1 x float> %1,266 <vscale x 1 x float> %2,267 <vscale x 1 x i1> %3,268 iXLen 0, iXLen %4, iXLen 1)269 270 ret <vscale x 1 x float> %a271}272 273define <vscale x 2 x float> @intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {274; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32:275; CHECK: # %bb.0: # %entry276; CHECK-NEXT: fsrmi a1, 0277; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma278; CHECK-NEXT: vfadd.vv v8, v8, v9279; CHECK-NEXT: fsrm a1280; CHECK-NEXT: ret281entry:282 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.nxv2f32(283 <vscale x 2 x float> poison,284 <vscale x 2 x float> %0,285 <vscale x 2 x float> %1,286 iXLen 0, iXLen %2)287 288 ret <vscale x 2 x float> %a289}290 291define <vscale x 2 x float> @intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {292; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:293; CHECK: # %bb.0: # %entry294; CHECK-NEXT: fsrmi a1, 0295; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu296; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t297; CHECK-NEXT: fsrm a1298; CHECK-NEXT: ret299entry:300 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32(301 <vscale x 2 x float> %0,302 <vscale x 2 x float> %1,303 <vscale x 2 x float> %2,304 <vscale x 2 x i1> %3,305 iXLen 0, iXLen %4, iXLen 1)306 307 ret <vscale x 2 x float> %a308}309 310define <vscale x 4 x float> @intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {311; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32:312; CHECK: # %bb.0: # %entry313; CHECK-NEXT: fsrmi a1, 0314; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma315; CHECK-NEXT: vfadd.vv v8, v8, v10316; CHECK-NEXT: fsrm a1317; CHECK-NEXT: ret318entry:319 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.nxv4f32(320 <vscale x 4 x float> poison,321 <vscale x 4 x float> %0,322 <vscale x 4 x float> %1,323 iXLen 0, iXLen %2)324 325 ret <vscale x 4 x float> %a326}327 328define <vscale x 4 x float> @intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {329; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:330; CHECK: # %bb.0: # %entry331; CHECK-NEXT: fsrmi a1, 0332; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu333; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t334; CHECK-NEXT: fsrm a1335; CHECK-NEXT: ret336entry:337 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32(338 <vscale x 4 x float> %0,339 <vscale x 4 x float> %1,340 <vscale x 4 x float> %2,341 <vscale x 4 x i1> %3,342 iXLen 0, iXLen %4, iXLen 1)343 344 ret <vscale x 4 x float> %a345}346 347define <vscale x 8 x float> @intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {348; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32:349; CHECK: # %bb.0: # %entry350; CHECK-NEXT: fsrmi a1, 0351; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma352; CHECK-NEXT: vfadd.vv v8, v8, v12353; CHECK-NEXT: fsrm a1354; CHECK-NEXT: ret355entry:356 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.nxv8f32.nxv8f32(357 <vscale x 8 x float> poison,358 <vscale x 8 x float> %0,359 <vscale x 8 x float> %1,360 iXLen 0, iXLen %2)361 362 ret <vscale x 8 x float> %a363}364 365define <vscale x 8 x float> @intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {366; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:367; CHECK: # %bb.0: # %entry368; CHECK-NEXT: fsrmi a1, 0369; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu370; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t371; CHECK-NEXT: fsrm a1372; CHECK-NEXT: ret373entry:374 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32(375 <vscale x 8 x float> %0,376 <vscale x 8 x float> %1,377 <vscale x 8 x float> %2,378 <vscale x 8 x i1> %3,379 iXLen 0, iXLen %4, iXLen 1)380 381 ret <vscale x 8 x float> %a382}383 384define <vscale x 16 x float> @intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, iXLen %2) nounwind {385; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32:386; CHECK: # %bb.0: # %entry387; CHECK-NEXT: fsrmi a1, 0388; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma389; CHECK-NEXT: vfadd.vv v8, v8, v16390; CHECK-NEXT: fsrm a1391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.nxv16f32.nxv16f32(394 <vscale x 16 x float> poison,395 <vscale x 16 x float> %0,396 <vscale x 16 x float> %1,397 iXLen 0, iXLen %2)398 399 ret <vscale x 16 x float> %a400}401 402define <vscale x 16 x float> @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {403; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32:404; CHECK: # %bb.0: # %entry405; CHECK-NEXT: vl8re32.v v24, (a0)406; CHECK-NEXT: fsrmi a0, 0407; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu408; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t409; CHECK-NEXT: fsrm a0410; CHECK-NEXT: ret411entry:412 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.nxv16f32(413 <vscale x 16 x float> %0,414 <vscale x 16 x float> %1,415 <vscale x 16 x float> %2,416 <vscale x 16 x i1> %3,417 iXLen 0, iXLen %4, iXLen 1)418 419 ret <vscale x 16 x float> %a420}421 422define <vscale x 1 x double> @intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {423; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64:424; CHECK: # %bb.0: # %entry425; CHECK-NEXT: fsrmi a1, 0426; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma427; CHECK-NEXT: vfadd.vv v8, v8, v9428; CHECK-NEXT: fsrm a1429; CHECK-NEXT: ret430entry:431 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(432 <vscale x 1 x double> poison,433 <vscale x 1 x double> %0,434 <vscale x 1 x double> %1,435 iXLen 0, iXLen %2)436 437 ret <vscale x 1 x double> %a438}439 440define <vscale x 1 x double> @intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {441; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:442; CHECK: # %bb.0: # %entry443; CHECK-NEXT: fsrmi a1, 0444; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu445; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t446; CHECK-NEXT: fsrm a1447; CHECK-NEXT: ret448entry:449 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64(450 <vscale x 1 x double> %0,451 <vscale x 1 x double> %1,452 <vscale x 1 x double> %2,453 <vscale x 1 x i1> %3,454 iXLen 0, iXLen %4, iXLen 1)455 456 ret <vscale x 1 x double> %a457}458 459define <vscale x 2 x double> @intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {460; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64:461; CHECK: # %bb.0: # %entry462; CHECK-NEXT: fsrmi a1, 0463; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma464; CHECK-NEXT: vfadd.vv v8, v8, v10465; CHECK-NEXT: fsrm a1466; CHECK-NEXT: ret467entry:468 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.nxv2f64.nxv2f64(469 <vscale x 2 x double> poison,470 <vscale x 2 x double> %0,471 <vscale x 2 x double> %1,472 iXLen 0, iXLen %2)473 474 ret <vscale x 2 x double> %a475}476 477define <vscale x 2 x double> @intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {478; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:479; CHECK: # %bb.0: # %entry480; CHECK-NEXT: fsrmi a1, 0481; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu482; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t483; CHECK-NEXT: fsrm a1484; CHECK-NEXT: ret485entry:486 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64(487 <vscale x 2 x double> %0,488 <vscale x 2 x double> %1,489 <vscale x 2 x double> %2,490 <vscale x 2 x i1> %3,491 iXLen 0, iXLen %4, iXLen 1)492 493 ret <vscale x 2 x double> %a494}495 496define <vscale x 4 x double> @intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {497; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64:498; CHECK: # %bb.0: # %entry499; CHECK-NEXT: fsrmi a1, 0500; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma501; CHECK-NEXT: vfadd.vv v8, v8, v12502; CHECK-NEXT: fsrm a1503; CHECK-NEXT: ret504entry:505 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.nxv4f64(506 <vscale x 4 x double> poison,507 <vscale x 4 x double> %0,508 <vscale x 4 x double> %1,509 iXLen 0, iXLen %2)510 511 ret <vscale x 4 x double> %a512}513 514define <vscale x 4 x double> @intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {515; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:516; CHECK: # %bb.0: # %entry517; CHECK-NEXT: fsrmi a1, 0518; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu519; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t520; CHECK-NEXT: fsrm a1521; CHECK-NEXT: ret522entry:523 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64(524 <vscale x 4 x double> %0,525 <vscale x 4 x double> %1,526 <vscale x 4 x double> %2,527 <vscale x 4 x i1> %3,528 iXLen 0, iXLen %4, iXLen 1)529 530 ret <vscale x 4 x double> %a531}532 533define <vscale x 8 x double> @intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, iXLen %2) nounwind {534; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64:535; CHECK: # %bb.0: # %entry536; CHECK-NEXT: fsrmi a1, 0537; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma538; CHECK-NEXT: vfadd.vv v8, v8, v16539; CHECK-NEXT: fsrm a1540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.nxv8f64.nxv8f64(543 <vscale x 8 x double> poison,544 <vscale x 8 x double> %0,545 <vscale x 8 x double> %1,546 iXLen 0, iXLen %2)547 548 ret <vscale x 8 x double> %a549}550 551define <vscale x 8 x double> @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vl8re64.v v24, (a0)555; CHECK-NEXT: fsrmi a0, 0556; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu557; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t558; CHECK-NEXT: fsrm a0559; CHECK-NEXT: ret560entry:561 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.nxv8f64(562 <vscale x 8 x double> %0,563 <vscale x 8 x double> %1,564 <vscale x 8 x double> %2,565 <vscale x 8 x i1> %3,566 iXLen 0, iXLen %4, iXLen 1)567 568 ret <vscale x 8 x double> %a569}570 571define <vscale x 1 x half> @intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, iXLen %2) nounwind {572; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16:573; CHECK: # %bb.0: # %entry574; CHECK-NEXT: fsrmi a1, 0575; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma576; CHECK-NEXT: vfadd.vf v8, v8, fa0577; CHECK-NEXT: fsrm a1578; CHECK-NEXT: ret579entry:580 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.f16(581 <vscale x 1 x half> poison,582 <vscale x 1 x half> %0,583 half %1,584 iXLen 0, iXLen %2)585 586 ret <vscale x 1 x half> %a587}588 589define <vscale x 1 x half> @intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {590; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16:591; CHECK: # %bb.0: # %entry592; CHECK-NEXT: fsrmi a1, 0593; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu594; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t595; CHECK-NEXT: fsrm a1596; CHECK-NEXT: ret597entry:598 %a = call <vscale x 1 x half> @llvm.riscv.vfadd.mask.nxv1f16.f16(599 <vscale x 1 x half> %0,600 <vscale x 1 x half> %1,601 half %2,602 <vscale x 1 x i1> %3,603 iXLen 0, iXLen %4, iXLen 1)604 605 ret <vscale x 1 x half> %a606}607 608define <vscale x 2 x half> @intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, iXLen %2) nounwind {609; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16:610; CHECK: # %bb.0: # %entry611; CHECK-NEXT: fsrmi a1, 0612; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma613; CHECK-NEXT: vfadd.vf v8, v8, fa0614; CHECK-NEXT: fsrm a1615; CHECK-NEXT: ret616entry:617 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.nxv2f16.f16(618 <vscale x 2 x half> poison,619 <vscale x 2 x half> %0,620 half %1,621 iXLen 0, iXLen %2)622 623 ret <vscale x 2 x half> %a624}625 626define <vscale x 2 x half> @intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {627; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16:628; CHECK: # %bb.0: # %entry629; CHECK-NEXT: fsrmi a1, 0630; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu631; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t632; CHECK-NEXT: fsrm a1633; CHECK-NEXT: ret634entry:635 %a = call <vscale x 2 x half> @llvm.riscv.vfadd.mask.nxv2f16.f16(636 <vscale x 2 x half> %0,637 <vscale x 2 x half> %1,638 half %2,639 <vscale x 2 x i1> %3,640 iXLen 0, iXLen %4, iXLen 1)641 642 ret <vscale x 2 x half> %a643}644 645define <vscale x 4 x half> @intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, iXLen %2) nounwind {646; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16:647; CHECK: # %bb.0: # %entry648; CHECK-NEXT: fsrmi a1, 0649; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma650; CHECK-NEXT: vfadd.vf v8, v8, fa0651; CHECK-NEXT: fsrm a1652; CHECK-NEXT: ret653entry:654 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.nxv4f16.f16(655 <vscale x 4 x half> poison,656 <vscale x 4 x half> %0,657 half %1,658 iXLen 0, iXLen %2)659 660 ret <vscale x 4 x half> %a661}662 663define <vscale x 4 x half> @intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {664; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16:665; CHECK: # %bb.0: # %entry666; CHECK-NEXT: fsrmi a1, 0667; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu668; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t669; CHECK-NEXT: fsrm a1670; CHECK-NEXT: ret671entry:672 %a = call <vscale x 4 x half> @llvm.riscv.vfadd.mask.nxv4f16.f16(673 <vscale x 4 x half> %0,674 <vscale x 4 x half> %1,675 half %2,676 <vscale x 4 x i1> %3,677 iXLen 0, iXLen %4, iXLen 1)678 679 ret <vscale x 4 x half> %a680}681 682define <vscale x 8 x half> @intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, iXLen %2) nounwind {683; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16:684; CHECK: # %bb.0: # %entry685; CHECK-NEXT: fsrmi a1, 0686; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma687; CHECK-NEXT: vfadd.vf v8, v8, fa0688; CHECK-NEXT: fsrm a1689; CHECK-NEXT: ret690entry:691 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.nxv8f16.f16(692 <vscale x 8 x half> poison,693 <vscale x 8 x half> %0,694 half %1,695 iXLen 0, iXLen %2)696 697 ret <vscale x 8 x half> %a698}699 700define <vscale x 8 x half> @intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {701; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: fsrmi a1, 0704; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu705; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t706; CHECK-NEXT: fsrm a1707; CHECK-NEXT: ret708entry:709 %a = call <vscale x 8 x half> @llvm.riscv.vfadd.mask.nxv8f16.f16(710 <vscale x 8 x half> %0,711 <vscale x 8 x half> %1,712 half %2,713 <vscale x 8 x i1> %3,714 iXLen 0, iXLen %4, iXLen 1)715 716 ret <vscale x 8 x half> %a717}718 719define <vscale x 16 x half> @intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, iXLen %2) nounwind {720; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16:721; CHECK: # %bb.0: # %entry722; CHECK-NEXT: fsrmi a1, 0723; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma724; CHECK-NEXT: vfadd.vf v8, v8, fa0725; CHECK-NEXT: fsrm a1726; CHECK-NEXT: ret727entry:728 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.nxv16f16.f16(729 <vscale x 16 x half> poison,730 <vscale x 16 x half> %0,731 half %1,732 iXLen 0, iXLen %2)733 734 ret <vscale x 16 x half> %a735}736 737define <vscale x 16 x half> @intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {738; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16:739; CHECK: # %bb.0: # %entry740; CHECK-NEXT: fsrmi a1, 0741; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu742; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t743; CHECK-NEXT: fsrm a1744; CHECK-NEXT: ret745entry:746 %a = call <vscale x 16 x half> @llvm.riscv.vfadd.mask.nxv16f16.f16(747 <vscale x 16 x half> %0,748 <vscale x 16 x half> %1,749 half %2,750 <vscale x 16 x i1> %3,751 iXLen 0, iXLen %4, iXLen 1)752 753 ret <vscale x 16 x half> %a754}755 756define <vscale x 32 x half> @intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, iXLen %2) nounwind {757; CHECK-LABEL: intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16:758; CHECK: # %bb.0: # %entry759; CHECK-NEXT: fsrmi a1, 0760; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma761; CHECK-NEXT: vfadd.vf v8, v8, fa0762; CHECK-NEXT: fsrm a1763; CHECK-NEXT: ret764entry:765 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.nxv32f16.f16(766 <vscale x 32 x half> poison,767 <vscale x 32 x half> %0,768 half %1,769 iXLen 0, iXLen %2)770 771 ret <vscale x 32 x half> %a772}773 774define <vscale x 32 x half> @intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {775; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16:776; CHECK: # %bb.0: # %entry777; CHECK-NEXT: fsrmi a1, 0778; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu779; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t780; CHECK-NEXT: fsrm a1781; CHECK-NEXT: ret782entry:783 %a = call <vscale x 32 x half> @llvm.riscv.vfadd.mask.nxv32f16.f16(784 <vscale x 32 x half> %0,785 <vscale x 32 x half> %1,786 half %2,787 <vscale x 32 x i1> %3,788 iXLen 0, iXLen %4, iXLen 1)789 790 ret <vscale x 32 x half> %a791}792 793define <vscale x 1 x float> @intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind {794; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32:795; CHECK: # %bb.0: # %entry796; CHECK-NEXT: fsrmi a1, 0797; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma798; CHECK-NEXT: vfadd.vf v8, v8, fa0799; CHECK-NEXT: fsrm a1800; CHECK-NEXT: ret801entry:802 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.nxv1f32.f32(803 <vscale x 1 x float> poison,804 <vscale x 1 x float> %0,805 float %1,806 iXLen 0, iXLen %2)807 808 ret <vscale x 1 x float> %a809}810 811define <vscale x 1 x float> @intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {812; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32:813; CHECK: # %bb.0: # %entry814; CHECK-NEXT: fsrmi a1, 0815; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu816; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t817; CHECK-NEXT: fsrm a1818; CHECK-NEXT: ret819entry:820 %a = call <vscale x 1 x float> @llvm.riscv.vfadd.mask.nxv1f32.f32(821 <vscale x 1 x float> %0,822 <vscale x 1 x float> %1,823 float %2,824 <vscale x 1 x i1> %3,825 iXLen 0, iXLen %4, iXLen 1)826 827 ret <vscale x 1 x float> %a828}829 830define <vscale x 2 x float> @intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, iXLen %2) nounwind {831; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32:832; CHECK: # %bb.0: # %entry833; CHECK-NEXT: fsrmi a1, 0834; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma835; CHECK-NEXT: vfadd.vf v8, v8, fa0836; CHECK-NEXT: fsrm a1837; CHECK-NEXT: ret838entry:839 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.nxv2f32.f32(840 <vscale x 2 x float> poison,841 <vscale x 2 x float> %0,842 float %1,843 iXLen 0, iXLen %2)844 845 ret <vscale x 2 x float> %a846}847 848define <vscale x 2 x float> @intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {849; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32:850; CHECK: # %bb.0: # %entry851; CHECK-NEXT: fsrmi a1, 0852; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu853; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t854; CHECK-NEXT: fsrm a1855; CHECK-NEXT: ret856entry:857 %a = call <vscale x 2 x float> @llvm.riscv.vfadd.mask.nxv2f32.f32(858 <vscale x 2 x float> %0,859 <vscale x 2 x float> %1,860 float %2,861 <vscale x 2 x i1> %3,862 iXLen 0, iXLen %4, iXLen 1)863 864 ret <vscale x 2 x float> %a865}866 867define <vscale x 4 x float> @intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, iXLen %2) nounwind {868; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32:869; CHECK: # %bb.0: # %entry870; CHECK-NEXT: fsrmi a1, 0871; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma872; CHECK-NEXT: vfadd.vf v8, v8, fa0873; CHECK-NEXT: fsrm a1874; CHECK-NEXT: ret875entry:876 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.nxv4f32.f32(877 <vscale x 4 x float> poison,878 <vscale x 4 x float> %0,879 float %1,880 iXLen 0, iXLen %2)881 882 ret <vscale x 4 x float> %a883}884 885define <vscale x 4 x float> @intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {886; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32:887; CHECK: # %bb.0: # %entry888; CHECK-NEXT: fsrmi a1, 0889; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu890; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t891; CHECK-NEXT: fsrm a1892; CHECK-NEXT: ret893entry:894 %a = call <vscale x 4 x float> @llvm.riscv.vfadd.mask.nxv4f32.f32(895 <vscale x 4 x float> %0,896 <vscale x 4 x float> %1,897 float %2,898 <vscale x 4 x i1> %3,899 iXLen 0, iXLen %4, iXLen 1)900 901 ret <vscale x 4 x float> %a902}903 904define <vscale x 8 x float> @intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, iXLen %2) nounwind {905; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32:906; CHECK: # %bb.0: # %entry907; CHECK-NEXT: fsrmi a1, 0908; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma909; CHECK-NEXT: vfadd.vf v8, v8, fa0910; CHECK-NEXT: fsrm a1911; CHECK-NEXT: ret912entry:913 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.nxv8f32.f32(914 <vscale x 8 x float> poison,915 <vscale x 8 x float> %0,916 float %1,917 iXLen 0, iXLen %2)918 919 ret <vscale x 8 x float> %a920}921 922define <vscale x 8 x float> @intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {923; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32:924; CHECK: # %bb.0: # %entry925; CHECK-NEXT: fsrmi a1, 0926; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu927; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t928; CHECK-NEXT: fsrm a1929; CHECK-NEXT: ret930entry:931 %a = call <vscale x 8 x float> @llvm.riscv.vfadd.mask.nxv8f32.f32(932 <vscale x 8 x float> %0,933 <vscale x 8 x float> %1,934 float %2,935 <vscale x 8 x i1> %3,936 iXLen 0, iXLen %4, iXLen 1)937 938 ret <vscale x 8 x float> %a939}940 941define <vscale x 16 x float> @intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, iXLen %2) nounwind {942; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32:943; CHECK: # %bb.0: # %entry944; CHECK-NEXT: fsrmi a1, 0945; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma946; CHECK-NEXT: vfadd.vf v8, v8, fa0947; CHECK-NEXT: fsrm a1948; CHECK-NEXT: ret949entry:950 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.nxv16f32.f32(951 <vscale x 16 x float> poison,952 <vscale x 16 x float> %0,953 float %1,954 iXLen 0, iXLen %2)955 956 ret <vscale x 16 x float> %a957}958 959define <vscale x 16 x float> @intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {960; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32:961; CHECK: # %bb.0: # %entry962; CHECK-NEXT: fsrmi a1, 0963; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu964; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t965; CHECK-NEXT: fsrm a1966; CHECK-NEXT: ret967entry:968 %a = call <vscale x 16 x float> @llvm.riscv.vfadd.mask.nxv16f32.f32(969 <vscale x 16 x float> %0,970 <vscale x 16 x float> %1,971 float %2,972 <vscale x 16 x i1> %3,973 iXLen 0, iXLen %4, iXLen 1)974 975 ret <vscale x 16 x float> %a976}977 978define <vscale x 1 x double> @intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, iXLen %2) nounwind {979; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64:980; CHECK: # %bb.0: # %entry981; CHECK-NEXT: fsrmi a1, 0982; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma983; CHECK-NEXT: vfadd.vf v8, v8, fa0984; CHECK-NEXT: fsrm a1985; CHECK-NEXT: ret986entry:987 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.f64(988 <vscale x 1 x double> poison,989 <vscale x 1 x double> %0,990 double %1,991 iXLen 0, iXLen %2)992 993 ret <vscale x 1 x double> %a994}995 996define <vscale x 1 x double> @intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {997; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64:998; CHECK: # %bb.0: # %entry999; CHECK-NEXT: fsrmi a1, 01000; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu1001; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t1002; CHECK-NEXT: fsrm a11003; CHECK-NEXT: ret1004entry:1005 %a = call <vscale x 1 x double> @llvm.riscv.vfadd.mask.nxv1f64.f64(1006 <vscale x 1 x double> %0,1007 <vscale x 1 x double> %1,1008 double %2,1009 <vscale x 1 x i1> %3,1010 iXLen 0, iXLen %4, iXLen 1)1011 1012 ret <vscale x 1 x double> %a1013}1014 1015define <vscale x 2 x double> @intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, iXLen %2) nounwind {1016; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64:1017; CHECK: # %bb.0: # %entry1018; CHECK-NEXT: fsrmi a1, 01019; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1020; CHECK-NEXT: vfadd.vf v8, v8, fa01021; CHECK-NEXT: fsrm a11022; CHECK-NEXT: ret1023entry:1024 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.nxv2f64.f64(1025 <vscale x 2 x double> poison,1026 <vscale x 2 x double> %0,1027 double %1,1028 iXLen 0, iXLen %2)1029 1030 ret <vscale x 2 x double> %a1031}1032 1033define <vscale x 2 x double> @intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1034; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64:1035; CHECK: # %bb.0: # %entry1036; CHECK-NEXT: fsrmi a1, 01037; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu1038; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t1039; CHECK-NEXT: fsrm a11040; CHECK-NEXT: ret1041entry:1042 %a = call <vscale x 2 x double> @llvm.riscv.vfadd.mask.nxv2f64.f64(1043 <vscale x 2 x double> %0,1044 <vscale x 2 x double> %1,1045 double %2,1046 <vscale x 2 x i1> %3,1047 iXLen 0, iXLen %4, iXLen 1)1048 1049 ret <vscale x 2 x double> %a1050}1051 1052define <vscale x 4 x double> @intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, iXLen %2) nounwind {1053; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64:1054; CHECK: # %bb.0: # %entry1055; CHECK-NEXT: fsrmi a1, 01056; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1057; CHECK-NEXT: vfadd.vf v8, v8, fa01058; CHECK-NEXT: fsrm a11059; CHECK-NEXT: ret1060entry:1061 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.nxv4f64.f64(1062 <vscale x 4 x double> poison,1063 <vscale x 4 x double> %0,1064 double %1,1065 iXLen 0, iXLen %2)1066 1067 ret <vscale x 4 x double> %a1068}1069 1070define <vscale x 4 x double> @intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1071; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64:1072; CHECK: # %bb.0: # %entry1073; CHECK-NEXT: fsrmi a1, 01074; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu1075; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t1076; CHECK-NEXT: fsrm a11077; CHECK-NEXT: ret1078entry:1079 %a = call <vscale x 4 x double> @llvm.riscv.vfadd.mask.nxv4f64.f64(1080 <vscale x 4 x double> %0,1081 <vscale x 4 x double> %1,1082 double %2,1083 <vscale x 4 x i1> %3,1084 iXLen 0, iXLen %4, iXLen 1)1085 1086 ret <vscale x 4 x double> %a1087}1088 1089define <vscale x 8 x double> @intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, iXLen %2) nounwind {1090; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64:1091; CHECK: # %bb.0: # %entry1092; CHECK-NEXT: fsrmi a1, 01093; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1094; CHECK-NEXT: vfadd.vf v8, v8, fa01095; CHECK-NEXT: fsrm a11096; CHECK-NEXT: ret1097entry:1098 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.nxv8f64.f64(1099 <vscale x 8 x double> poison,1100 <vscale x 8 x double> %0,1101 double %1,1102 iXLen 0, iXLen %2)1103 1104 ret <vscale x 8 x double> %a1105}1106 1107define <vscale x 8 x double> @intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1108; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64:1109; CHECK: # %bb.0: # %entry1110; CHECK-NEXT: fsrmi a1, 01111; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu1112; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t1113; CHECK-NEXT: fsrm a11114; CHECK-NEXT: ret1115entry:1116 %a = call <vscale x 8 x double> @llvm.riscv.vfadd.mask.nxv8f64.f64(1117 <vscale x 8 x double> %0,1118 <vscale x 8 x double> %1,1119 double %2,1120 <vscale x 8 x i1> %3,1121 iXLen 0, iXLen %4, iXLen 1)1122 1123 ret <vscale x 8 x double> %a1124}1125