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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN:   -global-isel -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN:   -global-isel -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i32:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT:    vluxei32.v v9, (a0), v812; CHECK-NEXT:    vmv1r.v v8, v913; CHECK-NEXT:    ret14entry:15  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i32(16    <vscale x 1 x i8> poison,17    ptr %0,18    <vscale x 1 x i32> %1,19    iXLen %2)20 21  ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i32(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i32:26; CHECK:       # %bb.0: # %entry27; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu28; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t29; CHECK-NEXT:    ret30entry:31  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i32(32    <vscale x 1 x i8> %0,33    ptr %1,34    <vscale x 1 x i32> %2,35    <vscale x 1 x i1> %3,36    iXLen %4, iXLen 1)37 38  ret <vscale x 1 x i8> %a39}40 41define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i32:43; CHECK:       # %bb.0: # %entry44; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma45; CHECK-NEXT:    vluxei32.v v9, (a0), v846; CHECK-NEXT:    vmv1r.v v8, v947; CHECK-NEXT:    ret48entry:49  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i32(50    <vscale x 2 x i8> poison,51    ptr %0,52    <vscale x 2 x i32> %1,53    iXLen %2)54 55  ret <vscale x 2 x i8> %a56}57 58define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i32(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i32:60; CHECK:       # %bb.0: # %entry61; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu62; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t63; CHECK-NEXT:    ret64entry:65  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i32(66    <vscale x 2 x i8> %0,67    ptr %1,68    <vscale x 2 x i32> %2,69    <vscale x 2 x i1> %3,70    iXLen %4, iXLen 1)71 72  ret <vscale x 2 x i8> %a73}74 75define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i32:77; CHECK:       # %bb.0: # %entry78; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma79; CHECK-NEXT:    vluxei32.v v10, (a0), v880; CHECK-NEXT:    vmv1r.v v8, v1081; CHECK-NEXT:    ret82entry:83  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i32(84    <vscale x 4 x i8> poison,85    ptr %0,86    <vscale x 4 x i32> %1,87    iXLen %2)88 89  ret <vscale x 4 x i8> %a90}91 92define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i32(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i32:94; CHECK:       # %bb.0: # %entry95; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu96; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t97; CHECK-NEXT:    ret98entry:99  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i32(100    <vscale x 4 x i8> %0,101    ptr %1,102    <vscale x 4 x i32> %2,103    <vscale x 4 x i1> %3,104    iXLen %4, iXLen 1)105 106  ret <vscale x 4 x i8> %a107}108 109define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i32:111; CHECK:       # %bb.0: # %entry112; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma113; CHECK-NEXT:    vluxei32.v v12, (a0), v8114; CHECK-NEXT:    vmv.v.v v8, v12115; CHECK-NEXT:    ret116entry:117  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i32(118    <vscale x 8 x i8> poison,119    ptr %0,120    <vscale x 8 x i32> %1,121    iXLen %2)122 123  ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i32(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i32:128; CHECK:       # %bb.0: # %entry129; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu130; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t131; CHECK-NEXT:    ret132entry:133  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i32(134    <vscale x 8 x i8> %0,135    ptr %1,136    <vscale x 8 x i32> %2,137    <vscale x 8 x i1> %3,138    iXLen %4, iXLen 1)139 140  ret <vscale x 8 x i8> %a141}142 143define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i32:145; CHECK:       # %bb.0: # %entry146; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma147; CHECK-NEXT:    vluxei32.v v16, (a0), v8148; CHECK-NEXT:    vmv.v.v v8, v16149; CHECK-NEXT:    ret150entry:151  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i32(152    <vscale x 16 x i8> poison,153    ptr %0,154    <vscale x 16 x i32> %1,155    iXLen %2)156 157  ret <vscale x 16 x i8> %a158}159 160define <vscale x 16 x i8> @intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i32(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i32:162; CHECK:       # %bb.0: # %entry163; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu164; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t165; CHECK-NEXT:    ret166entry:167  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i32(168    <vscale x 16 x i8> %0,169    ptr %1,170    <vscale x 16 x i32> %2,171    <vscale x 16 x i1> %3,172    iXLen %4, iXLen 1)173 174  ret <vscale x 16 x i8> %a175}176 177define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i32:179; CHECK:       # %bb.0: # %entry180; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma181; CHECK-NEXT:    vluxei32.v v9, (a0), v8182; CHECK-NEXT:    vmv1r.v v8, v9183; CHECK-NEXT:    ret184entry:185  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i32(186    <vscale x 1 x i16> poison,187    ptr %0,188    <vscale x 1 x i32> %1,189    iXLen %2)190 191  ret <vscale x 1 x i16> %a192}193 194define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i32(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i32:196; CHECK:       # %bb.0: # %entry197; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu198; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t199; CHECK-NEXT:    ret200entry:201  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i32(202    <vscale x 1 x i16> %0,203    ptr %1,204    <vscale x 1 x i32> %2,205    <vscale x 1 x i1> %3,206    iXLen %4, iXLen 1)207 208  ret <vscale x 1 x i16> %a209}210 211define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i32:213; CHECK:       # %bb.0: # %entry214; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma215; CHECK-NEXT:    vluxei32.v v9, (a0), v8216; CHECK-NEXT:    vmv1r.v v8, v9217; CHECK-NEXT:    ret218entry:219  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i32(220    <vscale x 2 x i16> poison,221    ptr %0,222    <vscale x 2 x i32> %1,223    iXLen %2)224 225  ret <vscale x 2 x i16> %a226}227 228define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i32(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i32:230; CHECK:       # %bb.0: # %entry231; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu232; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t233; CHECK-NEXT:    ret234entry:235  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i32(236    <vscale x 2 x i16> %0,237    ptr %1,238    <vscale x 2 x i32> %2,239    <vscale x 2 x i1> %3,240    iXLen %4, iXLen 1)241 242  ret <vscale x 2 x i16> %a243}244 245define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i32:247; CHECK:       # %bb.0: # %entry248; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma249; CHECK-NEXT:    vluxei32.v v10, (a0), v8250; CHECK-NEXT:    vmv.v.v v8, v10251; CHECK-NEXT:    ret252entry:253  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i32(254    <vscale x 4 x i16> poison,255    ptr %0,256    <vscale x 4 x i32> %1,257    iXLen %2)258 259  ret <vscale x 4 x i16> %a260}261 262define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i32(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {263; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i32:264; CHECK:       # %bb.0: # %entry265; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu266; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t267; CHECK-NEXT:    ret268entry:269  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i32(270    <vscale x 4 x i16> %0,271    ptr %1,272    <vscale x 4 x i32> %2,273    <vscale x 4 x i1> %3,274    iXLen %4, iXLen 1)275 276  ret <vscale x 4 x i16> %a277}278 279define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {280; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i32:281; CHECK:       # %bb.0: # %entry282; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma283; CHECK-NEXT:    vluxei32.v v12, (a0), v8284; CHECK-NEXT:    vmv.v.v v8, v12285; CHECK-NEXT:    ret286entry:287  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i32(288    <vscale x 8 x i16> poison,289    ptr %0,290    <vscale x 8 x i32> %1,291    iXLen %2)292 293  ret <vscale x 8 x i16> %a294}295 296define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i32(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {297; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i32:298; CHECK:       # %bb.0: # %entry299; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu300; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t301; CHECK-NEXT:    ret302entry:303  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i32(304    <vscale x 8 x i16> %0,305    ptr %1,306    <vscale x 8 x i32> %2,307    <vscale x 8 x i1> %3,308    iXLen %4, iXLen 1)309 310  ret <vscale x 8 x i16> %a311}312 313define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {314; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i32:315; CHECK:       # %bb.0: # %entry316; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma317; CHECK-NEXT:    vluxei32.v v16, (a0), v8318; CHECK-NEXT:    vmv.v.v v8, v16319; CHECK-NEXT:    ret320entry:321  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i32(322    <vscale x 16 x i16> poison,323    ptr %0,324    <vscale x 16 x i32> %1,325    iXLen %2)326 327  ret <vscale x 16 x i16> %a328}329 330define <vscale x 16 x i16> @intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i32(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {331; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i32:332; CHECK:       # %bb.0: # %entry333; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu334; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t335; CHECK-NEXT:    ret336entry:337  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i32(338    <vscale x 16 x i16> %0,339    ptr %1,340    <vscale x 16 x i32> %2,341    <vscale x 16 x i1> %3,342    iXLen %4, iXLen 1)343 344  ret <vscale x 16 x i16> %a345}346 347define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {348; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i32:349; CHECK:       # %bb.0: # %entry350; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma351; CHECK-NEXT:    vluxei32.v v8, (a0), v8352; CHECK-NEXT:    ret353entry:354  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i32(355    <vscale x 1 x i32> poison,356    ptr %0,357    <vscale x 1 x i32> %1,358    iXLen %2)359 360  ret <vscale x 1 x i32> %a361}362 363define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {364; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i32:365; CHECK:       # %bb.0: # %entry366; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu367; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t368; CHECK-NEXT:    ret369entry:370  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i32(371    <vscale x 1 x i32> %0,372    ptr %1,373    <vscale x 1 x i32> %2,374    <vscale x 1 x i1> %3,375    iXLen %4, iXLen 1)376 377  ret <vscale x 1 x i32> %a378}379 380define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {381; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i32:382; CHECK:       # %bb.0: # %entry383; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma384; CHECK-NEXT:    vluxei32.v v8, (a0), v8385; CHECK-NEXT:    ret386entry:387  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i32(388    <vscale x 2 x i32> poison,389    ptr %0,390    <vscale x 2 x i32> %1,391    iXLen %2)392 393  ret <vscale x 2 x i32> %a394}395 396define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {397; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i32:398; CHECK:       # %bb.0: # %entry399; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu400; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t401; CHECK-NEXT:    ret402entry:403  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i32(404    <vscale x 2 x i32> %0,405    ptr %1,406    <vscale x 2 x i32> %2,407    <vscale x 2 x i1> %3,408    iXLen %4, iXLen 1)409 410  ret <vscale x 2 x i32> %a411}412 413define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {414; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i32:415; CHECK:       # %bb.0: # %entry416; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma417; CHECK-NEXT:    vluxei32.v v8, (a0), v8418; CHECK-NEXT:    ret419entry:420  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i32(421    <vscale x 4 x i32> poison,422    ptr %0,423    <vscale x 4 x i32> %1,424    iXLen %2)425 426  ret <vscale x 4 x i32> %a427}428 429define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {430; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i32:431; CHECK:       # %bb.0: # %entry432; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu433; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t434; CHECK-NEXT:    ret435entry:436  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i32(437    <vscale x 4 x i32> %0,438    ptr %1,439    <vscale x 4 x i32> %2,440    <vscale x 4 x i1> %3,441    iXLen %4, iXLen 1)442 443  ret <vscale x 4 x i32> %a444}445 446define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {447; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i32:448; CHECK:       # %bb.0: # %entry449; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma450; CHECK-NEXT:    vluxei32.v v8, (a0), v8451; CHECK-NEXT:    ret452entry:453  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i32(454    <vscale x 8 x i32> poison,455    ptr %0,456    <vscale x 8 x i32> %1,457    iXLen %2)458 459  ret <vscale x 8 x i32> %a460}461 462define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {463; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i32:464; CHECK:       # %bb.0: # %entry465; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu466; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t467; CHECK-NEXT:    ret468entry:469  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i32(470    <vscale x 8 x i32> %0,471    ptr %1,472    <vscale x 8 x i32> %2,473    <vscale x 8 x i1> %3,474    iXLen %4, iXLen 1)475 476  ret <vscale x 8 x i32> %a477}478 479define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {480; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i32:481; CHECK:       # %bb.0: # %entry482; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma483; CHECK-NEXT:    vluxei32.v v8, (a0), v8484; CHECK-NEXT:    ret485entry:486  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i32(487    <vscale x 16 x i32> poison,488    ptr %0,489    <vscale x 16 x i32> %1,490    iXLen %2)491 492  ret <vscale x 16 x i32> %a493}494 495define <vscale x 16 x i32> @intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {496; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i32:497; CHECK:       # %bb.0: # %entry498; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu499; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t500; CHECK-NEXT:    ret501entry:502  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i32(503    <vscale x 16 x i32> %0,504    ptr %1,505    <vscale x 16 x i32> %2,506    <vscale x 16 x i1> %3,507    iXLen %4, iXLen 1)508 509  ret <vscale x 16 x i32> %a510}511 512define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {513; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i32:514; CHECK:       # %bb.0: # %entry515; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma516; CHECK-NEXT:    vluxei32.v v9, (a0), v8517; CHECK-NEXT:    vmv.v.v v8, v9518; CHECK-NEXT:    ret519entry:520  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(521    <vscale x 1 x i64> poison,522    ptr %0,523    <vscale x 1 x i32> %1,524    iXLen %2)525 526  ret <vscale x 1 x i64> %a527}528 529define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {530; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i32:531; CHECK:       # %bb.0: # %entry532; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu533; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t534; CHECK-NEXT:    ret535entry:536  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(537    <vscale x 1 x i64> %0,538    ptr %1,539    <vscale x 1 x i32> %2,540    <vscale x 1 x i1> %3,541    iXLen %4, iXLen 1)542 543  ret <vscale x 1 x i64> %a544}545 546define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {547; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i32:548; CHECK:       # %bb.0: # %entry549; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma550; CHECK-NEXT:    vmv1r.v v10, v8551; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma552; CHECK-NEXT:    vluxei32.v v8, (a0), v10553; CHECK-NEXT:    ret554entry:555  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i32(556    <vscale x 2 x i64> poison,557    ptr %0,558    <vscale x 2 x i32> %1,559    iXLen %2)560 561  ret <vscale x 2 x i64> %a562}563 564define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {565; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i32:566; CHECK:       # %bb.0: # %entry567; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu568; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t569; CHECK-NEXT:    ret570entry:571  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i32(572    <vscale x 2 x i64> %0,573    ptr %1,574    <vscale x 2 x i32> %2,575    <vscale x 2 x i1> %3,576    iXLen %4, iXLen 1)577 578  ret <vscale x 2 x i64> %a579}580 581define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {582; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i32:583; CHECK:       # %bb.0: # %entry584; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma585; CHECK-NEXT:    vmv2r.v v12, v8586; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma587; CHECK-NEXT:    vluxei32.v v8, (a0), v12588; CHECK-NEXT:    ret589entry:590  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i32(591    <vscale x 4 x i64> poison,592    ptr %0,593    <vscale x 4 x i32> %1,594    iXLen %2)595 596  ret <vscale x 4 x i64> %a597}598 599define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {600; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i32:601; CHECK:       # %bb.0: # %entry602; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu603; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t604; CHECK-NEXT:    ret605entry:606  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i32(607    <vscale x 4 x i64> %0,608    ptr %1,609    <vscale x 4 x i32> %2,610    <vscale x 4 x i1> %3,611    iXLen %4, iXLen 1)612 613  ret <vscale x 4 x i64> %a614}615 616define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {617; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i32:618; CHECK:       # %bb.0: # %entry619; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma620; CHECK-NEXT:    vmv4r.v v16, v8621; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma622; CHECK-NEXT:    vluxei32.v v8, (a0), v16623; CHECK-NEXT:    ret624entry:625  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i32(626    <vscale x 8 x i64> poison,627    ptr %0,628    <vscale x 8 x i32> %1,629    iXLen %2)630 631  ret <vscale x 8 x i64> %a632}633 634define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {635; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i32:636; CHECK:       # %bb.0: # %entry637; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu638; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t639; CHECK-NEXT:    ret640entry:641  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i32(642    <vscale x 8 x i64> %0,643    ptr %1,644    <vscale x 8 x i32> %2,645    <vscale x 8 x i1> %3,646    iXLen %4, iXLen 1)647 648  ret <vscale x 8 x i64> %a649}650 651define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {652; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i32:653; CHECK:       # %bb.0: # %entry654; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma655; CHECK-NEXT:    vluxei32.v v9, (a0), v8656; CHECK-NEXT:    vmv1r.v v8, v9657; CHECK-NEXT:    ret658entry:659  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i32(660    <vscale x 1 x half> poison,661    ptr %0,662    <vscale x 1 x i32> %1,663    iXLen %2)664 665  ret <vscale x 1 x half> %a666}667 668define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i32(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {669; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i32:670; CHECK:       # %bb.0: # %entry671; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu672; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t673; CHECK-NEXT:    ret674entry:675  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i32(676    <vscale x 1 x half> %0,677    ptr %1,678    <vscale x 1 x i32> %2,679    <vscale x 1 x i1> %3,680    iXLen %4, iXLen 1)681 682  ret <vscale x 1 x half> %a683}684 685define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {686; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i32:687; CHECK:       # %bb.0: # %entry688; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma689; CHECK-NEXT:    vluxei32.v v9, (a0), v8690; CHECK-NEXT:    vmv1r.v v8, v9691; CHECK-NEXT:    ret692entry:693  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i32(694    <vscale x 2 x half> poison,695    ptr %0,696    <vscale x 2 x i32> %1,697    iXLen %2)698 699  ret <vscale x 2 x half> %a700}701 702define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i32(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {703; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i32:704; CHECK:       # %bb.0: # %entry705; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu706; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t707; CHECK-NEXT:    ret708entry:709  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i32(710    <vscale x 2 x half> %0,711    ptr %1,712    <vscale x 2 x i32> %2,713    <vscale x 2 x i1> %3,714    iXLen %4, iXLen 1)715 716  ret <vscale x 2 x half> %a717}718 719define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {720; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i32:721; CHECK:       # %bb.0: # %entry722; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma723; CHECK-NEXT:    vluxei32.v v10, (a0), v8724; CHECK-NEXT:    vmv.v.v v8, v10725; CHECK-NEXT:    ret726entry:727  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i32(728    <vscale x 4 x half> poison,729    ptr %0,730    <vscale x 4 x i32> %1,731    iXLen %2)732 733  ret <vscale x 4 x half> %a734}735 736define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i32(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {737; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i32:738; CHECK:       # %bb.0: # %entry739; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu740; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t741; CHECK-NEXT:    ret742entry:743  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i32(744    <vscale x 4 x half> %0,745    ptr %1,746    <vscale x 4 x i32> %2,747    <vscale x 4 x i1> %3,748    iXLen %4, iXLen 1)749 750  ret <vscale x 4 x half> %a751}752 753define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {754; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i32:755; CHECK:       # %bb.0: # %entry756; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma757; CHECK-NEXT:    vluxei32.v v12, (a0), v8758; CHECK-NEXT:    vmv.v.v v8, v12759; CHECK-NEXT:    ret760entry:761  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i32(762    <vscale x 8 x half> poison,763    ptr %0,764    <vscale x 8 x i32> %1,765    iXLen %2)766 767  ret <vscale x 8 x half> %a768}769 770define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i32(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {771; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i32:772; CHECK:       # %bb.0: # %entry773; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu774; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t775; CHECK-NEXT:    ret776entry:777  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i32(778    <vscale x 8 x half> %0,779    ptr %1,780    <vscale x 8 x i32> %2,781    <vscale x 8 x i1> %3,782    iXLen %4, iXLen 1)783 784  ret <vscale x 8 x half> %a785}786 787define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {788; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i32:789; CHECK:       # %bb.0: # %entry790; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma791; CHECK-NEXT:    vluxei32.v v16, (a0), v8792; CHECK-NEXT:    vmv.v.v v8, v16793; CHECK-NEXT:    ret794entry:795  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i32(796    <vscale x 16 x half> poison,797    ptr %0,798    <vscale x 16 x i32> %1,799    iXLen %2)800 801  ret <vscale x 16 x half> %a802}803 804define <vscale x 16 x half> @intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i32(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {805; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i32:806; CHECK:       # %bb.0: # %entry807; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu808; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t809; CHECK-NEXT:    ret810entry:811  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i32(812    <vscale x 16 x half> %0,813    ptr %1,814    <vscale x 16 x i32> %2,815    <vscale x 16 x i1> %3,816    iXLen %4, iXLen 1)817 818  ret <vscale x 16 x half> %a819}820 821define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {822; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i32:823; CHECK:       # %bb.0: # %entry824; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma825; CHECK-NEXT:    vluxei32.v v8, (a0), v8826; CHECK-NEXT:    ret827entry:828  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i32(829    <vscale x 1 x float> poison,830    ptr %0,831    <vscale x 1 x i32> %1,832    iXLen %2)833 834  ret <vscale x 1 x float> %a835}836 837define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {838; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i32:839; CHECK:       # %bb.0: # %entry840; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu841; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t842; CHECK-NEXT:    ret843entry:844  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i32(845    <vscale x 1 x float> %0,846    ptr %1,847    <vscale x 1 x i32> %2,848    <vscale x 1 x i1> %3,849    iXLen %4, iXLen 1)850 851  ret <vscale x 1 x float> %a852}853 854define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {855; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i32:856; CHECK:       # %bb.0: # %entry857; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma858; CHECK-NEXT:    vluxei32.v v8, (a0), v8859; CHECK-NEXT:    ret860entry:861  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i32(862    <vscale x 2 x float> poison,863    ptr %0,864    <vscale x 2 x i32> %1,865    iXLen %2)866 867  ret <vscale x 2 x float> %a868}869 870define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {871; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i32:872; CHECK:       # %bb.0: # %entry873; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu874; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t875; CHECK-NEXT:    ret876entry:877  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i32(878    <vscale x 2 x float> %0,879    ptr %1,880    <vscale x 2 x i32> %2,881    <vscale x 2 x i1> %3,882    iXLen %4, iXLen 1)883 884  ret <vscale x 2 x float> %a885}886 887define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {888; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i32:889; CHECK:       # %bb.0: # %entry890; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma891; CHECK-NEXT:    vluxei32.v v8, (a0), v8892; CHECK-NEXT:    ret893entry:894  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i32(895    <vscale x 4 x float> poison,896    ptr %0,897    <vscale x 4 x i32> %1,898    iXLen %2)899 900  ret <vscale x 4 x float> %a901}902 903define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {904; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i32:905; CHECK:       # %bb.0: # %entry906; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu907; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t908; CHECK-NEXT:    ret909entry:910  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i32(911    <vscale x 4 x float> %0,912    ptr %1,913    <vscale x 4 x i32> %2,914    <vscale x 4 x i1> %3,915    iXLen %4, iXLen 1)916 917  ret <vscale x 4 x float> %a918}919 920define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {921; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i32:922; CHECK:       # %bb.0: # %entry923; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma924; CHECK-NEXT:    vluxei32.v v8, (a0), v8925; CHECK-NEXT:    ret926entry:927  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i32(928    <vscale x 8 x float> poison,929    ptr %0,930    <vscale x 8 x i32> %1,931    iXLen %2)932 933  ret <vscale x 8 x float> %a934}935 936define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {937; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i32:938; CHECK:       # %bb.0: # %entry939; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu940; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t941; CHECK-NEXT:    ret942entry:943  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i32(944    <vscale x 8 x float> %0,945    ptr %1,946    <vscale x 8 x i32> %2,947    <vscale x 8 x i1> %3,948    iXLen %4, iXLen 1)949 950  ret <vscale x 8 x float> %a951}952 953define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32(ptr %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {954; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i32:955; CHECK:       # %bb.0: # %entry956; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma957; CHECK-NEXT:    vluxei32.v v8, (a0), v8958; CHECK-NEXT:    ret959entry:960  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i32(961    <vscale x 16 x float> poison,962    ptr %0,963    <vscale x 16 x i32> %1,964    iXLen %2)965 966  ret <vscale x 16 x float> %a967}968 969define <vscale x 16 x float> @intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {970; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i32:971; CHECK:       # %bb.0: # %entry972; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu973; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t974; CHECK-NEXT:    ret975entry:976  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i32(977    <vscale x 16 x float> %0,978    ptr %1,979    <vscale x 16 x i32> %2,980    <vscale x 16 x i1> %3,981    iXLen %4, iXLen 1)982 983  ret <vscale x 16 x float> %a984}985 986define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32(ptr %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {987; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i32:988; CHECK:       # %bb.0: # %entry989; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma990; CHECK-NEXT:    vluxei32.v v9, (a0), v8991; CHECK-NEXT:    vmv.v.v v8, v9992; CHECK-NEXT:    ret993entry:994  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i32(995    <vscale x 1 x double> poison,996    ptr %0,997    <vscale x 1 x i32> %1,998    iXLen %2)999 1000  ret <vscale x 1 x double> %a1001}1002 1003define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i32(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1004; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i32:1005; CHECK:       # %bb.0: # %entry1006; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1007; CHECK-NEXT:    vluxei32.v v8, (a0), v9, v0.t1008; CHECK-NEXT:    ret1009entry:1010  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i32(1011    <vscale x 1 x double> %0,1012    ptr %1,1013    <vscale x 1 x i32> %2,1014    <vscale x 1 x i1> %3,1015    iXLen %4, iXLen 1)1016 1017  ret <vscale x 1 x double> %a1018}1019 1020define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32(ptr %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {1021; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i32:1022; CHECK:       # %bb.0: # %entry1023; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1024; CHECK-NEXT:    vmv1r.v v10, v81025; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1026; CHECK-NEXT:    vluxei32.v v8, (a0), v101027; CHECK-NEXT:    ret1028entry:1029  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i32(1030    <vscale x 2 x double> poison,1031    ptr %0,1032    <vscale x 2 x i32> %1,1033    iXLen %2)1034 1035  ret <vscale x 2 x double> %a1036}1037 1038define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i32(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1039; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i32:1040; CHECK:       # %bb.0: # %entry1041; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1042; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t1043; CHECK-NEXT:    ret1044entry:1045  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i32(1046    <vscale x 2 x double> %0,1047    ptr %1,1048    <vscale x 2 x i32> %2,1049    <vscale x 2 x i1> %3,1050    iXLen %4, iXLen 1)1051 1052  ret <vscale x 2 x double> %a1053}1054 1055define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32(ptr %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {1056; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i32:1057; CHECK:       # %bb.0: # %entry1058; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1059; CHECK-NEXT:    vmv2r.v v12, v81060; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1061; CHECK-NEXT:    vluxei32.v v8, (a0), v121062; CHECK-NEXT:    ret1063entry:1064  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i32(1065    <vscale x 4 x double> poison,1066    ptr %0,1067    <vscale x 4 x i32> %1,1068    iXLen %2)1069 1070  ret <vscale x 4 x double> %a1071}1072 1073define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i32(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1074; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i32:1075; CHECK:       # %bb.0: # %entry1076; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1077; CHECK-NEXT:    vluxei32.v v8, (a0), v12, v0.t1078; CHECK-NEXT:    ret1079entry:1080  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i32(1081    <vscale x 4 x double> %0,1082    ptr %1,1083    <vscale x 4 x i32> %2,1084    <vscale x 4 x i1> %3,1085    iXLen %4, iXLen 1)1086 1087  ret <vscale x 4 x double> %a1088}1089 1090define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32(ptr %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {1091; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i32:1092; CHECK:       # %bb.0: # %entry1093; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1094; CHECK-NEXT:    vmv4r.v v16, v81095; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1096; CHECK-NEXT:    vluxei32.v v8, (a0), v161097; CHECK-NEXT:    ret1098entry:1099  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i32(1100    <vscale x 8 x double> poison,1101    ptr %0,1102    <vscale x 8 x i32> %1,1103    iXLen %2)1104 1105  ret <vscale x 8 x double> %a1106}1107 1108define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i32(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1109; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i32:1110; CHECK:       # %bb.0: # %entry1111; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1112; CHECK-NEXT:    vluxei32.v v8, (a0), v16, v0.t1113; CHECK-NEXT:    ret1114entry:1115  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i32(1116    <vscale x 8 x double> %0,1117    ptr %1,1118    <vscale x 8 x i32> %2,1119    <vscale x 8 x i1> %3,1120    iXLen %4, iXLen 1)1121 1122  ret <vscale x 8 x double> %a1123}1124 1125define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1126; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i16:1127; CHECK:       # %bb.0: # %entry1128; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma1129; CHECK-NEXT:    vluxei16.v v9, (a0), v81130; CHECK-NEXT:    vmv1r.v v8, v91131; CHECK-NEXT:    ret1132entry:1133  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i16(1134    <vscale x 1 x i8> poison,1135    ptr %0,1136    <vscale x 1 x i16> %1,1137    iXLen %2)1138 1139  ret <vscale x 1 x i8> %a1140}1141 1142define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i16(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1143; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i16:1144; CHECK:       # %bb.0: # %entry1145; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu1146; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1147; CHECK-NEXT:    ret1148entry:1149  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i16(1150    <vscale x 1 x i8> %0,1151    ptr %1,1152    <vscale x 1 x i16> %2,1153    <vscale x 1 x i1> %3,1154    iXLen %4, iXLen 1)1155 1156  ret <vscale x 1 x i8> %a1157}1158 1159define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1160; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i16:1161; CHECK:       # %bb.0: # %entry1162; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma1163; CHECK-NEXT:    vluxei16.v v9, (a0), v81164; CHECK-NEXT:    vmv1r.v v8, v91165; CHECK-NEXT:    ret1166entry:1167  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i16(1168    <vscale x 2 x i8> poison,1169    ptr %0,1170    <vscale x 2 x i16> %1,1171    iXLen %2)1172 1173  ret <vscale x 2 x i8> %a1174}1175 1176define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i16(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1177; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i16:1178; CHECK:       # %bb.0: # %entry1179; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu1180; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1181; CHECK-NEXT:    ret1182entry:1183  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i16(1184    <vscale x 2 x i8> %0,1185    ptr %1,1186    <vscale x 2 x i16> %2,1187    <vscale x 2 x i1> %3,1188    iXLen %4, iXLen 1)1189 1190  ret <vscale x 2 x i8> %a1191}1192 1193define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1194; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i16:1195; CHECK:       # %bb.0: # %entry1196; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma1197; CHECK-NEXT:    vluxei16.v v9, (a0), v81198; CHECK-NEXT:    vmv1r.v v8, v91199; CHECK-NEXT:    ret1200entry:1201  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i16(1202    <vscale x 4 x i8> poison,1203    ptr %0,1204    <vscale x 4 x i16> %1,1205    iXLen %2)1206 1207  ret <vscale x 4 x i8> %a1208}1209 1210define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i16(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1211; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i16:1212; CHECK:       # %bb.0: # %entry1213; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu1214; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1215; CHECK-NEXT:    ret1216entry:1217  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i16(1218    <vscale x 4 x i8> %0,1219    ptr %1,1220    <vscale x 4 x i16> %2,1221    <vscale x 4 x i1> %3,1222    iXLen %4, iXLen 1)1223 1224  ret <vscale x 4 x i8> %a1225}1226 1227define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1228; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i16:1229; CHECK:       # %bb.0: # %entry1230; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma1231; CHECK-NEXT:    vluxei16.v v10, (a0), v81232; CHECK-NEXT:    vmv.v.v v8, v101233; CHECK-NEXT:    ret1234entry:1235  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i16(1236    <vscale x 8 x i8> poison,1237    ptr %0,1238    <vscale x 8 x i16> %1,1239    iXLen %2)1240 1241  ret <vscale x 8 x i8> %a1242}1243 1244define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i16(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1245; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i16:1246; CHECK:       # %bb.0: # %entry1247; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu1248; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1249; CHECK-NEXT:    ret1250entry:1251  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i16(1252    <vscale x 8 x i8> %0,1253    ptr %1,1254    <vscale x 8 x i16> %2,1255    <vscale x 8 x i1> %3,1256    iXLen %4, iXLen 1)1257 1258  ret <vscale x 8 x i8> %a1259}1260 1261define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1262; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i16:1263; CHECK:       # %bb.0: # %entry1264; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma1265; CHECK-NEXT:    vluxei16.v v12, (a0), v81266; CHECK-NEXT:    vmv.v.v v8, v121267; CHECK-NEXT:    ret1268entry:1269  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i16(1270    <vscale x 16 x i8> poison,1271    ptr %0,1272    <vscale x 16 x i16> %1,1273    iXLen %2)1274 1275  ret <vscale x 16 x i8> %a1276}1277 1278define <vscale x 16 x i8> @intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i16(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1279; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i16:1280; CHECK:       # %bb.0: # %entry1281; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu1282; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1283; CHECK-NEXT:    ret1284entry:1285  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i16(1286    <vscale x 16 x i8> %0,1287    ptr %1,1288    <vscale x 16 x i16> %2,1289    <vscale x 16 x i1> %3,1290    iXLen %4, iXLen 1)1291 1292  ret <vscale x 16 x i8> %a1293}1294 1295define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1296; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i16:1297; CHECK:       # %bb.0: # %entry1298; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma1299; CHECK-NEXT:    vluxei16.v v16, (a0), v81300; CHECK-NEXT:    vmv.v.v v8, v161301; CHECK-NEXT:    ret1302entry:1303  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i16(1304    <vscale x 32 x i8> poison,1305    ptr %0,1306    <vscale x 32 x i16> %1,1307    iXLen %2)1308 1309  ret <vscale x 32 x i8> %a1310}1311 1312define <vscale x 32 x i8> @intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i16(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1313; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i16:1314; CHECK:       # %bb.0: # %entry1315; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu1316; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1317; CHECK-NEXT:    ret1318entry:1319  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i16(1320    <vscale x 32 x i8> %0,1321    ptr %1,1322    <vscale x 32 x i16> %2,1323    <vscale x 32 x i1> %3,1324    iXLen %4, iXLen 1)1325 1326  ret <vscale x 32 x i8> %a1327}1328 1329define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1330; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i16:1331; CHECK:       # %bb.0: # %entry1332; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1333; CHECK-NEXT:    vluxei16.v v8, (a0), v81334; CHECK-NEXT:    ret1335entry:1336  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i16(1337    <vscale x 1 x i16> poison,1338    ptr %0,1339    <vscale x 1 x i16> %1,1340    iXLen %2)1341 1342  ret <vscale x 1 x i16> %a1343}1344 1345define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1346; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i16:1347; CHECK:       # %bb.0: # %entry1348; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu1349; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1350; CHECK-NEXT:    ret1351entry:1352  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i16(1353    <vscale x 1 x i16> %0,1354    ptr %1,1355    <vscale x 1 x i16> %2,1356    <vscale x 1 x i1> %3,1357    iXLen %4, iXLen 1)1358 1359  ret <vscale x 1 x i16> %a1360}1361 1362define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1363; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i16:1364; CHECK:       # %bb.0: # %entry1365; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1366; CHECK-NEXT:    vluxei16.v v8, (a0), v81367; CHECK-NEXT:    ret1368entry:1369  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i16(1370    <vscale x 2 x i16> poison,1371    ptr %0,1372    <vscale x 2 x i16> %1,1373    iXLen %2)1374 1375  ret <vscale x 2 x i16> %a1376}1377 1378define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1379; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i16:1380; CHECK:       # %bb.0: # %entry1381; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1382; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1383; CHECK-NEXT:    ret1384entry:1385  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i16(1386    <vscale x 2 x i16> %0,1387    ptr %1,1388    <vscale x 2 x i16> %2,1389    <vscale x 2 x i1> %3,1390    iXLen %4, iXLen 1)1391 1392  ret <vscale x 2 x i16> %a1393}1394 1395define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1396; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i16:1397; CHECK:       # %bb.0: # %entry1398; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1399; CHECK-NEXT:    vluxei16.v v8, (a0), v81400; CHECK-NEXT:    ret1401entry:1402  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i16(1403    <vscale x 4 x i16> poison,1404    ptr %0,1405    <vscale x 4 x i16> %1,1406    iXLen %2)1407 1408  ret <vscale x 4 x i16> %a1409}1410 1411define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1412; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i16:1413; CHECK:       # %bb.0: # %entry1414; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1415; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1416; CHECK-NEXT:    ret1417entry:1418  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i16(1419    <vscale x 4 x i16> %0,1420    ptr %1,1421    <vscale x 4 x i16> %2,1422    <vscale x 4 x i1> %3,1423    iXLen %4, iXLen 1)1424 1425  ret <vscale x 4 x i16> %a1426}1427 1428define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1429; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i16:1430; CHECK:       # %bb.0: # %entry1431; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1432; CHECK-NEXT:    vluxei16.v v8, (a0), v81433; CHECK-NEXT:    ret1434entry:1435  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i16(1436    <vscale x 8 x i16> poison,1437    ptr %0,1438    <vscale x 8 x i16> %1,1439    iXLen %2)1440 1441  ret <vscale x 8 x i16> %a1442}1443 1444define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1445; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i16:1446; CHECK:       # %bb.0: # %entry1447; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1448; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1449; CHECK-NEXT:    ret1450entry:1451  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i16(1452    <vscale x 8 x i16> %0,1453    ptr %1,1454    <vscale x 8 x i16> %2,1455    <vscale x 8 x i1> %3,1456    iXLen %4, iXLen 1)1457 1458  ret <vscale x 8 x i16> %a1459}1460 1461define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1462; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i16:1463; CHECK:       # %bb.0: # %entry1464; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1465; CHECK-NEXT:    vluxei16.v v8, (a0), v81466; CHECK-NEXT:    ret1467entry:1468  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i16(1469    <vscale x 16 x i16> poison,1470    ptr %0,1471    <vscale x 16 x i16> %1,1472    iXLen %2)1473 1474  ret <vscale x 16 x i16> %a1475}1476 1477define <vscale x 16 x i16> @intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1478; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i16:1479; CHECK:       # %bb.0: # %entry1480; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1481; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1482; CHECK-NEXT:    ret1483entry:1484  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i16(1485    <vscale x 16 x i16> %0,1486    ptr %1,1487    <vscale x 16 x i16> %2,1488    <vscale x 16 x i1> %3,1489    iXLen %4, iXLen 1)1490 1491  ret <vscale x 16 x i16> %a1492}1493 1494define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1495; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i16:1496; CHECK:       # %bb.0: # %entry1497; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1498; CHECK-NEXT:    vluxei16.v v8, (a0), v81499; CHECK-NEXT:    ret1500entry:1501  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i16(1502    <vscale x 32 x i16> poison,1503    ptr %0,1504    <vscale x 32 x i16> %1,1505    iXLen %2)1506 1507  ret <vscale x 32 x i16> %a1508}1509 1510define <vscale x 32 x i16> @intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1511; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i16:1512; CHECK:       # %bb.0: # %entry1513; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu1514; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1515; CHECK-NEXT:    ret1516entry:1517  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i16(1518    <vscale x 32 x i16> %0,1519    ptr %1,1520    <vscale x 32 x i16> %2,1521    <vscale x 32 x i1> %3,1522    iXLen %4, iXLen 1)1523 1524  ret <vscale x 32 x i16> %a1525}1526 1527define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1528; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16:1529; CHECK:       # %bb.0: # %entry1530; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1531; CHECK-NEXT:    vluxei16.v v9, (a0), v81532; CHECK-NEXT:    vmv1r.v v8, v91533; CHECK-NEXT:    ret1534entry:1535  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(1536    <vscale x 1 x i32> poison,1537    ptr %0,1538    <vscale x 1 x i16> %1,1539    iXLen %2)1540 1541  ret <vscale x 1 x i32> %a1542}1543 1544define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1545; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16:1546; CHECK:       # %bb.0: # %entry1547; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1548; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1549; CHECK-NEXT:    ret1550entry:1551  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(1552    <vscale x 1 x i32> %0,1553    ptr %1,1554    <vscale x 1 x i16> %2,1555    <vscale x 1 x i1> %3,1556    iXLen %4, iXLen 1)1557 1558  ret <vscale x 1 x i32> %a1559}1560 1561define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1562; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i16:1563; CHECK:       # %bb.0: # %entry1564; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1565; CHECK-NEXT:    vluxei16.v v9, (a0), v81566; CHECK-NEXT:    vmv.v.v v8, v91567; CHECK-NEXT:    ret1568entry:1569  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i16(1570    <vscale x 2 x i32> poison,1571    ptr %0,1572    <vscale x 2 x i16> %1,1573    iXLen %2)1574 1575  ret <vscale x 2 x i32> %a1576}1577 1578define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1579; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i16:1580; CHECK:       # %bb.0: # %entry1581; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1582; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1583; CHECK-NEXT:    ret1584entry:1585  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i16(1586    <vscale x 2 x i32> %0,1587    ptr %1,1588    <vscale x 2 x i16> %2,1589    <vscale x 2 x i1> %3,1590    iXLen %4, iXLen 1)1591 1592  ret <vscale x 2 x i32> %a1593}1594 1595define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1596; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i16:1597; CHECK:       # %bb.0: # %entry1598; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1599; CHECK-NEXT:    vmv1r.v v10, v81600; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1601; CHECK-NEXT:    vluxei16.v v8, (a0), v101602; CHECK-NEXT:    ret1603entry:1604  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i16(1605    <vscale x 4 x i32> poison,1606    ptr %0,1607    <vscale x 4 x i16> %1,1608    iXLen %2)1609 1610  ret <vscale x 4 x i32> %a1611}1612 1613define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1614; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i16:1615; CHECK:       # %bb.0: # %entry1616; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1617; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1618; CHECK-NEXT:    ret1619entry:1620  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i16(1621    <vscale x 4 x i32> %0,1622    ptr %1,1623    <vscale x 4 x i16> %2,1624    <vscale x 4 x i1> %3,1625    iXLen %4, iXLen 1)1626 1627  ret <vscale x 4 x i32> %a1628}1629 1630define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1631; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i16:1632; CHECK:       # %bb.0: # %entry1633; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1634; CHECK-NEXT:    vmv2r.v v12, v81635; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1636; CHECK-NEXT:    vluxei16.v v8, (a0), v121637; CHECK-NEXT:    ret1638entry:1639  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i16(1640    <vscale x 8 x i32> poison,1641    ptr %0,1642    <vscale x 8 x i16> %1,1643    iXLen %2)1644 1645  ret <vscale x 8 x i32> %a1646}1647 1648define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1649; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i16:1650; CHECK:       # %bb.0: # %entry1651; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1652; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1653; CHECK-NEXT:    ret1654entry:1655  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i16(1656    <vscale x 8 x i32> %0,1657    ptr %1,1658    <vscale x 8 x i16> %2,1659    <vscale x 8 x i1> %3,1660    iXLen %4, iXLen 1)1661 1662  ret <vscale x 8 x i32> %a1663}1664 1665define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1666; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i16:1667; CHECK:       # %bb.0: # %entry1668; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1669; CHECK-NEXT:    vmv4r.v v16, v81670; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1671; CHECK-NEXT:    vluxei16.v v8, (a0), v161672; CHECK-NEXT:    ret1673entry:1674  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i16(1675    <vscale x 16 x i32> poison,1676    ptr %0,1677    <vscale x 16 x i16> %1,1678    iXLen %2)1679 1680  ret <vscale x 16 x i32> %a1681}1682 1683define <vscale x 16 x i32> @intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i16(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1684; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i16:1685; CHECK:       # %bb.0: # %entry1686; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1687; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1688; CHECK-NEXT:    ret1689entry:1690  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i16(1691    <vscale x 16 x i32> %0,1692    ptr %1,1693    <vscale x 16 x i16> %2,1694    <vscale x 16 x i1> %3,1695    iXLen %4, iXLen 1)1696 1697  ret <vscale x 16 x i32> %a1698}1699 1700define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1701; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i16:1702; CHECK:       # %bb.0: # %entry1703; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1704; CHECK-NEXT:    vluxei16.v v9, (a0), v81705; CHECK-NEXT:    vmv.v.v v8, v91706; CHECK-NEXT:    ret1707entry:1708  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i16(1709    <vscale x 1 x i64> poison,1710    ptr %0,1711    <vscale x 1 x i16> %1,1712    iXLen %2)1713 1714  ret <vscale x 1 x i64> %a1715}1716 1717define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i16(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1718; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i16:1719; CHECK:       # %bb.0: # %entry1720; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1721; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1722; CHECK-NEXT:    ret1723entry:1724  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i16(1725    <vscale x 1 x i64> %0,1726    ptr %1,1727    <vscale x 1 x i16> %2,1728    <vscale x 1 x i1> %3,1729    iXLen %4, iXLen 1)1730 1731  ret <vscale x 1 x i64> %a1732}1733 1734define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1735; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i16:1736; CHECK:       # %bb.0: # %entry1737; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1738; CHECK-NEXT:    vmv1r.v v10, v81739; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1740; CHECK-NEXT:    vluxei16.v v8, (a0), v101741; CHECK-NEXT:    ret1742entry:1743  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i16(1744    <vscale x 2 x i64> poison,1745    ptr %0,1746    <vscale x 2 x i16> %1,1747    iXLen %2)1748 1749  ret <vscale x 2 x i64> %a1750}1751 1752define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i16(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1753; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i16:1754; CHECK:       # %bb.0: # %entry1755; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1756; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1757; CHECK-NEXT:    ret1758entry:1759  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i16(1760    <vscale x 2 x i64> %0,1761    ptr %1,1762    <vscale x 2 x i16> %2,1763    <vscale x 2 x i1> %3,1764    iXLen %4, iXLen 1)1765 1766  ret <vscale x 2 x i64> %a1767}1768 1769define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1770; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i16:1771; CHECK:       # %bb.0: # %entry1772; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1773; CHECK-NEXT:    vmv1r.v v12, v81774; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1775; CHECK-NEXT:    vluxei16.v v8, (a0), v121776; CHECK-NEXT:    ret1777entry:1778  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i16(1779    <vscale x 4 x i64> poison,1780    ptr %0,1781    <vscale x 4 x i16> %1,1782    iXLen %2)1783 1784  ret <vscale x 4 x i64> %a1785}1786 1787define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i16(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1788; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i16:1789; CHECK:       # %bb.0: # %entry1790; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1791; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1792; CHECK-NEXT:    ret1793entry:1794  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i16(1795    <vscale x 4 x i64> %0,1796    ptr %1,1797    <vscale x 4 x i16> %2,1798    <vscale x 4 x i1> %3,1799    iXLen %4, iXLen 1)1800 1801  ret <vscale x 4 x i64> %a1802}1803 1804define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1805; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i16:1806; CHECK:       # %bb.0: # %entry1807; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma1808; CHECK-NEXT:    vmv2r.v v16, v81809; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1810; CHECK-NEXT:    vluxei16.v v8, (a0), v161811; CHECK-NEXT:    ret1812entry:1813  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i16(1814    <vscale x 8 x i64> poison,1815    ptr %0,1816    <vscale x 8 x i16> %1,1817    iXLen %2)1818 1819  ret <vscale x 8 x i64> %a1820}1821 1822define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i16(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1823; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i16:1824; CHECK:       # %bb.0: # %entry1825; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1826; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t1827; CHECK-NEXT:    ret1828entry:1829  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i16(1830    <vscale x 8 x i64> %0,1831    ptr %1,1832    <vscale x 8 x i16> %2,1833    <vscale x 8 x i1> %3,1834    iXLen %4, iXLen 1)1835 1836  ret <vscale x 8 x i64> %a1837}1838 1839define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1840; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i16:1841; CHECK:       # %bb.0: # %entry1842; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1843; CHECK-NEXT:    vluxei16.v v8, (a0), v81844; CHECK-NEXT:    ret1845entry:1846  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i16(1847    <vscale x 1 x half> poison,1848    ptr %0,1849    <vscale x 1 x i16> %1,1850    iXLen %2)1851 1852  ret <vscale x 1 x half> %a1853}1854 1855define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1856; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i16:1857; CHECK:       # %bb.0: # %entry1858; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu1859; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1860; CHECK-NEXT:    ret1861entry:1862  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i16(1863    <vscale x 1 x half> %0,1864    ptr %1,1865    <vscale x 1 x i16> %2,1866    <vscale x 1 x i1> %3,1867    iXLen %4, iXLen 1)1868 1869  ret <vscale x 1 x half> %a1870}1871 1872define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1873; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i16:1874; CHECK:       # %bb.0: # %entry1875; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1876; CHECK-NEXT:    vluxei16.v v8, (a0), v81877; CHECK-NEXT:    ret1878entry:1879  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i16(1880    <vscale x 2 x half> poison,1881    ptr %0,1882    <vscale x 2 x i16> %1,1883    iXLen %2)1884 1885  ret <vscale x 2 x half> %a1886}1887 1888define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1889; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i16:1890; CHECK:       # %bb.0: # %entry1891; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1892; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1893; CHECK-NEXT:    ret1894entry:1895  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i16(1896    <vscale x 2 x half> %0,1897    ptr %1,1898    <vscale x 2 x i16> %2,1899    <vscale x 2 x i1> %3,1900    iXLen %4, iXLen 1)1901 1902  ret <vscale x 2 x half> %a1903}1904 1905define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1906; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i16:1907; CHECK:       # %bb.0: # %entry1908; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1909; CHECK-NEXT:    vluxei16.v v8, (a0), v81910; CHECK-NEXT:    ret1911entry:1912  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i16(1913    <vscale x 4 x half> poison,1914    ptr %0,1915    <vscale x 4 x i16> %1,1916    iXLen %2)1917 1918  ret <vscale x 4 x half> %a1919}1920 1921define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1922; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i16:1923; CHECK:       # %bb.0: # %entry1924; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1925; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t1926; CHECK-NEXT:    ret1927entry:1928  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i16(1929    <vscale x 4 x half> %0,1930    ptr %1,1931    <vscale x 4 x i16> %2,1932    <vscale x 4 x i1> %3,1933    iXLen %4, iXLen 1)1934 1935  ret <vscale x 4 x half> %a1936}1937 1938define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1939; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i16:1940; CHECK:       # %bb.0: # %entry1941; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1942; CHECK-NEXT:    vluxei16.v v8, (a0), v81943; CHECK-NEXT:    ret1944entry:1945  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i16(1946    <vscale x 8 x half> poison,1947    ptr %0,1948    <vscale x 8 x i16> %1,1949    iXLen %2)1950 1951  ret <vscale x 8 x half> %a1952}1953 1954define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1955; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i16:1956; CHECK:       # %bb.0: # %entry1957; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1958; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t1959; CHECK-NEXT:    ret1960entry:1961  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i16(1962    <vscale x 8 x half> %0,1963    ptr %1,1964    <vscale x 8 x i16> %2,1965    <vscale x 8 x i1> %3,1966    iXLen %4, iXLen 1)1967 1968  ret <vscale x 8 x half> %a1969}1970 1971define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1972; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i16:1973; CHECK:       # %bb.0: # %entry1974; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1975; CHECK-NEXT:    vluxei16.v v8, (a0), v81976; CHECK-NEXT:    ret1977entry:1978  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i16(1979    <vscale x 16 x half> poison,1980    ptr %0,1981    <vscale x 16 x i16> %1,1982    iXLen %2)1983 1984  ret <vscale x 16 x half> %a1985}1986 1987define <vscale x 16 x half> @intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1988; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i16:1989; CHECK:       # %bb.0: # %entry1990; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1991; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t1992; CHECK-NEXT:    ret1993entry:1994  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i16(1995    <vscale x 16 x half> %0,1996    ptr %1,1997    <vscale x 16 x i16> %2,1998    <vscale x 16 x i1> %3,1999    iXLen %4, iXLen 1)2000 2001  ret <vscale x 16 x half> %a2002}2003 2004define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16(ptr %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {2005; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i16:2006; CHECK:       # %bb.0: # %entry2007; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2008; CHECK-NEXT:    vluxei16.v v8, (a0), v82009; CHECK-NEXT:    ret2010entry:2011  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i16(2012    <vscale x 32 x half> poison,2013    ptr %0,2014    <vscale x 32 x i16> %1,2015    iXLen %2)2016 2017  ret <vscale x 32 x half> %a2018}2019 2020define <vscale x 32 x half> @intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2021; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i16:2022; CHECK:       # %bb.0: # %entry2023; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu2024; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t2025; CHECK-NEXT:    ret2026entry:2027  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i16(2028    <vscale x 32 x half> %0,2029    ptr %1,2030    <vscale x 32 x i16> %2,2031    <vscale x 32 x i1> %3,2032    iXLen %4, iXLen 1)2033 2034  ret <vscale x 32 x half> %a2035}2036 2037define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {2038; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i16:2039; CHECK:       # %bb.0: # %entry2040; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2041; CHECK-NEXT:    vluxei16.v v9, (a0), v82042; CHECK-NEXT:    vmv1r.v v8, v92043; CHECK-NEXT:    ret2044entry:2045  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i16(2046    <vscale x 1 x float> poison,2047    ptr %0,2048    <vscale x 1 x i16> %1,2049    iXLen %2)2050 2051  ret <vscale x 1 x float> %a2052}2053 2054define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2055; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i16:2056; CHECK:       # %bb.0: # %entry2057; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu2058; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2059; CHECK-NEXT:    ret2060entry:2061  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i16(2062    <vscale x 1 x float> %0,2063    ptr %1,2064    <vscale x 1 x i16> %2,2065    <vscale x 1 x i1> %3,2066    iXLen %4, iXLen 1)2067 2068  ret <vscale x 1 x float> %a2069}2070 2071define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {2072; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i16:2073; CHECK:       # %bb.0: # %entry2074; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2075; CHECK-NEXT:    vluxei16.v v9, (a0), v82076; CHECK-NEXT:    vmv.v.v v8, v92077; CHECK-NEXT:    ret2078entry:2079  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i16(2080    <vscale x 2 x float> poison,2081    ptr %0,2082    <vscale x 2 x i16> %1,2083    iXLen %2)2084 2085  ret <vscale x 2 x float> %a2086}2087 2088define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i16(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2089; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i16:2090; CHECK:       # %bb.0: # %entry2091; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu2092; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2093; CHECK-NEXT:    ret2094entry:2095  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i16(2096    <vscale x 2 x float> %0,2097    ptr %1,2098    <vscale x 2 x i16> %2,2099    <vscale x 2 x i1> %3,2100    iXLen %4, iXLen 1)2101 2102  ret <vscale x 2 x float> %a2103}2104 2105define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2106; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i16:2107; CHECK:       # %bb.0: # %entry2108; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2109; CHECK-NEXT:    vmv1r.v v10, v82110; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2111; CHECK-NEXT:    vluxei16.v v8, (a0), v102112; CHECK-NEXT:    ret2113entry:2114  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i16(2115    <vscale x 4 x float> poison,2116    ptr %0,2117    <vscale x 4 x i16> %1,2118    iXLen %2)2119 2120  ret <vscale x 4 x float> %a2121}2122 2123define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i16(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2124; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i16:2125; CHECK:       # %bb.0: # %entry2126; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu2127; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t2128; CHECK-NEXT:    ret2129entry:2130  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i16(2131    <vscale x 4 x float> %0,2132    ptr %1,2133    <vscale x 4 x i16> %2,2134    <vscale x 4 x i1> %3,2135    iXLen %4, iXLen 1)2136 2137  ret <vscale x 4 x float> %a2138}2139 2140define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2141; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i16:2142; CHECK:       # %bb.0: # %entry2143; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2144; CHECK-NEXT:    vmv2r.v v12, v82145; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2146; CHECK-NEXT:    vluxei16.v v8, (a0), v122147; CHECK-NEXT:    ret2148entry:2149  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i16(2150    <vscale x 8 x float> poison,2151    ptr %0,2152    <vscale x 8 x i16> %1,2153    iXLen %2)2154 2155  ret <vscale x 8 x float> %a2156}2157 2158define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i16(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2159; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i16:2160; CHECK:       # %bb.0: # %entry2161; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu2162; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t2163; CHECK-NEXT:    ret2164entry:2165  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i16(2166    <vscale x 8 x float> %0,2167    ptr %1,2168    <vscale x 8 x i16> %2,2169    <vscale x 8 x i1> %3,2170    iXLen %4, iXLen 1)2171 2172  ret <vscale x 8 x float> %a2173}2174 2175define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16(ptr %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {2176; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i16:2177; CHECK:       # %bb.0: # %entry2178; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2179; CHECK-NEXT:    vmv4r.v v16, v82180; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2181; CHECK-NEXT:    vluxei16.v v8, (a0), v162182; CHECK-NEXT:    ret2183entry:2184  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i16(2185    <vscale x 16 x float> poison,2186    ptr %0,2187    <vscale x 16 x i16> %1,2188    iXLen %2)2189 2190  ret <vscale x 16 x float> %a2191}2192 2193define <vscale x 16 x float> @intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i16(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2194; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i16:2195; CHECK:       # %bb.0: # %entry2196; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu2197; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t2198; CHECK-NEXT:    ret2199entry:2200  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i16(2201    <vscale x 16 x float> %0,2202    ptr %1,2203    <vscale x 16 x i16> %2,2204    <vscale x 16 x i1> %3,2205    iXLen %4, iXLen 1)2206 2207  ret <vscale x 16 x float> %a2208}2209 2210define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16(ptr %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {2211; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i16:2212; CHECK:       # %bb.0: # %entry2213; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2214; CHECK-NEXT:    vluxei16.v v9, (a0), v82215; CHECK-NEXT:    vmv.v.v v8, v92216; CHECK-NEXT:    ret2217entry:2218  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i16(2219    <vscale x 1 x double> poison,2220    ptr %0,2221    <vscale x 1 x i16> %1,2222    iXLen %2)2223 2224  ret <vscale x 1 x double> %a2225}2226 2227define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i16(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2228; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i16:2229; CHECK:       # %bb.0: # %entry2230; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu2231; CHECK-NEXT:    vluxei16.v v8, (a0), v9, v0.t2232; CHECK-NEXT:    ret2233entry:2234  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i16(2235    <vscale x 1 x double> %0,2236    ptr %1,2237    <vscale x 1 x i16> %2,2238    <vscale x 1 x i1> %3,2239    iXLen %4, iXLen 1)2240 2241  ret <vscale x 1 x double> %a2242}2243 2244define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16(ptr %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {2245; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i16:2246; CHECK:       # %bb.0: # %entry2247; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2248; CHECK-NEXT:    vmv1r.v v10, v82249; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma2250; CHECK-NEXT:    vluxei16.v v8, (a0), v102251; CHECK-NEXT:    ret2252entry:2253  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i16(2254    <vscale x 2 x double> poison,2255    ptr %0,2256    <vscale x 2 x i16> %1,2257    iXLen %2)2258 2259  ret <vscale x 2 x double> %a2260}2261 2262define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i16(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2263; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i16:2264; CHECK:       # %bb.0: # %entry2265; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu2266; CHECK-NEXT:    vluxei16.v v8, (a0), v10, v0.t2267; CHECK-NEXT:    ret2268entry:2269  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i16(2270    <vscale x 2 x double> %0,2271    ptr %1,2272    <vscale x 2 x i16> %2,2273    <vscale x 2 x i1> %3,2274    iXLen %4, iXLen 1)2275 2276  ret <vscale x 2 x double> %a2277}2278 2279define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16(ptr %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {2280; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i16:2281; CHECK:       # %bb.0: # %entry2282; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2283; CHECK-NEXT:    vmv1r.v v12, v82284; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma2285; CHECK-NEXT:    vluxei16.v v8, (a0), v122286; CHECK-NEXT:    ret2287entry:2288  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i16(2289    <vscale x 4 x double> poison,2290    ptr %0,2291    <vscale x 4 x i16> %1,2292    iXLen %2)2293 2294  ret <vscale x 4 x double> %a2295}2296 2297define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i16(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2298; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i16:2299; CHECK:       # %bb.0: # %entry2300; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu2301; CHECK-NEXT:    vluxei16.v v8, (a0), v12, v0.t2302; CHECK-NEXT:    ret2303entry:2304  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i16(2305    <vscale x 4 x double> %0,2306    ptr %1,2307    <vscale x 4 x i16> %2,2308    <vscale x 4 x i1> %3,2309    iXLen %4, iXLen 1)2310 2311  ret <vscale x 4 x double> %a2312}2313 2314define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16(ptr %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {2315; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i16:2316; CHECK:       # %bb.0: # %entry2317; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2318; CHECK-NEXT:    vmv2r.v v16, v82319; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma2320; CHECK-NEXT:    vluxei16.v v8, (a0), v162321; CHECK-NEXT:    ret2322entry:2323  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i16(2324    <vscale x 8 x double> poison,2325    ptr %0,2326    <vscale x 8 x i16> %1,2327    iXLen %2)2328 2329  ret <vscale x 8 x double> %a2330}2331 2332define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i16(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2333; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i16:2334; CHECK:       # %bb.0: # %entry2335; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu2336; CHECK-NEXT:    vluxei16.v v8, (a0), v16, v0.t2337; CHECK-NEXT:    ret2338entry:2339  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i16(2340    <vscale x 8 x double> %0,2341    ptr %1,2342    <vscale x 8 x i16> %2,2343    <vscale x 8 x i1> %3,2344    iXLen %4, iXLen 1)2345 2346  ret <vscale x 8 x double> %a2347}2348 2349define <vscale x 1 x i8> @intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2350; CHECK-LABEL: intrinsic_vluxei_v_nxv1i8_nxv1i8_nxv1i8:2351; CHECK:       # %bb.0: # %entry2352; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma2353; CHECK-NEXT:    vluxei8.v v8, (a0), v82354; CHECK-NEXT:    ret2355entry:2356  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.nxv1i8.nxv1i8(2357    <vscale x 1 x i8> poison,2358    ptr %0,2359    <vscale x 1 x i8> %1,2360    iXLen %2)2361 2362  ret <vscale x 1 x i8> %a2363}2364 2365define <vscale x 1 x i8> @intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2366; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i8_nxv1i8_nxv1i8:2367; CHECK:       # %bb.0: # %entry2368; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu2369; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2370; CHECK-NEXT:    ret2371entry:2372  %a = call <vscale x 1 x i8> @llvm.riscv.vluxei.mask.nxv1i8.nxv1i8(2373    <vscale x 1 x i8> %0,2374    ptr %1,2375    <vscale x 1 x i8> %2,2376    <vscale x 1 x i1> %3,2377    iXLen %4, iXLen 1)2378 2379  ret <vscale x 1 x i8> %a2380}2381 2382define <vscale x 2 x i8> @intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2383; CHECK-LABEL: intrinsic_vluxei_v_nxv2i8_nxv2i8_nxv2i8:2384; CHECK:       # %bb.0: # %entry2385; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma2386; CHECK-NEXT:    vluxei8.v v8, (a0), v82387; CHECK-NEXT:    ret2388entry:2389  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.nxv2i8.nxv2i8(2390    <vscale x 2 x i8> poison,2391    ptr %0,2392    <vscale x 2 x i8> %1,2393    iXLen %2)2394 2395  ret <vscale x 2 x i8> %a2396}2397 2398define <vscale x 2 x i8> @intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2399; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i8_nxv2i8_nxv2i8:2400; CHECK:       # %bb.0: # %entry2401; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu2402; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2403; CHECK-NEXT:    ret2404entry:2405  %a = call <vscale x 2 x i8> @llvm.riscv.vluxei.mask.nxv2i8.nxv2i8(2406    <vscale x 2 x i8> %0,2407    ptr %1,2408    <vscale x 2 x i8> %2,2409    <vscale x 2 x i1> %3,2410    iXLen %4, iXLen 1)2411 2412  ret <vscale x 2 x i8> %a2413}2414 2415define <vscale x 4 x i8> @intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2416; CHECK-LABEL: intrinsic_vluxei_v_nxv4i8_nxv4i8_nxv4i8:2417; CHECK:       # %bb.0: # %entry2418; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma2419; CHECK-NEXT:    vluxei8.v v8, (a0), v82420; CHECK-NEXT:    ret2421entry:2422  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.nxv4i8.nxv4i8(2423    <vscale x 4 x i8> poison,2424    ptr %0,2425    <vscale x 4 x i8> %1,2426    iXLen %2)2427 2428  ret <vscale x 4 x i8> %a2429}2430 2431define <vscale x 4 x i8> @intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2432; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i8_nxv4i8_nxv4i8:2433; CHECK:       # %bb.0: # %entry2434; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu2435; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2436; CHECK-NEXT:    ret2437entry:2438  %a = call <vscale x 4 x i8> @llvm.riscv.vluxei.mask.nxv4i8.nxv4i8(2439    <vscale x 4 x i8> %0,2440    ptr %1,2441    <vscale x 4 x i8> %2,2442    <vscale x 4 x i1> %3,2443    iXLen %4, iXLen 1)2444 2445  ret <vscale x 4 x i8> %a2446}2447 2448define <vscale x 8 x i8> @intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2449; CHECK-LABEL: intrinsic_vluxei_v_nxv8i8_nxv8i8_nxv8i8:2450; CHECK:       # %bb.0: # %entry2451; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma2452; CHECK-NEXT:    vluxei8.v v8, (a0), v82453; CHECK-NEXT:    ret2454entry:2455  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.nxv8i8.nxv8i8(2456    <vscale x 8 x i8> poison,2457    ptr %0,2458    <vscale x 8 x i8> %1,2459    iXLen %2)2460 2461  ret <vscale x 8 x i8> %a2462}2463 2464define <vscale x 8 x i8> @intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2465; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i8_nxv8i8_nxv8i8:2466; CHECK:       # %bb.0: # %entry2467; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu2468; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2469; CHECK-NEXT:    ret2470entry:2471  %a = call <vscale x 8 x i8> @llvm.riscv.vluxei.mask.nxv8i8.nxv8i8(2472    <vscale x 8 x i8> %0,2473    ptr %1,2474    <vscale x 8 x i8> %2,2475    <vscale x 8 x i1> %3,2476    iXLen %4, iXLen 1)2477 2478  ret <vscale x 8 x i8> %a2479}2480 2481define <vscale x 16 x i8> @intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2482; CHECK-LABEL: intrinsic_vluxei_v_nxv16i8_nxv16i8_nxv16i8:2483; CHECK:       # %bb.0: # %entry2484; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma2485; CHECK-NEXT:    vluxei8.v v8, (a0), v82486; CHECK-NEXT:    ret2487entry:2488  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.nxv16i8.nxv16i8(2489    <vscale x 16 x i8> poison,2490    ptr %0,2491    <vscale x 16 x i8> %1,2492    iXLen %2)2493 2494  ret <vscale x 16 x i8> %a2495}2496 2497define <vscale x 16 x i8> @intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2498; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i8_nxv16i8_nxv16i8:2499; CHECK:       # %bb.0: # %entry2500; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu2501; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t2502; CHECK-NEXT:    ret2503entry:2504  %a = call <vscale x 16 x i8> @llvm.riscv.vluxei.mask.nxv16i8.nxv16i8(2505    <vscale x 16 x i8> %0,2506    ptr %1,2507    <vscale x 16 x i8> %2,2508    <vscale x 16 x i1> %3,2509    iXLen %4, iXLen 1)2510 2511  ret <vscale x 16 x i8> %a2512}2513 2514define <vscale x 32 x i8> @intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {2515; CHECK-LABEL: intrinsic_vluxei_v_nxv32i8_nxv32i8_nxv32i8:2516; CHECK:       # %bb.0: # %entry2517; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma2518; CHECK-NEXT:    vluxei8.v v8, (a0), v82519; CHECK-NEXT:    ret2520entry:2521  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.nxv32i8.nxv32i8(2522    <vscale x 32 x i8> poison,2523    ptr %0,2524    <vscale x 32 x i8> %1,2525    iXLen %2)2526 2527  ret <vscale x 32 x i8> %a2528}2529 2530define <vscale x 32 x i8> @intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2531; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i8_nxv32i8_nxv32i8:2532; CHECK:       # %bb.0: # %entry2533; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu2534; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t2535; CHECK-NEXT:    ret2536entry:2537  %a = call <vscale x 32 x i8> @llvm.riscv.vluxei.mask.nxv32i8.nxv32i8(2538    <vscale x 32 x i8> %0,2539    ptr %1,2540    <vscale x 32 x i8> %2,2541    <vscale x 32 x i1> %3,2542    iXLen %4, iXLen 1)2543 2544  ret <vscale x 32 x i8> %a2545}2546 2547define <vscale x 64 x i8> @intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8(ptr %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {2548; CHECK-LABEL: intrinsic_vluxei_v_nxv64i8_nxv64i8_nxv64i8:2549; CHECK:       # %bb.0: # %entry2550; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma2551; CHECK-NEXT:    vluxei8.v v8, (a0), v82552; CHECK-NEXT:    ret2553entry:2554  %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.nxv64i8.nxv64i8(2555    <vscale x 64 x i8> poison,2556    ptr %0,2557    <vscale x 64 x i8> %1,2558    iXLen %2)2559 2560  ret <vscale x 64 x i8> %a2561}2562 2563define <vscale x 64 x i8> @intrinsic_vluxei_mask_v_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {2564; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv64i8_nxv64i8_nxv64i8:2565; CHECK:       # %bb.0: # %entry2566; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu2567; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t2568; CHECK-NEXT:    ret2569entry:2570  %a = call <vscale x 64 x i8> @llvm.riscv.vluxei.mask.nxv64i8.nxv64i8(2571    <vscale x 64 x i8> %0,2572    ptr %1,2573    <vscale x 64 x i8> %2,2574    <vscale x 64 x i1> %3,2575    iXLen %4, iXLen 1)2576 2577  ret <vscale x 64 x i8> %a2578}2579 2580define <vscale x 1 x i16> @intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2581; CHECK-LABEL: intrinsic_vluxei_v_nxv1i16_nxv1i16_nxv1i8:2582; CHECK:       # %bb.0: # %entry2583; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2584; CHECK-NEXT:    vluxei8.v v9, (a0), v82585; CHECK-NEXT:    vmv1r.v v8, v92586; CHECK-NEXT:    ret2587entry:2588  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.nxv1i16.nxv1i8(2589    <vscale x 1 x i16> poison,2590    ptr %0,2591    <vscale x 1 x i8> %1,2592    iXLen %2)2593 2594  ret <vscale x 1 x i16> %a2595}2596 2597define <vscale x 1 x i16> @intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2598; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i16_nxv1i16_nxv1i8:2599; CHECK:       # %bb.0: # %entry2600; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu2601; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2602; CHECK-NEXT:    ret2603entry:2604  %a = call <vscale x 1 x i16> @llvm.riscv.vluxei.mask.nxv1i16.nxv1i8(2605    <vscale x 1 x i16> %0,2606    ptr %1,2607    <vscale x 1 x i8> %2,2608    <vscale x 1 x i1> %3,2609    iXLen %4, iXLen 1)2610 2611  ret <vscale x 1 x i16> %a2612}2613 2614define <vscale x 2 x i16> @intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2615; CHECK-LABEL: intrinsic_vluxei_v_nxv2i16_nxv2i16_nxv2i8:2616; CHECK:       # %bb.0: # %entry2617; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2618; CHECK-NEXT:    vluxei8.v v9, (a0), v82619; CHECK-NEXT:    vmv1r.v v8, v92620; CHECK-NEXT:    ret2621entry:2622  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.nxv2i16.nxv2i8(2623    <vscale x 2 x i16> poison,2624    ptr %0,2625    <vscale x 2 x i8> %1,2626    iXLen %2)2627 2628  ret <vscale x 2 x i16> %a2629}2630 2631define <vscale x 2 x i16> @intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2632; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i16_nxv2i16_nxv2i8:2633; CHECK:       # %bb.0: # %entry2634; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu2635; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2636; CHECK-NEXT:    ret2637entry:2638  %a = call <vscale x 2 x i16> @llvm.riscv.vluxei.mask.nxv2i16.nxv2i8(2639    <vscale x 2 x i16> %0,2640    ptr %1,2641    <vscale x 2 x i8> %2,2642    <vscale x 2 x i1> %3,2643    iXLen %4, iXLen 1)2644 2645  ret <vscale x 2 x i16> %a2646}2647 2648define <vscale x 4 x i16> @intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2649; CHECK-LABEL: intrinsic_vluxei_v_nxv4i16_nxv4i16_nxv4i8:2650; CHECK:       # %bb.0: # %entry2651; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2652; CHECK-NEXT:    vluxei8.v v9, (a0), v82653; CHECK-NEXT:    vmv.v.v v8, v92654; CHECK-NEXT:    ret2655entry:2656  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.nxv4i16.nxv4i8(2657    <vscale x 4 x i16> poison,2658    ptr %0,2659    <vscale x 4 x i8> %1,2660    iXLen %2)2661 2662  ret <vscale x 4 x i16> %a2663}2664 2665define <vscale x 4 x i16> @intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2666; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i16_nxv4i16_nxv4i8:2667; CHECK:       # %bb.0: # %entry2668; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu2669; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2670; CHECK-NEXT:    ret2671entry:2672  %a = call <vscale x 4 x i16> @llvm.riscv.vluxei.mask.nxv4i16.nxv4i8(2673    <vscale x 4 x i16> %0,2674    ptr %1,2675    <vscale x 4 x i8> %2,2676    <vscale x 4 x i1> %3,2677    iXLen %4, iXLen 1)2678 2679  ret <vscale x 4 x i16> %a2680}2681 2682define <vscale x 8 x i16> @intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2683; CHECK-LABEL: intrinsic_vluxei_v_nxv8i16_nxv8i16_nxv8i8:2684; CHECK:       # %bb.0: # %entry2685; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2686; CHECK-NEXT:    vmv1r.v v10, v82687; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2688; CHECK-NEXT:    vluxei8.v v8, (a0), v102689; CHECK-NEXT:    ret2690entry:2691  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.nxv8i16.nxv8i8(2692    <vscale x 8 x i16> poison,2693    ptr %0,2694    <vscale x 8 x i8> %1,2695    iXLen %2)2696 2697  ret <vscale x 8 x i16> %a2698}2699 2700define <vscale x 8 x i16> @intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2701; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i16_nxv8i16_nxv8i8:2702; CHECK:       # %bb.0: # %entry2703; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu2704; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t2705; CHECK-NEXT:    ret2706entry:2707  %a = call <vscale x 8 x i16> @llvm.riscv.vluxei.mask.nxv8i16.nxv8i8(2708    <vscale x 8 x i16> %0,2709    ptr %1,2710    <vscale x 8 x i8> %2,2711    <vscale x 8 x i1> %3,2712    iXLen %4, iXLen 1)2713 2714  ret <vscale x 8 x i16> %a2715}2716 2717define <vscale x 16 x i16> @intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2718; CHECK-LABEL: intrinsic_vluxei_v_nxv16i16_nxv16i16_nxv16i8:2719; CHECK:       # %bb.0: # %entry2720; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2721; CHECK-NEXT:    vmv2r.v v12, v82722; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2723; CHECK-NEXT:    vluxei8.v v8, (a0), v122724; CHECK-NEXT:    ret2725entry:2726  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.nxv16i16.nxv16i8(2727    <vscale x 16 x i16> poison,2728    ptr %0,2729    <vscale x 16 x i8> %1,2730    iXLen %2)2731 2732  ret <vscale x 16 x i16> %a2733}2734 2735define <vscale x 16 x i16> @intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2736; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i16_nxv16i16_nxv16i8:2737; CHECK:       # %bb.0: # %entry2738; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu2739; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t2740; CHECK-NEXT:    ret2741entry:2742  %a = call <vscale x 16 x i16> @llvm.riscv.vluxei.mask.nxv16i16.nxv16i8(2743    <vscale x 16 x i16> %0,2744    ptr %1,2745    <vscale x 16 x i8> %2,2746    <vscale x 16 x i1> %3,2747    iXLen %4, iXLen 1)2748 2749  ret <vscale x 16 x i16> %a2750}2751 2752define <vscale x 32 x i16> @intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {2753; CHECK-LABEL: intrinsic_vluxei_v_nxv32i16_nxv32i16_nxv32i8:2754; CHECK:       # %bb.0: # %entry2755; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2756; CHECK-NEXT:    vmv4r.v v16, v82757; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2758; CHECK-NEXT:    vluxei8.v v8, (a0), v162759; CHECK-NEXT:    ret2760entry:2761  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.nxv32i16.nxv32i8(2762    <vscale x 32 x i16> poison,2763    ptr %0,2764    <vscale x 32 x i8> %1,2765    iXLen %2)2766 2767  ret <vscale x 32 x i16> %a2768}2769 2770define <vscale x 32 x i16> @intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2771; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32i16_nxv32i16_nxv32i8:2772; CHECK:       # %bb.0: # %entry2773; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu2774; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t2775; CHECK-NEXT:    ret2776entry:2777  %a = call <vscale x 32 x i16> @llvm.riscv.vluxei.mask.nxv32i16.nxv32i8(2778    <vscale x 32 x i16> %0,2779    ptr %1,2780    <vscale x 32 x i8> %2,2781    <vscale x 32 x i1> %3,2782    iXLen %4, iXLen 1)2783 2784  ret <vscale x 32 x i16> %a2785}2786 2787define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2788; CHECK-LABEL: intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i8:2789; CHECK:       # %bb.0: # %entry2790; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2791; CHECK-NEXT:    vluxei8.v v9, (a0), v82792; CHECK-NEXT:    vmv1r.v v8, v92793; CHECK-NEXT:    ret2794entry:2795  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i8(2796    <vscale x 1 x i32> poison,2797    ptr %0,2798    <vscale x 1 x i8> %1,2799    iXLen %2)2800 2801  ret <vscale x 1 x i32> %a2802}2803 2804define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i8(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2805; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i8:2806; CHECK:       # %bb.0: # %entry2807; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu2808; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2809; CHECK-NEXT:    ret2810entry:2811  %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i8(2812    <vscale x 1 x i32> %0,2813    ptr %1,2814    <vscale x 1 x i8> %2,2815    <vscale x 1 x i1> %3,2816    iXLen %4, iXLen 1)2817 2818  ret <vscale x 1 x i32> %a2819}2820 2821define <vscale x 2 x i32> @intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2822; CHECK-LABEL: intrinsic_vluxei_v_nxv2i32_nxv2i32_nxv2i8:2823; CHECK:       # %bb.0: # %entry2824; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2825; CHECK-NEXT:    vluxei8.v v9, (a0), v82826; CHECK-NEXT:    vmv.v.v v8, v92827; CHECK-NEXT:    ret2828entry:2829  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.nxv2i32.nxv2i8(2830    <vscale x 2 x i32> poison,2831    ptr %0,2832    <vscale x 2 x i8> %1,2833    iXLen %2)2834 2835  ret <vscale x 2 x i32> %a2836}2837 2838define <vscale x 2 x i32> @intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i8(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2839; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i32_nxv2i32_nxv2i8:2840; CHECK:       # %bb.0: # %entry2841; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu2842; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2843; CHECK-NEXT:    ret2844entry:2845  %a = call <vscale x 2 x i32> @llvm.riscv.vluxei.mask.nxv2i32.nxv2i8(2846    <vscale x 2 x i32> %0,2847    ptr %1,2848    <vscale x 2 x i8> %2,2849    <vscale x 2 x i1> %3,2850    iXLen %4, iXLen 1)2851 2852  ret <vscale x 2 x i32> %a2853}2854 2855define <vscale x 4 x i32> @intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {2856; CHECK-LABEL: intrinsic_vluxei_v_nxv4i32_nxv4i32_nxv4i8:2857; CHECK:       # %bb.0: # %entry2858; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2859; CHECK-NEXT:    vmv1r.v v10, v82860; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2861; CHECK-NEXT:    vluxei8.v v8, (a0), v102862; CHECK-NEXT:    ret2863entry:2864  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.nxv4i32.nxv4i8(2865    <vscale x 4 x i32> poison,2866    ptr %0,2867    <vscale x 4 x i8> %1,2868    iXLen %2)2869 2870  ret <vscale x 4 x i32> %a2871}2872 2873define <vscale x 4 x i32> @intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i8(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2874; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i32_nxv4i32_nxv4i8:2875; CHECK:       # %bb.0: # %entry2876; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu2877; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t2878; CHECK-NEXT:    ret2879entry:2880  %a = call <vscale x 4 x i32> @llvm.riscv.vluxei.mask.nxv4i32.nxv4i8(2881    <vscale x 4 x i32> %0,2882    ptr %1,2883    <vscale x 4 x i8> %2,2884    <vscale x 4 x i1> %3,2885    iXLen %4, iXLen 1)2886 2887  ret <vscale x 4 x i32> %a2888}2889 2890define <vscale x 8 x i32> @intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {2891; CHECK-LABEL: intrinsic_vluxei_v_nxv8i32_nxv8i32_nxv8i8:2892; CHECK:       # %bb.0: # %entry2893; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2894; CHECK-NEXT:    vmv1r.v v12, v82895; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2896; CHECK-NEXT:    vluxei8.v v8, (a0), v122897; CHECK-NEXT:    ret2898entry:2899  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.nxv8i32.nxv8i8(2900    <vscale x 8 x i32> poison,2901    ptr %0,2902    <vscale x 8 x i8> %1,2903    iXLen %2)2904 2905  ret <vscale x 8 x i32> %a2906}2907 2908define <vscale x 8 x i32> @intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i8(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2909; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i32_nxv8i32_nxv8i8:2910; CHECK:       # %bb.0: # %entry2911; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu2912; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t2913; CHECK-NEXT:    ret2914entry:2915  %a = call <vscale x 8 x i32> @llvm.riscv.vluxei.mask.nxv8i32.nxv8i8(2916    <vscale x 8 x i32> %0,2917    ptr %1,2918    <vscale x 8 x i8> %2,2919    <vscale x 8 x i1> %3,2920    iXLen %4, iXLen 1)2921 2922  ret <vscale x 8 x i32> %a2923}2924 2925define <vscale x 16 x i32> @intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {2926; CHECK-LABEL: intrinsic_vluxei_v_nxv16i32_nxv16i32_nxv16i8:2927; CHECK:       # %bb.0: # %entry2928; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2929; CHECK-NEXT:    vmv2r.v v16, v82930; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2931; CHECK-NEXT:    vluxei8.v v8, (a0), v162932; CHECK-NEXT:    ret2933entry:2934  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.nxv16i32.nxv16i8(2935    <vscale x 16 x i32> poison,2936    ptr %0,2937    <vscale x 16 x i8> %1,2938    iXLen %2)2939 2940  ret <vscale x 16 x i32> %a2941}2942 2943define <vscale x 16 x i32> @intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i8(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2944; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16i32_nxv16i32_nxv16i8:2945; CHECK:       # %bb.0: # %entry2946; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu2947; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t2948; CHECK-NEXT:    ret2949entry:2950  %a = call <vscale x 16 x i32> @llvm.riscv.vluxei.mask.nxv16i32.nxv16i8(2951    <vscale x 16 x i32> %0,2952    ptr %1,2953    <vscale x 16 x i8> %2,2954    <vscale x 16 x i1> %3,2955    iXLen %4, iXLen 1)2956 2957  ret <vscale x 16 x i32> %a2958}2959 2960define <vscale x 1 x i64> @intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {2961; CHECK-LABEL: intrinsic_vluxei_v_nxv1i64_nxv1i64_nxv1i8:2962; CHECK:       # %bb.0: # %entry2963; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2964; CHECK-NEXT:    vluxei8.v v9, (a0), v82965; CHECK-NEXT:    vmv.v.v v8, v92966; CHECK-NEXT:    ret2967entry:2968  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i8(2969    <vscale x 1 x i64> poison,2970    ptr %0,2971    <vscale x 1 x i8> %1,2972    iXLen %2)2973 2974  ret <vscale x 1 x i64> %a2975}2976 2977define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i8(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2978; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1i64_nxv1i64_nxv1i8:2979; CHECK:       # %bb.0: # %entry2980; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu2981; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t2982; CHECK-NEXT:    ret2983entry:2984  %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i8(2985    <vscale x 1 x i64> %0,2986    ptr %1,2987    <vscale x 1 x i8> %2,2988    <vscale x 1 x i1> %3,2989    iXLen %4, iXLen 1)2990 2991  ret <vscale x 1 x i64> %a2992}2993 2994define <vscale x 2 x i64> @intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {2995; CHECK-LABEL: intrinsic_vluxei_v_nxv2i64_nxv2i64_nxv2i8:2996; CHECK:       # %bb.0: # %entry2997; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma2998; CHECK-NEXT:    vmv1r.v v10, v82999; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma3000; CHECK-NEXT:    vluxei8.v v8, (a0), v103001; CHECK-NEXT:    ret3002entry:3003  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.nxv2i64.nxv2i8(3004    <vscale x 2 x i64> poison,3005    ptr %0,3006    <vscale x 2 x i8> %1,3007    iXLen %2)3008 3009  ret <vscale x 2 x i64> %a3010}3011 3012define <vscale x 2 x i64> @intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i8(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3013; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2i64_nxv2i64_nxv2i8:3014; CHECK:       # %bb.0: # %entry3015; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu3016; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3017; CHECK-NEXT:    ret3018entry:3019  %a = call <vscale x 2 x i64> @llvm.riscv.vluxei.mask.nxv2i64.nxv2i8(3020    <vscale x 2 x i64> %0,3021    ptr %1,3022    <vscale x 2 x i8> %2,3023    <vscale x 2 x i1> %3,3024    iXLen %4, iXLen 1)3025 3026  ret <vscale x 2 x i64> %a3027}3028 3029define <vscale x 4 x i64> @intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3030; CHECK-LABEL: intrinsic_vluxei_v_nxv4i64_nxv4i64_nxv4i8:3031; CHECK:       # %bb.0: # %entry3032; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3033; CHECK-NEXT:    vmv1r.v v12, v83034; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma3035; CHECK-NEXT:    vluxei8.v v8, (a0), v123036; CHECK-NEXT:    ret3037entry:3038  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.nxv4i64.nxv4i8(3039    <vscale x 4 x i64> poison,3040    ptr %0,3041    <vscale x 4 x i8> %1,3042    iXLen %2)3043 3044  ret <vscale x 4 x i64> %a3045}3046 3047define <vscale x 4 x i64> @intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i8(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3048; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4i64_nxv4i64_nxv4i8:3049; CHECK:       # %bb.0: # %entry3050; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu3051; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3052; CHECK-NEXT:    ret3053entry:3054  %a = call <vscale x 4 x i64> @llvm.riscv.vluxei.mask.nxv4i64.nxv4i8(3055    <vscale x 4 x i64> %0,3056    ptr %1,3057    <vscale x 4 x i8> %2,3058    <vscale x 4 x i1> %3,3059    iXLen %4, iXLen 1)3060 3061  ret <vscale x 4 x i64> %a3062}3063 3064define <vscale x 8 x i64> @intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3065; CHECK-LABEL: intrinsic_vluxei_v_nxv8i64_nxv8i64_nxv8i8:3066; CHECK:       # %bb.0: # %entry3067; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3068; CHECK-NEXT:    vmv1r.v v16, v83069; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma3070; CHECK-NEXT:    vluxei8.v v8, (a0), v163071; CHECK-NEXT:    ret3072entry:3073  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.nxv8i64.nxv8i8(3074    <vscale x 8 x i64> poison,3075    ptr %0,3076    <vscale x 8 x i8> %1,3077    iXLen %2)3078 3079  ret <vscale x 8 x i64> %a3080}3081 3082define <vscale x 8 x i64> @intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i8(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3083; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8i64_nxv8i64_nxv8i8:3084; CHECK:       # %bb.0: # %entry3085; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu3086; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3087; CHECK-NEXT:    ret3088entry:3089  %a = call <vscale x 8 x i64> @llvm.riscv.vluxei.mask.nxv8i64.nxv8i8(3090    <vscale x 8 x i64> %0,3091    ptr %1,3092    <vscale x 8 x i8> %2,3093    <vscale x 8 x i1> %3,3094    iXLen %4, iXLen 1)3095 3096  ret <vscale x 8 x i64> %a3097}3098 3099define <vscale x 1 x half> @intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3100; CHECK-LABEL: intrinsic_vluxei_v_nxv1f16_nxv1f16_nxv1i8:3101; CHECK:       # %bb.0: # %entry3102; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma3103; CHECK-NEXT:    vluxei8.v v9, (a0), v83104; CHECK-NEXT:    vmv1r.v v8, v93105; CHECK-NEXT:    ret3106entry:3107  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.nxv1f16.nxv1i8(3108    <vscale x 1 x half> poison,3109    ptr %0,3110    <vscale x 1 x i8> %1,3111    iXLen %2)3112 3113  ret <vscale x 1 x half> %a3114}3115 3116define <vscale x 1 x half> @intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i8(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3117; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f16_nxv1f16_nxv1i8:3118; CHECK:       # %bb.0: # %entry3119; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu3120; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3121; CHECK-NEXT:    ret3122entry:3123  %a = call <vscale x 1 x half> @llvm.riscv.vluxei.mask.nxv1f16.nxv1i8(3124    <vscale x 1 x half> %0,3125    ptr %1,3126    <vscale x 1 x i8> %2,3127    <vscale x 1 x i1> %3,3128    iXLen %4, iXLen 1)3129 3130  ret <vscale x 1 x half> %a3131}3132 3133define <vscale x 2 x half> @intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3134; CHECK-LABEL: intrinsic_vluxei_v_nxv2f16_nxv2f16_nxv2i8:3135; CHECK:       # %bb.0: # %entry3136; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma3137; CHECK-NEXT:    vluxei8.v v9, (a0), v83138; CHECK-NEXT:    vmv1r.v v8, v93139; CHECK-NEXT:    ret3140entry:3141  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.nxv2f16.nxv2i8(3142    <vscale x 2 x half> poison,3143    ptr %0,3144    <vscale x 2 x i8> %1,3145    iXLen %2)3146 3147  ret <vscale x 2 x half> %a3148}3149 3150define <vscale x 2 x half> @intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i8(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3151; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f16_nxv2f16_nxv2i8:3152; CHECK:       # %bb.0: # %entry3153; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu3154; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3155; CHECK-NEXT:    ret3156entry:3157  %a = call <vscale x 2 x half> @llvm.riscv.vluxei.mask.nxv2f16.nxv2i8(3158    <vscale x 2 x half> %0,3159    ptr %1,3160    <vscale x 2 x i8> %2,3161    <vscale x 2 x i1> %3,3162    iXLen %4, iXLen 1)3163 3164  ret <vscale x 2 x half> %a3165}3166 3167define <vscale x 4 x half> @intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3168; CHECK-LABEL: intrinsic_vluxei_v_nxv4f16_nxv4f16_nxv4i8:3169; CHECK:       # %bb.0: # %entry3170; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma3171; CHECK-NEXT:    vluxei8.v v9, (a0), v83172; CHECK-NEXT:    vmv.v.v v8, v93173; CHECK-NEXT:    ret3174entry:3175  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.nxv4f16.nxv4i8(3176    <vscale x 4 x half> poison,3177    ptr %0,3178    <vscale x 4 x i8> %1,3179    iXLen %2)3180 3181  ret <vscale x 4 x half> %a3182}3183 3184define <vscale x 4 x half> @intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i8(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3185; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f16_nxv4f16_nxv4i8:3186; CHECK:       # %bb.0: # %entry3187; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu3188; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3189; CHECK-NEXT:    ret3190entry:3191  %a = call <vscale x 4 x half> @llvm.riscv.vluxei.mask.nxv4f16.nxv4i8(3192    <vscale x 4 x half> %0,3193    ptr %1,3194    <vscale x 4 x i8> %2,3195    <vscale x 4 x i1> %3,3196    iXLen %4, iXLen 1)3197 3198  ret <vscale x 4 x half> %a3199}3200 3201define <vscale x 8 x half> @intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3202; CHECK-LABEL: intrinsic_vluxei_v_nxv8f16_nxv8f16_nxv8i8:3203; CHECK:       # %bb.0: # %entry3204; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3205; CHECK-NEXT:    vmv1r.v v10, v83206; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma3207; CHECK-NEXT:    vluxei8.v v8, (a0), v103208; CHECK-NEXT:    ret3209entry:3210  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.nxv8f16.nxv8i8(3211    <vscale x 8 x half> poison,3212    ptr %0,3213    <vscale x 8 x i8> %1,3214    iXLen %2)3215 3216  ret <vscale x 8 x half> %a3217}3218 3219define <vscale x 8 x half> @intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i8(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3220; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f16_nxv8f16_nxv8i8:3221; CHECK:       # %bb.0: # %entry3222; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu3223; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3224; CHECK-NEXT:    ret3225entry:3226  %a = call <vscale x 8 x half> @llvm.riscv.vluxei.mask.nxv8f16.nxv8i8(3227    <vscale x 8 x half> %0,3228    ptr %1,3229    <vscale x 8 x i8> %2,3230    <vscale x 8 x i1> %3,3231    iXLen %4, iXLen 1)3232 3233  ret <vscale x 8 x half> %a3234}3235 3236define <vscale x 16 x half> @intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {3237; CHECK-LABEL: intrinsic_vluxei_v_nxv16f16_nxv16f16_nxv16i8:3238; CHECK:       # %bb.0: # %entry3239; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3240; CHECK-NEXT:    vmv2r.v v12, v83241; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma3242; CHECK-NEXT:    vluxei8.v v8, (a0), v123243; CHECK-NEXT:    ret3244entry:3245  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.nxv16f16.nxv16i8(3246    <vscale x 16 x half> poison,3247    ptr %0,3248    <vscale x 16 x i8> %1,3249    iXLen %2)3250 3251  ret <vscale x 16 x half> %a3252}3253 3254define <vscale x 16 x half> @intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i8(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3255; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f16_nxv16f16_nxv16i8:3256; CHECK:       # %bb.0: # %entry3257; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu3258; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3259; CHECK-NEXT:    ret3260entry:3261  %a = call <vscale x 16 x half> @llvm.riscv.vluxei.mask.nxv16f16.nxv16i8(3262    <vscale x 16 x half> %0,3263    ptr %1,3264    <vscale x 16 x i8> %2,3265    <vscale x 16 x i1> %3,3266    iXLen %4, iXLen 1)3267 3268  ret <vscale x 16 x half> %a3269}3270 3271define <vscale x 32 x half> @intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8(ptr %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {3272; CHECK-LABEL: intrinsic_vluxei_v_nxv32f16_nxv32f16_nxv32i8:3273; CHECK:       # %bb.0: # %entry3274; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3275; CHECK-NEXT:    vmv4r.v v16, v83276; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma3277; CHECK-NEXT:    vluxei8.v v8, (a0), v163278; CHECK-NEXT:    ret3279entry:3280  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.nxv32f16.nxv32i8(3281    <vscale x 32 x half> poison,3282    ptr %0,3283    <vscale x 32 x i8> %1,3284    iXLen %2)3285 3286  ret <vscale x 32 x half> %a3287}3288 3289define <vscale x 32 x half> @intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i8(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {3290; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv32f16_nxv32f16_nxv32i8:3291; CHECK:       # %bb.0: # %entry3292; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu3293; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3294; CHECK-NEXT:    ret3295entry:3296  %a = call <vscale x 32 x half> @llvm.riscv.vluxei.mask.nxv32f16.nxv32i8(3297    <vscale x 32 x half> %0,3298    ptr %1,3299    <vscale x 32 x i8> %2,3300    <vscale x 32 x i1> %3,3301    iXLen %4, iXLen 1)3302 3303  ret <vscale x 32 x half> %a3304}3305 3306define <vscale x 1 x float> @intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3307; CHECK-LABEL: intrinsic_vluxei_v_nxv1f32_nxv1f32_nxv1i8:3308; CHECK:       # %bb.0: # %entry3309; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma3310; CHECK-NEXT:    vluxei8.v v9, (a0), v83311; CHECK-NEXT:    vmv1r.v v8, v93312; CHECK-NEXT:    ret3313entry:3314  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.nxv1f32.nxv1i8(3315    <vscale x 1 x float> poison,3316    ptr %0,3317    <vscale x 1 x i8> %1,3318    iXLen %2)3319 3320  ret <vscale x 1 x float> %a3321}3322 3323define <vscale x 1 x float> @intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i8(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3324; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f32_nxv1f32_nxv1i8:3325; CHECK:       # %bb.0: # %entry3326; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu3327; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3328; CHECK-NEXT:    ret3329entry:3330  %a = call <vscale x 1 x float> @llvm.riscv.vluxei.mask.nxv1f32.nxv1i8(3331    <vscale x 1 x float> %0,3332    ptr %1,3333    <vscale x 1 x i8> %2,3334    <vscale x 1 x i1> %3,3335    iXLen %4, iXLen 1)3336 3337  ret <vscale x 1 x float> %a3338}3339 3340define <vscale x 2 x float> @intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3341; CHECK-LABEL: intrinsic_vluxei_v_nxv2f32_nxv2f32_nxv2i8:3342; CHECK:       # %bb.0: # %entry3343; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma3344; CHECK-NEXT:    vluxei8.v v9, (a0), v83345; CHECK-NEXT:    vmv.v.v v8, v93346; CHECK-NEXT:    ret3347entry:3348  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.nxv2f32.nxv2i8(3349    <vscale x 2 x float> poison,3350    ptr %0,3351    <vscale x 2 x i8> %1,3352    iXLen %2)3353 3354  ret <vscale x 2 x float> %a3355}3356 3357define <vscale x 2 x float> @intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i8(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3358; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f32_nxv2f32_nxv2i8:3359; CHECK:       # %bb.0: # %entry3360; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu3361; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3362; CHECK-NEXT:    ret3363entry:3364  %a = call <vscale x 2 x float> @llvm.riscv.vluxei.mask.nxv2f32.nxv2i8(3365    <vscale x 2 x float> %0,3366    ptr %1,3367    <vscale x 2 x i8> %2,3368    <vscale x 2 x i1> %3,3369    iXLen %4, iXLen 1)3370 3371  ret <vscale x 2 x float> %a3372}3373 3374define <vscale x 4 x float> @intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3375; CHECK-LABEL: intrinsic_vluxei_v_nxv4f32_nxv4f32_nxv4i8:3376; CHECK:       # %bb.0: # %entry3377; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3378; CHECK-NEXT:    vmv1r.v v10, v83379; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma3380; CHECK-NEXT:    vluxei8.v v8, (a0), v103381; CHECK-NEXT:    ret3382entry:3383  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.nxv4f32.nxv4i8(3384    <vscale x 4 x float> poison,3385    ptr %0,3386    <vscale x 4 x i8> %1,3387    iXLen %2)3388 3389  ret <vscale x 4 x float> %a3390}3391 3392define <vscale x 4 x float> @intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i8(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3393; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f32_nxv4f32_nxv4i8:3394; CHECK:       # %bb.0: # %entry3395; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu3396; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3397; CHECK-NEXT:    ret3398entry:3399  %a = call <vscale x 4 x float> @llvm.riscv.vluxei.mask.nxv4f32.nxv4i8(3400    <vscale x 4 x float> %0,3401    ptr %1,3402    <vscale x 4 x i8> %2,3403    <vscale x 4 x i1> %3,3404    iXLen %4, iXLen 1)3405 3406  ret <vscale x 4 x float> %a3407}3408 3409define <vscale x 8 x float> @intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3410; CHECK-LABEL: intrinsic_vluxei_v_nxv8f32_nxv8f32_nxv8i8:3411; CHECK:       # %bb.0: # %entry3412; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3413; CHECK-NEXT:    vmv1r.v v12, v83414; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma3415; CHECK-NEXT:    vluxei8.v v8, (a0), v123416; CHECK-NEXT:    ret3417entry:3418  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.nxv8f32.nxv8i8(3419    <vscale x 8 x float> poison,3420    ptr %0,3421    <vscale x 8 x i8> %1,3422    iXLen %2)3423 3424  ret <vscale x 8 x float> %a3425}3426 3427define <vscale x 8 x float> @intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i8(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3428; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f32_nxv8f32_nxv8i8:3429; CHECK:       # %bb.0: # %entry3430; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu3431; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3432; CHECK-NEXT:    ret3433entry:3434  %a = call <vscale x 8 x float> @llvm.riscv.vluxei.mask.nxv8f32.nxv8i8(3435    <vscale x 8 x float> %0,3436    ptr %1,3437    <vscale x 8 x i8> %2,3438    <vscale x 8 x i1> %3,3439    iXLen %4, iXLen 1)3440 3441  ret <vscale x 8 x float> %a3442}3443 3444define <vscale x 16 x float> @intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8(ptr %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {3445; CHECK-LABEL: intrinsic_vluxei_v_nxv16f32_nxv16f32_nxv16i8:3446; CHECK:       # %bb.0: # %entry3447; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3448; CHECK-NEXT:    vmv2r.v v16, v83449; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma3450; CHECK-NEXT:    vluxei8.v v8, (a0), v163451; CHECK-NEXT:    ret3452entry:3453  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.nxv16f32.nxv16i8(3454    <vscale x 16 x float> poison,3455    ptr %0,3456    <vscale x 16 x i8> %1,3457    iXLen %2)3458 3459  ret <vscale x 16 x float> %a3460}3461 3462define <vscale x 16 x float> @intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i8(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3463; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv16f32_nxv16f32_nxv16i8:3464; CHECK:       # %bb.0: # %entry3465; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu3466; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3467; CHECK-NEXT:    ret3468entry:3469  %a = call <vscale x 16 x float> @llvm.riscv.vluxei.mask.nxv16f32.nxv16i8(3470    <vscale x 16 x float> %0,3471    ptr %1,3472    <vscale x 16 x i8> %2,3473    <vscale x 16 x i1> %3,3474    iXLen %4, iXLen 1)3475 3476  ret <vscale x 16 x float> %a3477}3478 3479define <vscale x 1 x double> @intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8(ptr %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {3480; CHECK-LABEL: intrinsic_vluxei_v_nxv1f64_nxv1f64_nxv1i8:3481; CHECK:       # %bb.0: # %entry3482; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma3483; CHECK-NEXT:    vluxei8.v v9, (a0), v83484; CHECK-NEXT:    vmv.v.v v8, v93485; CHECK-NEXT:    ret3486entry:3487  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.nxv1f64.nxv1i8(3488    <vscale x 1 x double> poison,3489    ptr %0,3490    <vscale x 1 x i8> %1,3491    iXLen %2)3492 3493  ret <vscale x 1 x double> %a3494}3495 3496define <vscale x 1 x double> @intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i8(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3497; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv1f64_nxv1f64_nxv1i8:3498; CHECK:       # %bb.0: # %entry3499; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu3500; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t3501; CHECK-NEXT:    ret3502entry:3503  %a = call <vscale x 1 x double> @llvm.riscv.vluxei.mask.nxv1f64.nxv1i8(3504    <vscale x 1 x double> %0,3505    ptr %1,3506    <vscale x 1 x i8> %2,3507    <vscale x 1 x i1> %3,3508    iXLen %4, iXLen 1)3509 3510  ret <vscale x 1 x double> %a3511}3512 3513define <vscale x 2 x double> @intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8(ptr %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {3514; CHECK-LABEL: intrinsic_vluxei_v_nxv2f64_nxv2f64_nxv2i8:3515; CHECK:       # %bb.0: # %entry3516; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3517; CHECK-NEXT:    vmv1r.v v10, v83518; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma3519; CHECK-NEXT:    vluxei8.v v8, (a0), v103520; CHECK-NEXT:    ret3521entry:3522  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.nxv2f64.nxv2i8(3523    <vscale x 2 x double> poison,3524    ptr %0,3525    <vscale x 2 x i8> %1,3526    iXLen %2)3527 3528  ret <vscale x 2 x double> %a3529}3530 3531define <vscale x 2 x double> @intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i8(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3532; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv2f64_nxv2f64_nxv2i8:3533; CHECK:       # %bb.0: # %entry3534; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu3535; CHECK-NEXT:    vluxei8.v v8, (a0), v10, v0.t3536; CHECK-NEXT:    ret3537entry:3538  %a = call <vscale x 2 x double> @llvm.riscv.vluxei.mask.nxv2f64.nxv2i8(3539    <vscale x 2 x double> %0,3540    ptr %1,3541    <vscale x 2 x i8> %2,3542    <vscale x 2 x i1> %3,3543    iXLen %4, iXLen 1)3544 3545  ret <vscale x 2 x double> %a3546}3547 3548define <vscale x 4 x double> @intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8(ptr %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {3549; CHECK-LABEL: intrinsic_vluxei_v_nxv4f64_nxv4f64_nxv4i8:3550; CHECK:       # %bb.0: # %entry3551; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3552; CHECK-NEXT:    vmv1r.v v12, v83553; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma3554; CHECK-NEXT:    vluxei8.v v8, (a0), v123555; CHECK-NEXT:    ret3556entry:3557  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.nxv4f64.nxv4i8(3558    <vscale x 4 x double> poison,3559    ptr %0,3560    <vscale x 4 x i8> %1,3561    iXLen %2)3562 3563  ret <vscale x 4 x double> %a3564}3565 3566define <vscale x 4 x double> @intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i8(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3567; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv4f64_nxv4f64_nxv4i8:3568; CHECK:       # %bb.0: # %entry3569; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu3570; CHECK-NEXT:    vluxei8.v v8, (a0), v12, v0.t3571; CHECK-NEXT:    ret3572entry:3573  %a = call <vscale x 4 x double> @llvm.riscv.vluxei.mask.nxv4f64.nxv4i8(3574    <vscale x 4 x double> %0,3575    ptr %1,3576    <vscale x 4 x i8> %2,3577    <vscale x 4 x i1> %3,3578    iXLen %4, iXLen 1)3579 3580  ret <vscale x 4 x double> %a3581}3582 3583define <vscale x 8 x double> @intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8(ptr %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {3584; CHECK-LABEL: intrinsic_vluxei_v_nxv8f64_nxv8f64_nxv8i8:3585; CHECK:       # %bb.0: # %entry3586; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma3587; CHECK-NEXT:    vmv1r.v v16, v83588; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma3589; CHECK-NEXT:    vluxei8.v v8, (a0), v163590; CHECK-NEXT:    ret3591entry:3592  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.nxv8f64.nxv8i8(3593    <vscale x 8 x double> poison,3594    ptr %0,3595    <vscale x 8 x i8> %1,3596    iXLen %2)3597 3598  ret <vscale x 8 x double> %a3599}3600 3601define <vscale x 8 x double> @intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i8(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3602; CHECK-LABEL: intrinsic_vluxei_mask_v_nxv8f64_nxv8f64_nxv8i8:3603; CHECK:       # %bb.0: # %entry3604; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu3605; CHECK-NEXT:    vluxei8.v v8, (a0), v16, v0.t3606; CHECK-NEXT:    ret3607entry:3608  %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8(3609    <vscale x 8 x double> %0,3610    ptr %1,3611    <vscale x 8 x i8> %2,3612    <vscale x 8 x i1> %3,3613    iXLen %4, iXLen 1)3614 3615  ret <vscale x 8 x double> %a3616}3617