157 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s --check-prefix=RV32I3; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s --check-prefix=RV64I4 5define i8 @scmp.8.8(i8 signext %x, i8 signext %y) nounwind {6; RV32I-LABEL: scmp.8.8:7; RV32I: # %bb.0:8; RV32I-NEXT: slt a2, a1, a09; RV32I-NEXT: slt a0, a0, a110; RV32I-NEXT: sub a0, a2, a011; RV32I-NEXT: ret12;13; RV64I-LABEL: scmp.8.8:14; RV64I: # %bb.0:15; RV64I-NEXT: slt a2, a1, a016; RV64I-NEXT: slt a0, a0, a117; RV64I-NEXT: sub a0, a2, a018; RV64I-NEXT: ret19 %1 = call i8 @llvm.scmp(i8 %x, i8 %y)20 ret i8 %121}22 23define i8 @scmp.8.16(i16 signext %x, i16 signext %y) nounwind {24; RV32I-LABEL: scmp.8.16:25; RV32I: # %bb.0:26; RV32I-NEXT: slt a2, a1, a027; RV32I-NEXT: slt a0, a0, a128; RV32I-NEXT: sub a0, a2, a029; RV32I-NEXT: ret30;31; RV64I-LABEL: scmp.8.16:32; RV64I: # %bb.0:33; RV64I-NEXT: slt a2, a1, a034; RV64I-NEXT: slt a0, a0, a135; RV64I-NEXT: sub a0, a2, a036; RV64I-NEXT: ret37 %1 = call i8 @llvm.scmp(i16 %x, i16 %y)38 ret i8 %139}40 41define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {42; RV32I-LABEL: scmp.8.32:43; RV32I: # %bb.0:44; RV32I-NEXT: slt a2, a1, a045; RV32I-NEXT: slt a0, a0, a146; RV32I-NEXT: sub a0, a2, a047; RV32I-NEXT: ret48;49; RV64I-LABEL: scmp.8.32:50; RV64I: # %bb.0:51; RV64I-NEXT: sext.w a0, a052; RV64I-NEXT: sext.w a1, a153; RV64I-NEXT: slt a2, a1, a054; RV64I-NEXT: slt a0, a0, a155; RV64I-NEXT: sub a0, a2, a056; RV64I-NEXT: ret57 %1 = call i8 @llvm.scmp(i32 %x, i32 %y)58 ret i8 %159}60 61define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {62; RV32I-LABEL: scmp.8.64:63; RV32I: # %bb.0:64; RV32I-NEXT: beq a1, a3, .LBB3_265; RV32I-NEXT: # %bb.1:66; RV32I-NEXT: slt a4, a3, a167; RV32I-NEXT: slt a0, a1, a368; RV32I-NEXT: sub a0, a4, a069; RV32I-NEXT: ret70; RV32I-NEXT: .LBB3_2:71; RV32I-NEXT: sltu a4, a2, a072; RV32I-NEXT: sltu a0, a0, a273; RV32I-NEXT: sub a0, a4, a074; RV32I-NEXT: ret75;76; RV64I-LABEL: scmp.8.64:77; RV64I: # %bb.0:78; RV64I-NEXT: slt a2, a1, a079; RV64I-NEXT: slt a0, a0, a180; RV64I-NEXT: sub a0, a2, a081; RV64I-NEXT: ret82 %1 = call i8 @llvm.scmp(i64 %x, i64 %y)83 ret i8 %184}85 86define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {87; RV32I-LABEL: scmp.32.32:88; RV32I: # %bb.0:89; RV32I-NEXT: slt a2, a1, a090; RV32I-NEXT: slt a0, a0, a191; RV32I-NEXT: sub a0, a2, a092; RV32I-NEXT: ret93;94; RV64I-LABEL: scmp.32.32:95; RV64I: # %bb.0:96; RV64I-NEXT: sext.w a0, a097; RV64I-NEXT: sext.w a1, a198; RV64I-NEXT: slt a2, a1, a099; RV64I-NEXT: slt a0, a0, a1100; RV64I-NEXT: subw a0, a2, a0101; RV64I-NEXT: ret102 %1 = call i32 @llvm.scmp(i32 %x, i32 %y)103 ret i32 %1104}105 106define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {107; RV32I-LABEL: scmp.32.64:108; RV32I: # %bb.0:109; RV32I-NEXT: beq a1, a3, .LBB5_2110; RV32I-NEXT: # %bb.1:111; RV32I-NEXT: slt a4, a3, a1112; RV32I-NEXT: slt a0, a1, a3113; RV32I-NEXT: sub a0, a4, a0114; RV32I-NEXT: ret115; RV32I-NEXT: .LBB5_2:116; RV32I-NEXT: sltu a4, a2, a0117; RV32I-NEXT: sltu a0, a0, a2118; RV32I-NEXT: sub a0, a4, a0119; RV32I-NEXT: ret120;121; RV64I-LABEL: scmp.32.64:122; RV64I: # %bb.0:123; RV64I-NEXT: slt a2, a1, a0124; RV64I-NEXT: slt a0, a0, a1125; RV64I-NEXT: subw a0, a2, a0126; RV64I-NEXT: ret127 %1 = call i32 @llvm.scmp(i64 %x, i64 %y)128 ret i32 %1129}130 131define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {132; RV32I-LABEL: scmp.64.64:133; RV32I: # %bb.0:134; RV32I-NEXT: beq a1, a3, .LBB6_2135; RV32I-NEXT: # %bb.1:136; RV32I-NEXT: slt a4, a3, a1137; RV32I-NEXT: slt a1, a1, a3138; RV32I-NEXT: j .LBB6_3139; RV32I-NEXT: .LBB6_2:140; RV32I-NEXT: sltu a4, a2, a0141; RV32I-NEXT: sltu a1, a0, a2142; RV32I-NEXT: .LBB6_3:143; RV32I-NEXT: sub a0, a4, a1144; RV32I-NEXT: sltu a1, a4, a1145; RV32I-NEXT: neg a1, a1146; RV32I-NEXT: ret147;148; RV64I-LABEL: scmp.64.64:149; RV64I: # %bb.0:150; RV64I-NEXT: slt a2, a1, a0151; RV64I-NEXT: slt a0, a0, a1152; RV64I-NEXT: sub a0, a2, a0153; RV64I-NEXT: ret154 %1 = call i64 @llvm.scmp(i64 %x, i64 %y)155 ret i64 %1156}157