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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=riscv32 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV323; RUN: llc -mtriple=riscv64 -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=RV644 5define i16 @test_lshr_i48(i48 %x) {6; RV32-LABEL: test_lshr_i48:7; RV32: # %bb.0:8; RV32-NEXT: srli a0, a0, 169; RV32-NEXT: ret10;11; RV64-LABEL: test_lshr_i48:12; RV64: # %bb.0:13; RV64-NEXT: srliw a0, a0, 1614; RV64-NEXT: ret15 %lshr = lshr i48 %x, 1616 %trunc = trunc i48 %lshr to i1617 ret i16 %trunc18}19 20define i16 @test_ashr_i48(i48 %x) {21; RV32-LABEL: test_ashr_i48:22; RV32: # %bb.0:23; RV32-NEXT: srai a0, a0, 1624; RV32-NEXT: ret25;26; RV64-LABEL: test_ashr_i48:27; RV64: # %bb.0:28; RV64-NEXT: sraiw a0, a0, 1629; RV64-NEXT: ret30 %ashr = ashr i48 %x, 1631 %trunc = trunc i48 %ashr to i1632 ret i16 %trunc33}34 35define i16 @test_shl_i48(i48 %x) {36; RV32-LABEL: test_shl_i48:37; RV32: # %bb.0:38; RV32-NEXT: slli a0, a0, 839; RV32-NEXT: ret40;41; RV64-LABEL: test_shl_i48:42; RV64: # %bb.0:43; RV64-NEXT: slli a0, a0, 844; RV64-NEXT: ret45 %shl = shl i48 %x, 846 %trunc = trunc i48 %shl to i1647 ret i16 %trunc48}49 50; FIXME: Could use srlw to remove slli+srli.51define i16 @test_lshr_i48_2(i48 %x, i48 %y) {52; RV32-LABEL: test_lshr_i48_2:53; RV32: # %bb.0:54; RV32-NEXT: andi a2, a2, 1555; RV32-NEXT: srl a0, a0, a256; RV32-NEXT: ret57;58; RV64-LABEL: test_lshr_i48_2:59; RV64: # %bb.0:60; RV64-NEXT: andi a1, a1, 1561; RV64-NEXT: slli a0, a0, 3262; RV64-NEXT: srli a0, a0, 3263; RV64-NEXT: srl a0, a0, a164; RV64-NEXT: ret65 %and = and i48 %y, 1566 %lshr = lshr i48 %x, %and67 %trunc = trunc i48 %lshr to i1668 ret i16 %trunc69}70 71; FIXME: Could use sraw to remove the sext.w.72define i16 @test_ashr_i48_2(i48 %x, i48 %y) {73; RV32-LABEL: test_ashr_i48_2:74; RV32: # %bb.0:75; RV32-NEXT: andi a2, a2, 1576; RV32-NEXT: sra a0, a0, a277; RV32-NEXT: ret78;79; RV64-LABEL: test_ashr_i48_2:80; RV64: # %bb.0:81; RV64-NEXT: andi a1, a1, 1582; RV64-NEXT: sext.w a0, a083; RV64-NEXT: sra a0, a0, a184; RV64-NEXT: ret85 %and = and i48 %y, 1586 %ashr = ashr i48 %x, %and87 %trunc = trunc i48 %ashr to i1688 ret i16 %trunc89}90 91define i16 @test_shl_i48_2(i48 %x, i48 %y) {92; RV32-LABEL: test_shl_i48_2:93; RV32: # %bb.0:94; RV32-NEXT: andi a2, a2, 1595; RV32-NEXT: sll a0, a0, a296; RV32-NEXT: ret97;98; RV64-LABEL: test_shl_i48_2:99; RV64: # %bb.0:100; RV64-NEXT: andi a1, a1, 15101; RV64-NEXT: sll a0, a0, a1102; RV64-NEXT: ret103 %and = and i48 %y, 15104 %shl = shl i48 %x, %and105 %trunc = trunc i48 %shl to i16106 ret i16 %trunc107}108 109define i32 @test_fshl_i32(i32 %x, i32 %_, i32 %y) {110; RV32-LABEL: test_fshl_i32:111; RV32: # %bb.0:112; RV32-NEXT: not a3, a2113; RV32-NEXT: sll a0, a0, a2114; RV32-NEXT: srli a1, a1, 1115; RV32-NEXT: srl a1, a1, a3116; RV32-NEXT: or a0, a0, a1117; RV32-NEXT: ret118;119; RV64-LABEL: test_fshl_i32:120; RV64: # %bb.0:121; RV64-NEXT: not a3, a2122; RV64-NEXT: sllw a0, a0, a2123; RV64-NEXT: srliw a1, a1, 1124; RV64-NEXT: srlw a1, a1, a3125; RV64-NEXT: or a0, a0, a1126; RV64-NEXT: ret127 %fshl = call i32 @llvm.fshl.i32(i32 %x, i32 %_, i32 %y)128 %shl = shl i32 %x, %y129 %or = or i32 %fshl, %shl130 ret i32 %or131}132 133define i32 @test_fshr_i32(i32 %_, i32 %x, i32 %y) {134; RV32-LABEL: test_fshr_i32:135; RV32: # %bb.0:136; RV32-NEXT: not a3, a2137; RV32-NEXT: slli a0, a0, 1138; RV32-NEXT: sll a0, a0, a3139; RV32-NEXT: srl a1, a1, a2140; RV32-NEXT: or a0, a0, a1141; RV32-NEXT: ret142;143; RV64-LABEL: test_fshr_i32:144; RV64: # %bb.0:145; RV64-NEXT: not a3, a2146; RV64-NEXT: slli a0, a0, 1147; RV64-NEXT: sllw a0, a0, a3148; RV64-NEXT: srlw a1, a1, a2149; RV64-NEXT: or a0, a0, a1150; RV64-NEXT: ret151 %fshr = call i32 @llvm.fshr.i32(i32 %_, i32 %x, i32 %y)152 %lshr = lshr i32 %x, %y153 %or = or i32 %lshr, %fshr154 ret i32 %or155}156