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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -verify-machineinstrs -global-isel < %s \3; RUN: | FileCheck %s -check-prefix=RV32I4; RUN: llc -mtriple=riscv64 -verify-machineinstrs -global-isel < %s \5; RUN: | FileCheck %s -check-prefix=RV64I6 7; Basic shift support is tested as part of ALU.ll. This file ensures that8; shifts which may not be supported natively are lowered properly.9 10define i64 @lshr64(i64 %a, i64 %b) nounwind {11; RV32I-LABEL: lshr64:12; RV32I: # %bb.0:13; RV32I-NEXT: li a3, 3214; RV32I-NEXT: bltu a2, a3, .LBB0_215; RV32I-NEXT: # %bb.1:16; RV32I-NEXT: srl a4, a1, a217; RV32I-NEXT: bnez a2, .LBB0_318; RV32I-NEXT: j .LBB0_419; RV32I-NEXT: .LBB0_2:20; RV32I-NEXT: srl a4, a0, a221; RV32I-NEXT: neg a5, a222; RV32I-NEXT: sll a5, a1, a523; RV32I-NEXT: or a4, a4, a524; RV32I-NEXT: beqz a2, .LBB0_425; RV32I-NEXT: .LBB0_3:26; RV32I-NEXT: mv a0, a427; RV32I-NEXT: .LBB0_4:28; RV32I-NEXT: bltu a2, a3, .LBB0_629; RV32I-NEXT: # %bb.5:30; RV32I-NEXT: li a1, 031; RV32I-NEXT: ret32; RV32I-NEXT: .LBB0_6:33; RV32I-NEXT: srl a1, a1, a234; RV32I-NEXT: ret35;36; RV64I-LABEL: lshr64:37; RV64I: # %bb.0:38; RV64I-NEXT: srl a0, a0, a139; RV64I-NEXT: ret40 %1 = lshr i64 %a, %b41 ret i64 %142}43 44define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {45; RV32I-LABEL: lshr64_minsize:46; RV32I: # %bb.0:47; RV32I-NEXT: li a3, 3248; RV32I-NEXT: bltu a2, a3, .LBB1_249; RV32I-NEXT: # %bb.1:50; RV32I-NEXT: srl a4, a1, a251; RV32I-NEXT: bnez a2, .LBB1_352; RV32I-NEXT: j .LBB1_453; RV32I-NEXT: .LBB1_2:54; RV32I-NEXT: srl a4, a0, a255; RV32I-NEXT: neg a5, a256; RV32I-NEXT: sll a5, a1, a557; RV32I-NEXT: or a4, a4, a558; RV32I-NEXT: beqz a2, .LBB1_459; RV32I-NEXT: .LBB1_3:60; RV32I-NEXT: mv a0, a461; RV32I-NEXT: .LBB1_4:62; RV32I-NEXT: bltu a2, a3, .LBB1_663; RV32I-NEXT: # %bb.5:64; RV32I-NEXT: li a1, 065; RV32I-NEXT: ret66; RV32I-NEXT: .LBB1_6:67; RV32I-NEXT: srl a1, a1, a268; RV32I-NEXT: ret69;70; RV64I-LABEL: lshr64_minsize:71; RV64I: # %bb.0:72; RV64I-NEXT: srl a0, a0, a173; RV64I-NEXT: ret74 %1 = lshr i64 %a, %b75 ret i64 %176}77 78define i64 @ashr64(i64 %a, i64 %b) nounwind {79; RV32I-LABEL: ashr64:80; RV32I: # %bb.0:81; RV32I-NEXT: li a3, 3282; RV32I-NEXT: bltu a2, a3, .LBB2_283; RV32I-NEXT: # %bb.1:84; RV32I-NEXT: sra a4, a1, a285; RV32I-NEXT: bnez a2, .LBB2_386; RV32I-NEXT: j .LBB2_487; RV32I-NEXT: .LBB2_2:88; RV32I-NEXT: srl a4, a0, a289; RV32I-NEXT: neg a5, a290; RV32I-NEXT: sll a5, a1, a591; RV32I-NEXT: or a4, a4, a592; RV32I-NEXT: beqz a2, .LBB2_493; RV32I-NEXT: .LBB2_3:94; RV32I-NEXT: mv a0, a495; RV32I-NEXT: .LBB2_4:96; RV32I-NEXT: bltu a2, a3, .LBB2_697; RV32I-NEXT: # %bb.5:98; RV32I-NEXT: srai a1, a1, 3199; RV32I-NEXT: ret100; RV32I-NEXT: .LBB2_6:101; RV32I-NEXT: sra a1, a1, a2102; RV32I-NEXT: ret103;104; RV64I-LABEL: ashr64:105; RV64I: # %bb.0:106; RV64I-NEXT: sra a0, a0, a1107; RV64I-NEXT: ret108 %1 = ashr i64 %a, %b109 ret i64 %1110}111 112define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {113; RV32I-LABEL: ashr64_minsize:114; RV32I: # %bb.0:115; RV32I-NEXT: li a3, 32116; RV32I-NEXT: bltu a2, a3, .LBB3_2117; RV32I-NEXT: # %bb.1:118; RV32I-NEXT: sra a4, a1, a2119; RV32I-NEXT: bnez a2, .LBB3_3120; RV32I-NEXT: j .LBB3_4121; RV32I-NEXT: .LBB3_2:122; RV32I-NEXT: srl a4, a0, a2123; RV32I-NEXT: neg a5, a2124; RV32I-NEXT: sll a5, a1, a5125; RV32I-NEXT: or a4, a4, a5126; RV32I-NEXT: beqz a2, .LBB3_4127; RV32I-NEXT: .LBB3_3:128; RV32I-NEXT: mv a0, a4129; RV32I-NEXT: .LBB3_4:130; RV32I-NEXT: bltu a2, a3, .LBB3_6131; RV32I-NEXT: # %bb.5:132; RV32I-NEXT: srai a1, a1, 31133; RV32I-NEXT: ret134; RV32I-NEXT: .LBB3_6:135; RV32I-NEXT: sra a1, a1, a2136; RV32I-NEXT: ret137;138; RV64I-LABEL: ashr64_minsize:139; RV64I: # %bb.0:140; RV64I-NEXT: sra a0, a0, a1141; RV64I-NEXT: ret142 %1 = ashr i64 %a, %b143 ret i64 %1144}145 146define i64 @shl64(i64 %a, i64 %b) nounwind {147; RV32I-LABEL: shl64:148; RV32I: # %bb.0:149; RV32I-NEXT: mv a3, a0150; RV32I-NEXT: li a0, 32151; RV32I-NEXT: bltu a2, a0, .LBB4_2152; RV32I-NEXT: # %bb.1:153; RV32I-NEXT: li a0, 0154; RV32I-NEXT: sll a3, a3, a2155; RV32I-NEXT: bnez a2, .LBB4_3156; RV32I-NEXT: j .LBB4_4157; RV32I-NEXT: .LBB4_2:158; RV32I-NEXT: sll a0, a3, a2159; RV32I-NEXT: neg a4, a2160; RV32I-NEXT: srl a3, a3, a4161; RV32I-NEXT: sll a4, a1, a2162; RV32I-NEXT: or a3, a3, a4163; RV32I-NEXT: beqz a2, .LBB4_4164; RV32I-NEXT: .LBB4_3:165; RV32I-NEXT: mv a1, a3166; RV32I-NEXT: .LBB4_4:167; RV32I-NEXT: ret168;169; RV64I-LABEL: shl64:170; RV64I: # %bb.0:171; RV64I-NEXT: sll a0, a0, a1172; RV64I-NEXT: ret173 %1 = shl i64 %a, %b174 ret i64 %1175}176 177define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {178; RV32I-LABEL: shl64_minsize:179; RV32I: # %bb.0:180; RV32I-NEXT: mv a3, a0181; RV32I-NEXT: li a0, 32182; RV32I-NEXT: bltu a2, a0, .LBB5_2183; RV32I-NEXT: # %bb.1:184; RV32I-NEXT: li a0, 0185; RV32I-NEXT: sll a3, a3, a2186; RV32I-NEXT: bnez a2, .LBB5_3187; RV32I-NEXT: j .LBB5_4188; RV32I-NEXT: .LBB5_2:189; RV32I-NEXT: sll a0, a3, a2190; RV32I-NEXT: neg a4, a2191; RV32I-NEXT: srl a3, a3, a4192; RV32I-NEXT: sll a4, a1, a2193; RV32I-NEXT: or a3, a3, a4194; RV32I-NEXT: beqz a2, .LBB5_4195; RV32I-NEXT: .LBB5_3:196; RV32I-NEXT: mv a1, a3197; RV32I-NEXT: .LBB5_4:198; RV32I-NEXT: ret199;200; RV64I-LABEL: shl64_minsize:201; RV64I: # %bb.0:202; RV64I-NEXT: sll a0, a0, a1203; RV64I-NEXT: ret204 %1 = shl i64 %a, %b205 ret i64 %1206}207 208define i128 @lshr128(i128 %a, i128 %b) nounwind {209; RV32I-LABEL: lshr128:210; RV32I: # %bb.0:211; RV32I-NEXT: lw a2, 0(a2)212; RV32I-NEXT: lw a3, 8(a1)213; RV32I-NEXT: lw a7, 12(a1)214; RV32I-NEXT: li t0, 32215; RV32I-NEXT: srl t2, a3, a2216; RV32I-NEXT: neg t6, a2217; RV32I-NEXT: sll t5, a7, t6218; RV32I-NEXT: bltu a2, t0, .LBB6_2219; RV32I-NEXT: # %bb.1:220; RV32I-NEXT: srl a5, a7, a2221; RV32I-NEXT: mv a4, a3222; RV32I-NEXT: bnez a2, .LBB6_3223; RV32I-NEXT: j .LBB6_4224; RV32I-NEXT: .LBB6_2:225; RV32I-NEXT: or a5, t2, t5226; RV32I-NEXT: mv a4, a3227; RV32I-NEXT: beqz a2, .LBB6_4228; RV32I-NEXT: .LBB6_3:229; RV32I-NEXT: mv a4, a5230; RV32I-NEXT: .LBB6_4:231; RV32I-NEXT: lw a5, 0(a1)232; RV32I-NEXT: lw a1, 4(a1)233; RV32I-NEXT: bltu a2, t0, .LBB6_6234; RV32I-NEXT: # %bb.5:235; RV32I-NEXT: li a6, 0236; RV32I-NEXT: srl t4, a1, a2237; RV32I-NEXT: j .LBB6_7238; RV32I-NEXT: .LBB6_6:239; RV32I-NEXT: srl a6, a7, a2240; RV32I-NEXT: srl t1, a5, a2241; RV32I-NEXT: sll t3, a1, t6242; RV32I-NEXT: or t4, t1, t3243; RV32I-NEXT: .LBB6_7:244; RV32I-NEXT: li t1, 64245; RV32I-NEXT: mv t3, a5246; RV32I-NEXT: beqz a2, .LBB6_9247; RV32I-NEXT: # %bb.8:248; RV32I-NEXT: mv t3, t4249; RV32I-NEXT: .LBB6_9:250; RV32I-NEXT: addi sp, sp, -16251; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill252; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill253; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill254; RV32I-NEXT: sub s0, t1, a2255; RV32I-NEXT: bltu a2, t0, .LBB6_12256; RV32I-NEXT: # %bb.10:257; RV32I-NEXT: li t4, 0258; RV32I-NEXT: bgeu s0, t0, .LBB6_13259; RV32I-NEXT: .LBB6_11:260; RV32I-NEXT: sll t6, a3, t6261; RV32I-NEXT: neg s1, s0262; RV32I-NEXT: srl s1, a3, s1263; RV32I-NEXT: or s2, s1, t5264; RV32I-NEXT: j .LBB6_14265; RV32I-NEXT: .LBB6_12:266; RV32I-NEXT: srl t4, a1, a2267; RV32I-NEXT: bltu s0, t0, .LBB6_11268; RV32I-NEXT: .LBB6_13:269; RV32I-NEXT: li t6, 0270; RV32I-NEXT: sll s2, a3, s0271; RV32I-NEXT: .LBB6_14:272; RV32I-NEXT: addi s1, a2, -64273; RV32I-NEXT: mv t5, a7274; RV32I-NEXT: beqz s0, .LBB6_16275; RV32I-NEXT: # %bb.15:276; RV32I-NEXT: mv t5, s2277; RV32I-NEXT: .LBB6_16:278; RV32I-NEXT: bltu s1, t0, .LBB6_18279; RV32I-NEXT: # %bb.17:280; RV32I-NEXT: srl t2, a7, s1281; RV32I-NEXT: bnez s1, .LBB6_19282; RV32I-NEXT: j .LBB6_20283; RV32I-NEXT: .LBB6_18:284; RV32I-NEXT: neg s0, s1285; RV32I-NEXT: sll s0, a7, s0286; RV32I-NEXT: or t2, t2, s0287; RV32I-NEXT: beqz s1, .LBB6_20288; RV32I-NEXT: .LBB6_19:289; RV32I-NEXT: mv a3, t2290; RV32I-NEXT: .LBB6_20:291; RV32I-NEXT: bltu s1, t0, .LBB6_22292; RV32I-NEXT: # %bb.21:293; RV32I-NEXT: li a7, 0294; RV32I-NEXT: bltu a2, t1, .LBB6_23295; RV32I-NEXT: j .LBB6_24296; RV32I-NEXT: .LBB6_22:297; RV32I-NEXT: srl a7, a7, a2298; RV32I-NEXT: bgeu a2, t1, .LBB6_24299; RV32I-NEXT: .LBB6_23:300; RV32I-NEXT: or a3, t3, t6301; RV32I-NEXT: or a7, t4, t5302; RV32I-NEXT: .LBB6_24:303; RV32I-NEXT: bnez a2, .LBB6_28304; RV32I-NEXT: # %bb.25:305; RV32I-NEXT: bltu a2, t1, .LBB6_27306; RV32I-NEXT: .LBB6_26:307; RV32I-NEXT: li a4, 0308; RV32I-NEXT: li a6, 0309; RV32I-NEXT: .LBB6_27:310; RV32I-NEXT: sw a5, 0(a0)311; RV32I-NEXT: sw a1, 4(a0)312; RV32I-NEXT: sw a4, 8(a0)313; RV32I-NEXT: sw a6, 12(a0)314; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload315; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload316; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload317; RV32I-NEXT: addi sp, sp, 16318; RV32I-NEXT: ret319; RV32I-NEXT: .LBB6_28:320; RV32I-NEXT: mv a5, a3321; RV32I-NEXT: mv a1, a7322; RV32I-NEXT: bgeu a2, t1, .LBB6_26323; RV32I-NEXT: j .LBB6_27324;325; RV64I-LABEL: lshr128:326; RV64I: # %bb.0:327; RV64I-NEXT: li a3, 64328; RV64I-NEXT: bltu a2, a3, .LBB6_2329; RV64I-NEXT: # %bb.1:330; RV64I-NEXT: sub a4, a2, a3331; RV64I-NEXT: srl a4, a1, a4332; RV64I-NEXT: bnez a2, .LBB6_3333; RV64I-NEXT: j .LBB6_4334; RV64I-NEXT: .LBB6_2:335; RV64I-NEXT: srl a4, a0, a2336; RV64I-NEXT: neg a5, a2337; RV64I-NEXT: sll a5, a1, a5338; RV64I-NEXT: or a4, a4, a5339; RV64I-NEXT: beqz a2, .LBB6_4340; RV64I-NEXT: .LBB6_3:341; RV64I-NEXT: mv a0, a4342; RV64I-NEXT: .LBB6_4:343; RV64I-NEXT: bltu a2, a3, .LBB6_6344; RV64I-NEXT: # %bb.5:345; RV64I-NEXT: li a1, 0346; RV64I-NEXT: ret347; RV64I-NEXT: .LBB6_6:348; RV64I-NEXT: srl a1, a1, a2349; RV64I-NEXT: ret350 %1 = lshr i128 %a, %b351 ret i128 %1352}353 354define i128 @ashr128(i128 %a, i128 %b) nounwind {355; RV32I-LABEL: ashr128:356; RV32I: # %bb.0:357; RV32I-NEXT: lw a2, 0(a2)358; RV32I-NEXT: lw a4, 8(a1)359; RV32I-NEXT: lw a3, 12(a1)360; RV32I-NEXT: li t0, 32361; RV32I-NEXT: srl t2, a4, a2362; RV32I-NEXT: neg t6, a2363; RV32I-NEXT: sll t5, a3, t6364; RV32I-NEXT: bltu a2, t0, .LBB7_2365; RV32I-NEXT: # %bb.1:366; RV32I-NEXT: sra a6, a3, a2367; RV32I-NEXT: mv a5, a4368; RV32I-NEXT: bnez a2, .LBB7_3369; RV32I-NEXT: j .LBB7_4370; RV32I-NEXT: .LBB7_2:371; RV32I-NEXT: or a6, t2, t5372; RV32I-NEXT: mv a5, a4373; RV32I-NEXT: beqz a2, .LBB7_4374; RV32I-NEXT: .LBB7_3:375; RV32I-NEXT: mv a5, a6376; RV32I-NEXT: .LBB7_4:377; RV32I-NEXT: lw a6, 0(a1)378; RV32I-NEXT: lw a1, 4(a1)379; RV32I-NEXT: bltu a2, t0, .LBB7_6380; RV32I-NEXT: # %bb.5:381; RV32I-NEXT: srai a7, a3, 31382; RV32I-NEXT: srl t4, a1, a2383; RV32I-NEXT: j .LBB7_7384; RV32I-NEXT: .LBB7_6:385; RV32I-NEXT: sra a7, a3, a2386; RV32I-NEXT: srl t1, a6, a2387; RV32I-NEXT: sll t3, a1, t6388; RV32I-NEXT: or t4, t1, t3389; RV32I-NEXT: .LBB7_7:390; RV32I-NEXT: li t1, 64391; RV32I-NEXT: mv t3, a6392; RV32I-NEXT: beqz a2, .LBB7_9393; RV32I-NEXT: # %bb.8:394; RV32I-NEXT: mv t3, t4395; RV32I-NEXT: .LBB7_9:396; RV32I-NEXT: addi sp, sp, -16397; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill398; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill399; RV32I-NEXT: sw s2, 4(sp) # 4-byte Folded Spill400; RV32I-NEXT: sub s0, t1, a2401; RV32I-NEXT: bltu a2, t0, .LBB7_12402; RV32I-NEXT: # %bb.10:403; RV32I-NEXT: li t4, 0404; RV32I-NEXT: bgeu s0, t0, .LBB7_13405; RV32I-NEXT: .LBB7_11:406; RV32I-NEXT: sll t6, a4, t6407; RV32I-NEXT: neg s1, s0408; RV32I-NEXT: srl s1, a4, s1409; RV32I-NEXT: or s2, s1, t5410; RV32I-NEXT: j .LBB7_14411; RV32I-NEXT: .LBB7_12:412; RV32I-NEXT: srl t4, a1, a2413; RV32I-NEXT: bltu s0, t0, .LBB7_11414; RV32I-NEXT: .LBB7_13:415; RV32I-NEXT: li t6, 0416; RV32I-NEXT: sll s2, a4, s0417; RV32I-NEXT: .LBB7_14:418; RV32I-NEXT: addi s1, a2, -64419; RV32I-NEXT: mv t5, a3420; RV32I-NEXT: beqz s0, .LBB7_16421; RV32I-NEXT: # %bb.15:422; RV32I-NEXT: mv t5, s2423; RV32I-NEXT: .LBB7_16:424; RV32I-NEXT: bltu s1, t0, .LBB7_18425; RV32I-NEXT: # %bb.17:426; RV32I-NEXT: sra t2, a3, s1427; RV32I-NEXT: bnez s1, .LBB7_19428; RV32I-NEXT: j .LBB7_20429; RV32I-NEXT: .LBB7_18:430; RV32I-NEXT: neg s0, s1431; RV32I-NEXT: sll s0, a3, s0432; RV32I-NEXT: or t2, t2, s0433; RV32I-NEXT: beqz s1, .LBB7_20434; RV32I-NEXT: .LBB7_19:435; RV32I-NEXT: mv a4, t2436; RV32I-NEXT: .LBB7_20:437; RV32I-NEXT: bltu s1, t0, .LBB7_22438; RV32I-NEXT: # %bb.21:439; RV32I-NEXT: srai t0, a3, 31440; RV32I-NEXT: bltu a2, t1, .LBB7_23441; RV32I-NEXT: j .LBB7_24442; RV32I-NEXT: .LBB7_22:443; RV32I-NEXT: sra t0, a3, a2444; RV32I-NEXT: bgeu a2, t1, .LBB7_24445; RV32I-NEXT: .LBB7_23:446; RV32I-NEXT: or a4, t3, t6447; RV32I-NEXT: or t0, t4, t5448; RV32I-NEXT: .LBB7_24:449; RV32I-NEXT: bnez a2, .LBB7_28450; RV32I-NEXT: # %bb.25:451; RV32I-NEXT: bltu a2, t1, .LBB7_27452; RV32I-NEXT: .LBB7_26:453; RV32I-NEXT: srai a5, a3, 31454; RV32I-NEXT: mv a7, a5455; RV32I-NEXT: .LBB7_27:456; RV32I-NEXT: sw a6, 0(a0)457; RV32I-NEXT: sw a1, 4(a0)458; RV32I-NEXT: sw a5, 8(a0)459; RV32I-NEXT: sw a7, 12(a0)460; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload461; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload462; RV32I-NEXT: lw s2, 4(sp) # 4-byte Folded Reload463; RV32I-NEXT: addi sp, sp, 16464; RV32I-NEXT: ret465; RV32I-NEXT: .LBB7_28:466; RV32I-NEXT: mv a6, a4467; RV32I-NEXT: mv a1, t0468; RV32I-NEXT: bgeu a2, t1, .LBB7_26469; RV32I-NEXT: j .LBB7_27470;471; RV64I-LABEL: ashr128:472; RV64I: # %bb.0:473; RV64I-NEXT: li a3, 64474; RV64I-NEXT: bltu a2, a3, .LBB7_2475; RV64I-NEXT: # %bb.1:476; RV64I-NEXT: sub a4, a2, a3477; RV64I-NEXT: sra a4, a1, a4478; RV64I-NEXT: bnez a2, .LBB7_3479; RV64I-NEXT: j .LBB7_4480; RV64I-NEXT: .LBB7_2:481; RV64I-NEXT: srl a4, a0, a2482; RV64I-NEXT: neg a5, a2483; RV64I-NEXT: sll a5, a1, a5484; RV64I-NEXT: or a4, a4, a5485; RV64I-NEXT: beqz a2, .LBB7_4486; RV64I-NEXT: .LBB7_3:487; RV64I-NEXT: mv a0, a4488; RV64I-NEXT: .LBB7_4:489; RV64I-NEXT: bltu a2, a3, .LBB7_6490; RV64I-NEXT: # %bb.5:491; RV64I-NEXT: srai a1, a1, 63492; RV64I-NEXT: ret493; RV64I-NEXT: .LBB7_6:494; RV64I-NEXT: sra a1, a1, a2495; RV64I-NEXT: ret496 %1 = ashr i128 %a, %b497 ret i128 %1498}499 500define i128 @shl128(i128 %a, i128 %b) nounwind {501; RV32I-LABEL: shl128:502; RV32I: # %bb.0:503; RV32I-NEXT: lw a2, 0(a2)504; RV32I-NEXT: lw a7, 0(a1)505; RV32I-NEXT: lw a3, 4(a1)506; RV32I-NEXT: li a6, 64507; RV32I-NEXT: li t1, 32508; RV32I-NEXT: neg t5, a2509; RV32I-NEXT: srl t2, a7, t5510; RV32I-NEXT: sll t0, a3, a2511; RV32I-NEXT: bltu a2, t1, .LBB8_2512; RV32I-NEXT: # %bb.1:513; RV32I-NEXT: li a4, 0514; RV32I-NEXT: sll t3, a7, a2515; RV32I-NEXT: j .LBB8_3516; RV32I-NEXT: .LBB8_2:517; RV32I-NEXT: sll a4, a7, a2518; RV32I-NEXT: or t3, t2, t0519; RV32I-NEXT: .LBB8_3:520; RV32I-NEXT: sub t4, a6, a2521; RV32I-NEXT: mv a5, a3522; RV32I-NEXT: beqz a2, .LBB8_5523; RV32I-NEXT: # %bb.4:524; RV32I-NEXT: mv a5, t3525; RV32I-NEXT: .LBB8_5:526; RV32I-NEXT: bltu t4, t1, .LBB8_7527; RV32I-NEXT: # %bb.6:528; RV32I-NEXT: srl t2, a3, t4529; RV32I-NEXT: mv t3, a7530; RV32I-NEXT: bnez t4, .LBB8_8531; RV32I-NEXT: j .LBB8_9532; RV32I-NEXT: .LBB8_7:533; RV32I-NEXT: neg t3, t4534; RV32I-NEXT: sll t3, a3, t3535; RV32I-NEXT: or t2, t2, t3536; RV32I-NEXT: mv t3, a7537; RV32I-NEXT: beqz t4, .LBB8_9538; RV32I-NEXT: .LBB8_8:539; RV32I-NEXT: mv t3, t2540; RV32I-NEXT: .LBB8_9:541; RV32I-NEXT: bltu t4, t1, .LBB8_11542; RV32I-NEXT: # %bb.10:543; RV32I-NEXT: li t4, 0544; RV32I-NEXT: j .LBB8_12545; RV32I-NEXT: .LBB8_11:546; RV32I-NEXT: srl t4, a3, t5547; RV32I-NEXT: .LBB8_12:548; RV32I-NEXT: addi sp, sp, -16549; RV32I-NEXT: sw s0, 12(sp) # 4-byte Folded Spill550; RV32I-NEXT: sw s1, 8(sp) # 4-byte Folded Spill551; RV32I-NEXT: lw t2, 8(a1)552; RV32I-NEXT: lw a1, 12(a1)553; RV32I-NEXT: bltu a2, t1, .LBB8_14554; RV32I-NEXT: # %bb.13:555; RV32I-NEXT: li t6, 0556; RV32I-NEXT: sll s1, t2, a2557; RV32I-NEXT: j .LBB8_15558; RV32I-NEXT: .LBB8_14:559; RV32I-NEXT: sll t6, t2, a2560; RV32I-NEXT: srl t5, t2, t5561; RV32I-NEXT: sll s0, a1, a2562; RV32I-NEXT: or s1, t5, s0563; RV32I-NEXT: .LBB8_15:564; RV32I-NEXT: addi s0, a2, -64565; RV32I-NEXT: mv t5, a1566; RV32I-NEXT: beqz a2, .LBB8_17567; RV32I-NEXT: # %bb.16:568; RV32I-NEXT: mv t5, s1569; RV32I-NEXT: .LBB8_17:570; RV32I-NEXT: bltu s0, t1, .LBB8_19571; RV32I-NEXT: # %bb.18:572; RV32I-NEXT: li t1, 0573; RV32I-NEXT: sll a7, a7, s0574; RV32I-NEXT: bnez s0, .LBB8_20575; RV32I-NEXT: j .LBB8_21576; RV32I-NEXT: .LBB8_19:577; RV32I-NEXT: sll t1, a7, a2578; RV32I-NEXT: neg s1, s0579; RV32I-NEXT: srl a7, a7, s1580; RV32I-NEXT: or a7, a7, t0581; RV32I-NEXT: beqz s0, .LBB8_21582; RV32I-NEXT: .LBB8_20:583; RV32I-NEXT: mv a3, a7584; RV32I-NEXT: .LBB8_21:585; RV32I-NEXT: bltu a2, a6, .LBB8_23586; RV32I-NEXT: # %bb.22:587; RV32I-NEXT: li a4, 0588; RV32I-NEXT: li a5, 0589; RV32I-NEXT: bnez a2, .LBB8_24590; RV32I-NEXT: j .LBB8_25591; RV32I-NEXT: .LBB8_23:592; RV32I-NEXT: or t1, t3, t6593; RV32I-NEXT: or a3, t4, t5594; RV32I-NEXT: beqz a2, .LBB8_25595; RV32I-NEXT: .LBB8_24:596; RV32I-NEXT: mv t2, t1597; RV32I-NEXT: mv a1, a3598; RV32I-NEXT: .LBB8_25:599; RV32I-NEXT: sw a4, 0(a0)600; RV32I-NEXT: sw a5, 4(a0)601; RV32I-NEXT: sw t2, 8(a0)602; RV32I-NEXT: sw a1, 12(a0)603; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload604; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload605; RV32I-NEXT: addi sp, sp, 16606; RV32I-NEXT: ret607;608; RV64I-LABEL: shl128:609; RV64I: # %bb.0:610; RV64I-NEXT: mv a3, a0611; RV64I-NEXT: li a4, 64612; RV64I-NEXT: bltu a2, a4, .LBB8_2613; RV64I-NEXT: # %bb.1:614; RV64I-NEXT: li a0, 0615; RV64I-NEXT: sub a4, a2, a4616; RV64I-NEXT: sll a3, a3, a4617; RV64I-NEXT: bnez a2, .LBB8_3618; RV64I-NEXT: j .LBB8_4619; RV64I-NEXT: .LBB8_2:620; RV64I-NEXT: sll a0, a3, a2621; RV64I-NEXT: neg a4, a2622; RV64I-NEXT: srl a3, a3, a4623; RV64I-NEXT: sll a4, a1, a2624; RV64I-NEXT: or a3, a3, a4625; RV64I-NEXT: beqz a2, .LBB8_4626; RV64I-NEXT: .LBB8_3:627; RV64I-NEXT: mv a1, a3628; RV64I-NEXT: .LBB8_4:629; RV64I-NEXT: ret630 %1 = shl i128 %a, %b631 ret i128 %1632}633 634define i64 @fshr64_minsize(i64 %a, i64 %b) minsize nounwind {635; RV32I-LABEL: fshr64_minsize:636; RV32I: # %bb.0:637; RV32I-NEXT: andi a5, a2, 63638; RV32I-NEXT: li a4, 32639; RV32I-NEXT: bltu a5, a4, .LBB9_2640; RV32I-NEXT: # %bb.1:641; RV32I-NEXT: srl a6, a1, a5642; RV32I-NEXT: j .LBB9_3643; RV32I-NEXT: .LBB9_2:644; RV32I-NEXT: srl a3, a0, a2645; RV32I-NEXT: neg a6, a5646; RV32I-NEXT: sll a6, a1, a6647; RV32I-NEXT: or a6, a3, a6648; RV32I-NEXT: .LBB9_3:649; RV32I-NEXT: mv a3, a0650; RV32I-NEXT: beqz a5, .LBB9_5651; RV32I-NEXT: # %bb.4:652; RV32I-NEXT: mv a3, a6653; RV32I-NEXT: .LBB9_5:654; RV32I-NEXT: neg a6, a2655; RV32I-NEXT: bltu a5, a4, .LBB9_7656; RV32I-NEXT: # %bb.6:657; RV32I-NEXT: li a2, 0658; RV32I-NEXT: j .LBB9_8659; RV32I-NEXT: .LBB9_7:660; RV32I-NEXT: srl a2, a1, a2661; RV32I-NEXT: .LBB9_8:662; RV32I-NEXT: andi a5, a6, 63663; RV32I-NEXT: bltu a5, a4, .LBB9_10664; RV32I-NEXT: # %bb.9:665; RV32I-NEXT: li a4, 0666; RV32I-NEXT: sll a0, a0, a5667; RV32I-NEXT: bnez a5, .LBB9_11668; RV32I-NEXT: j .LBB9_12669; RV32I-NEXT: .LBB9_10:670; RV32I-NEXT: sll a4, a0, a6671; RV32I-NEXT: neg a7, a5672; RV32I-NEXT: srl a0, a0, a7673; RV32I-NEXT: sll a6, a1, a6674; RV32I-NEXT: or a0, a0, a6675; RV32I-NEXT: beqz a5, .LBB9_12676; RV32I-NEXT: .LBB9_11:677; RV32I-NEXT: mv a1, a0678; RV32I-NEXT: .LBB9_12:679; RV32I-NEXT: or a0, a3, a4680; RV32I-NEXT: or a1, a2, a1681; RV32I-NEXT: ret682;683; RV64I-LABEL: fshr64_minsize:684; RV64I: # %bb.0:685; RV64I-NEXT: neg a2, a1686; RV64I-NEXT: srl a1, a0, a1687; RV64I-NEXT: sll a0, a0, a2688; RV64I-NEXT: or a0, a1, a0689; RV64I-NEXT: ret690 %res = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)691 ret i64 %res692}693 694define i128 @fshr128_minsize(i128 %a, i128 %b) minsize nounwind {695; RV32I-LABEL: fshr128_minsize:696; RV32I: # %bb.0:697; RV32I-NEXT: lw t3, 0(a2)698; RV32I-NEXT: lw a2, 8(a1)699; RV32I-NEXT: lw a3, 12(a1)700; RV32I-NEXT: andi t4, t3, 127701; RV32I-NEXT: li a6, 32702; RV32I-NEXT: neg t6, t4703; RV32I-NEXT: sll t5, a3, t6704; RV32I-NEXT: bltu t4, a6, .LBB10_2705; RV32I-NEXT: # %bb.1:706; RV32I-NEXT: srl a5, a3, t4707; RV32I-NEXT: j .LBB10_3708; RV32I-NEXT: .LBB10_2:709; RV32I-NEXT: srl a4, a2, t3710; RV32I-NEXT: or a5, a4, t5711; RV32I-NEXT: .LBB10_3:712; RV32I-NEXT: mv a4, a2713; RV32I-NEXT: beqz t4, .LBB10_5714; RV32I-NEXT: # %bb.4:715; RV32I-NEXT: mv a4, a5716; RV32I-NEXT: .LBB10_5:717; RV32I-NEXT: lw a7, 0(a1)718; RV32I-NEXT: lw a5, 4(a1)719; RV32I-NEXT: bltu t4, a6, .LBB10_7720; RV32I-NEXT: # %bb.6:721; RV32I-NEXT: li a1, 0722; RV32I-NEXT: srl t2, a5, t4723; RV32I-NEXT: j .LBB10_8724; RV32I-NEXT: .LBB10_7:725; RV32I-NEXT: srl a1, a3, t3726; RV32I-NEXT: srl t0, a7, t3727; RV32I-NEXT: sll t1, a5, t6728; RV32I-NEXT: or t2, t0, t1729; RV32I-NEXT: .LBB10_8:730; RV32I-NEXT: li t0, 64731; RV32I-NEXT: mv t1, a7732; RV32I-NEXT: beqz t4, .LBB10_10733; RV32I-NEXT: # %bb.9:734; RV32I-NEXT: mv t1, t2735; RV32I-NEXT: .LBB10_10:736; RV32I-NEXT: addi sp, sp, -32737; RV32I-NEXT: sw s0, 28(sp) # 4-byte Folded Spill738; RV32I-NEXT: sw s1, 24(sp) # 4-byte Folded Spill739; RV32I-NEXT: sw s2, 20(sp) # 4-byte Folded Spill740; RV32I-NEXT: sw s3, 16(sp) # 4-byte Folded Spill741; RV32I-NEXT: sw s4, 12(sp) # 4-byte Folded Spill742; RV32I-NEXT: sub s0, t0, t4743; RV32I-NEXT: bltu t4, a6, .LBB10_13744; RV32I-NEXT: # %bb.11:745; RV32I-NEXT: li t2, 0746; RV32I-NEXT: bgeu s0, a6, .LBB10_14747; RV32I-NEXT: .LBB10_12:748; RV32I-NEXT: sll t6, a2, t6749; RV32I-NEXT: neg s1, s0750; RV32I-NEXT: srl s1, a2, s1751; RV32I-NEXT: or s2, s1, t5752; RV32I-NEXT: j .LBB10_15753; RV32I-NEXT: .LBB10_13:754; RV32I-NEXT: srl t2, a5, t3755; RV32I-NEXT: bltu s0, a6, .LBB10_12756; RV32I-NEXT: .LBB10_14:757; RV32I-NEXT: li t6, 0758; RV32I-NEXT: sll s2, a2, s0759; RV32I-NEXT: .LBB10_15:760; RV32I-NEXT: addi s1, t4, -64761; RV32I-NEXT: mv t5, a3762; RV32I-NEXT: beqz s0, .LBB10_17763; RV32I-NEXT: # %bb.16:764; RV32I-NEXT: mv t5, s2765; RV32I-NEXT: .LBB10_17:766; RV32I-NEXT: bltu s1, a6, .LBB10_19767; RV32I-NEXT: # %bb.18:768; RV32I-NEXT: srl s2, a3, s1769; RV32I-NEXT: j .LBB10_20770; RV32I-NEXT: .LBB10_19:771; RV32I-NEXT: srl s0, a2, t4772; RV32I-NEXT: neg s2, s1773; RV32I-NEXT: sll s2, a3, s2774; RV32I-NEXT: or s2, s0, s2775; RV32I-NEXT: .LBB10_20:776; RV32I-NEXT: mv s0, a2777; RV32I-NEXT: beqz s1, .LBB10_22778; RV32I-NEXT: # %bb.21:779; RV32I-NEXT: mv s0, s2780; RV32I-NEXT: .LBB10_22:781; RV32I-NEXT: bltu s1, a6, .LBB10_24782; RV32I-NEXT: # %bb.23:783; RV32I-NEXT: li s1, 0784; RV32I-NEXT: bltu t4, t0, .LBB10_25785; RV32I-NEXT: j .LBB10_26786; RV32I-NEXT: .LBB10_24:787; RV32I-NEXT: srl s1, a3, t4788; RV32I-NEXT: bgeu t4, t0, .LBB10_26789; RV32I-NEXT: .LBB10_25:790; RV32I-NEXT: or s0, t1, t6791; RV32I-NEXT: or s1, t2, t5792; RV32I-NEXT: .LBB10_26:793; RV32I-NEXT: mv t1, a7794; RV32I-NEXT: mv t2, a5795; RV32I-NEXT: beqz t4, .LBB10_28796; RV32I-NEXT: # %bb.27:797; RV32I-NEXT: mv t1, s0798; RV32I-NEXT: mv t2, s1799; RV32I-NEXT: .LBB10_28:800; RV32I-NEXT: neg t6, t3801; RV32I-NEXT: bltu t4, t0, .LBB10_30802; RV32I-NEXT: # %bb.29:803; RV32I-NEXT: li a4, 0804; RV32I-NEXT: li a1, 0805; RV32I-NEXT: .LBB10_30:806; RV32I-NEXT: andi t3, t6, 127807; RV32I-NEXT: neg s2, t3808; RV32I-NEXT: srl s0, a7, s2809; RV32I-NEXT: bltu t3, a6, .LBB10_32810; RV32I-NEXT: # %bb.31:811; RV32I-NEXT: li t4, 0812; RV32I-NEXT: sll s3, a7, t3813; RV32I-NEXT: j .LBB10_33814; RV32I-NEXT: .LBB10_32:815; RV32I-NEXT: sll t4, a7, t6816; RV32I-NEXT: sll t5, a5, t6817; RV32I-NEXT: or s3, s0, t5818; RV32I-NEXT: .LBB10_33:819; RV32I-NEXT: sub s1, t0, t3820; RV32I-NEXT: mv t5, a5821; RV32I-NEXT: beqz t3, .LBB10_35822; RV32I-NEXT: # %bb.34:823; RV32I-NEXT: mv t5, s3824; RV32I-NEXT: .LBB10_35:825; RV32I-NEXT: bltu s1, a6, .LBB10_37826; RV32I-NEXT: # %bb.36:827; RV32I-NEXT: srl s3, a5, s1828; RV32I-NEXT: j .LBB10_38829; RV32I-NEXT: .LBB10_37:830; RV32I-NEXT: neg s3, s1831; RV32I-NEXT: sll s3, a5, s3832; RV32I-NEXT: or s3, s0, s3833; RV32I-NEXT: .LBB10_38:834; RV32I-NEXT: mv s0, a7835; RV32I-NEXT: beqz s1, .LBB10_40836; RV32I-NEXT: # %bb.39:837; RV32I-NEXT: mv s0, s3838; RV32I-NEXT: .LBB10_40:839; RV32I-NEXT: bltu s1, a6, .LBB10_43840; RV32I-NEXT: # %bb.41:841; RV32I-NEXT: li s1, 0842; RV32I-NEXT: bgeu t3, a6, .LBB10_44843; RV32I-NEXT: .LBB10_42:844; RV32I-NEXT: sll s3, a2, t6845; RV32I-NEXT: srl s2, a2, s2846; RV32I-NEXT: sll t6, a3, t6847; RV32I-NEXT: or s4, s2, t6848; RV32I-NEXT: j .LBB10_45849; RV32I-NEXT: .LBB10_43:850; RV32I-NEXT: srl s1, a5, s2851; RV32I-NEXT: bltu t3, a6, .LBB10_42852; RV32I-NEXT: .LBB10_44:853; RV32I-NEXT: li s3, 0854; RV32I-NEXT: sll s4, a2, t3855; RV32I-NEXT: .LBB10_45:856; RV32I-NEXT: addi s2, t3, -64857; RV32I-NEXT: mv t6, a3858; RV32I-NEXT: beqz t3, .LBB10_47859; RV32I-NEXT: # %bb.46:860; RV32I-NEXT: mv t6, s4861; RV32I-NEXT: .LBB10_47:862; RV32I-NEXT: bltu s2, a6, .LBB10_49863; RV32I-NEXT: # %bb.48:864; RV32I-NEXT: li a6, 0865; RV32I-NEXT: sll a7, a7, s2866; RV32I-NEXT: bnez s2, .LBB10_50867; RV32I-NEXT: j .LBB10_51868; RV32I-NEXT: .LBB10_49:869; RV32I-NEXT: sll a6, a7, t3870; RV32I-NEXT: neg s4, s2871; RV32I-NEXT: srl a7, a7, s4872; RV32I-NEXT: sll s4, a5, t3873; RV32I-NEXT: or a7, a7, s4874; RV32I-NEXT: beqz s2, .LBB10_51875; RV32I-NEXT: .LBB10_50:876; RV32I-NEXT: mv a5, a7877; RV32I-NEXT: .LBB10_51:878; RV32I-NEXT: bltu t3, t0, .LBB10_53879; RV32I-NEXT: # %bb.52:880; RV32I-NEXT: li t4, 0881; RV32I-NEXT: li t5, 0882; RV32I-NEXT: bnez t3, .LBB10_54883; RV32I-NEXT: j .LBB10_55884; RV32I-NEXT: .LBB10_53:885; RV32I-NEXT: or a6, s0, s3886; RV32I-NEXT: or a5, s1, t6887; RV32I-NEXT: beqz t3, .LBB10_55888; RV32I-NEXT: .LBB10_54:889; RV32I-NEXT: mv a2, a6890; RV32I-NEXT: mv a3, a5891; RV32I-NEXT: .LBB10_55:892; RV32I-NEXT: or a5, t1, t4893; RV32I-NEXT: or a6, t2, t5894; RV32I-NEXT: or a2, a4, a2895; RV32I-NEXT: or a1, a1, a3896; RV32I-NEXT: sw a5, 0(a0)897; RV32I-NEXT: sw a6, 4(a0)898; RV32I-NEXT: sw a2, 8(a0)899; RV32I-NEXT: sw a1, 12(a0)900; RV32I-NEXT: lw s0, 28(sp) # 4-byte Folded Reload901; RV32I-NEXT: lw s1, 24(sp) # 4-byte Folded Reload902; RV32I-NEXT: lw s2, 20(sp) # 4-byte Folded Reload903; RV32I-NEXT: lw s3, 16(sp) # 4-byte Folded Reload904; RV32I-NEXT: lw s4, 12(sp) # 4-byte Folded Reload905; RV32I-NEXT: addi sp, sp, 32906; RV32I-NEXT: ret907;908; RV64I-LABEL: fshr128_minsize:909; RV64I: # %bb.0:910; RV64I-NEXT: andi a5, a2, 127911; RV64I-NEXT: li a4, 64912; RV64I-NEXT: bltu a5, a4, .LBB10_2913; RV64I-NEXT: # %bb.1:914; RV64I-NEXT: sub a3, a5, a4915; RV64I-NEXT: srl a6, a1, a3916; RV64I-NEXT: j .LBB10_3917; RV64I-NEXT: .LBB10_2:918; RV64I-NEXT: srl a3, a0, a2919; RV64I-NEXT: neg a6, a5920; RV64I-NEXT: sll a6, a1, a6921; RV64I-NEXT: or a6, a3, a6922; RV64I-NEXT: .LBB10_3:923; RV64I-NEXT: mv a3, a0924; RV64I-NEXT: beqz a5, .LBB10_5925; RV64I-NEXT: # %bb.4:926; RV64I-NEXT: mv a3, a6927; RV64I-NEXT: .LBB10_5:928; RV64I-NEXT: neg a7, a2929; RV64I-NEXT: bltu a5, a4, .LBB10_7930; RV64I-NEXT: # %bb.6:931; RV64I-NEXT: li a2, 0932; RV64I-NEXT: j .LBB10_8933; RV64I-NEXT: .LBB10_7:934; RV64I-NEXT: srl a2, a1, a2935; RV64I-NEXT: .LBB10_8:936; RV64I-NEXT: andi a6, a7, 127937; RV64I-NEXT: bltu a6, a4, .LBB10_10938; RV64I-NEXT: # %bb.9:939; RV64I-NEXT: li a5, 0940; RV64I-NEXT: sub a4, a6, a4941; RV64I-NEXT: sll a0, a0, a4942; RV64I-NEXT: bnez a6, .LBB10_11943; RV64I-NEXT: j .LBB10_12944; RV64I-NEXT: .LBB10_10:945; RV64I-NEXT: sll a5, a0, a7946; RV64I-NEXT: neg a4, a6947; RV64I-NEXT: srl a0, a0, a4948; RV64I-NEXT: sll a4, a1, a7949; RV64I-NEXT: or a0, a0, a4950; RV64I-NEXT: beqz a6, .LBB10_12951; RV64I-NEXT: .LBB10_11:952; RV64I-NEXT: mv a1, a0953; RV64I-NEXT: .LBB10_12:954; RV64I-NEXT: or a0, a3, a5955; RV64I-NEXT: or a1, a2, a1956; RV64I-NEXT: ret957 %res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %b)958 ret i128 %res959}960