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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=riscv32 -mattr=+f,+zfh < %s \3; RUN: | FileCheck %s --check-prefix=RV32F4; RUN: llc -global-isel -mtriple=riscv32 -mattr=+d,+zfh < %s \5; RUN: | FileCheck %s --check-prefix=RV32D6; RUN: llc -global-isel -mtriple=riscv64 -mattr=+f,+zfh < %s \7; RUN: | FileCheck %s --check-prefix=RV64F8; RUN: llc -global-isel -mtriple=riscv64 -mattr=+d,+zfh < %s \9; RUN: | FileCheck %s --check-prefix=RV64D10 11define void @zero_f16(ptr %i) {12; RV32F-LABEL: zero_f16:13; RV32F: # %bb.0: # %entry14; RV32F-NEXT: sh zero, 0(a0)15; RV32F-NEXT: ret16;17; RV32D-LABEL: zero_f16:18; RV32D: # %bb.0: # %entry19; RV32D-NEXT: sh zero, 0(a0)20; RV32D-NEXT: ret21;22; RV64F-LABEL: zero_f16:23; RV64F: # %bb.0: # %entry24; RV64F-NEXT: sh zero, 0(a0)25; RV64F-NEXT: ret26;27; RV64D-LABEL: zero_f16:28; RV64D: # %bb.0: # %entry29; RV64D-NEXT: sh zero, 0(a0)30; RV64D-NEXT: ret31entry:32 store half 0.0, ptr %i, align 433 ret void34}35 36define void @zero_bf16(ptr %i) {37; RV32F-LABEL: zero_bf16:38; RV32F: # %bb.0: # %entry39; RV32F-NEXT: sh zero, 0(a0)40; RV32F-NEXT: ret41;42; RV32D-LABEL: zero_bf16:43; RV32D: # %bb.0: # %entry44; RV32D-NEXT: sh zero, 0(a0)45; RV32D-NEXT: ret46;47; RV64F-LABEL: zero_bf16:48; RV64F: # %bb.0: # %entry49; RV64F-NEXT: sh zero, 0(a0)50; RV64F-NEXT: ret51;52; RV64D-LABEL: zero_bf16:53; RV64D: # %bb.0: # %entry54; RV64D-NEXT: sh zero, 0(a0)55; RV64D-NEXT: ret56entry:57 store bfloat 0.0, ptr %i, align 458 ret void59}60 61define void @zero_f32(ptr %i) {62; RV32F-LABEL: zero_f32:63; RV32F: # %bb.0: # %entry64; RV32F-NEXT: sw zero, 0(a0)65; RV32F-NEXT: ret66;67; RV32D-LABEL: zero_f32:68; RV32D: # %bb.0: # %entry69; RV32D-NEXT: sw zero, 0(a0)70; RV32D-NEXT: ret71;72; RV64F-LABEL: zero_f32:73; RV64F: # %bb.0: # %entry74; RV64F-NEXT: sw zero, 0(a0)75; RV64F-NEXT: ret76;77; RV64D-LABEL: zero_f32:78; RV64D: # %bb.0: # %entry79; RV64D-NEXT: sw zero, 0(a0)80; RV64D-NEXT: ret81entry:82 store float 0.0, ptr %i, align 483 ret void84}85 86 87define void @zero_f64(ptr %i) {88; RV32F-LABEL: zero_f64:89; RV32F: # %bb.0: # %entry90; RV32F-NEXT: lui a1, %hi(.LCPI3_0)91; RV32F-NEXT: addi a1, a1, %lo(.LCPI3_0)92; RV32F-NEXT: lw a2, 0(a1)93; RV32F-NEXT: lw a1, 4(a1)94; RV32F-NEXT: sw a2, 0(a0)95; RV32F-NEXT: sw a1, 4(a0)96; RV32F-NEXT: ret97;98; RV32D-LABEL: zero_f64:99; RV32D: # %bb.0: # %entry100; RV32D-NEXT: fcvt.d.w fa5, zero101; RV32D-NEXT: fsd fa5, 0(a0)102; RV32D-NEXT: ret103;104; RV64F-LABEL: zero_f64:105; RV64F: # %bb.0: # %entry106; RV64F-NEXT: sd zero, 0(a0)107; RV64F-NEXT: ret108;109; RV64D-LABEL: zero_f64:110; RV64D: # %bb.0: # %entry111; RV64D-NEXT: sd zero, 0(a0)112; RV64D-NEXT: ret113entry:114 store double 0.0, ptr %i, align 8115 ret void116}117 118define void @zero_v1f32(ptr %i) {119; RV32F-LABEL: zero_v1f32:120; RV32F: # %bb.0: # %entry121; RV32F-NEXT: sw zero, 0(a0)122; RV32F-NEXT: ret123;124; RV32D-LABEL: zero_v1f32:125; RV32D: # %bb.0: # %entry126; RV32D-NEXT: sw zero, 0(a0)127; RV32D-NEXT: ret128;129; RV64F-LABEL: zero_v1f32:130; RV64F: # %bb.0: # %entry131; RV64F-NEXT: sw zero, 0(a0)132; RV64F-NEXT: ret133;134; RV64D-LABEL: zero_v1f32:135; RV64D: # %bb.0: # %entry136; RV64D-NEXT: sw zero, 0(a0)137; RV64D-NEXT: ret138entry:139 store <1 x float> <float 0.0>, ptr %i, align 8140 ret void141}142 143define void @zero_v2f32(ptr %i) {144; RV32F-LABEL: zero_v2f32:145; RV32F: # %bb.0: # %entry146; RV32F-NEXT: sw zero, 0(a0)147; RV32F-NEXT: sw zero, 4(a0)148; RV32F-NEXT: ret149;150; RV32D-LABEL: zero_v2f32:151; RV32D: # %bb.0: # %entry152; RV32D-NEXT: sw zero, 0(a0)153; RV32D-NEXT: sw zero, 4(a0)154; RV32D-NEXT: ret155;156; RV64F-LABEL: zero_v2f32:157; RV64F: # %bb.0: # %entry158; RV64F-NEXT: sw zero, 0(a0)159; RV64F-NEXT: sw zero, 4(a0)160; RV64F-NEXT: ret161;162; RV64D-LABEL: zero_v2f32:163; RV64D: # %bb.0: # %entry164; RV64D-NEXT: sw zero, 0(a0)165; RV64D-NEXT: sw zero, 4(a0)166; RV64D-NEXT: ret167entry:168 store <2 x float> <float 0.0, float 0.0>, ptr %i, align 8169 ret void170}171 172define void @zero_v4f32(ptr %i) {173; RV32F-LABEL: zero_v4f32:174; RV32F: # %bb.0: # %entry175; RV32F-NEXT: sw zero, 0(a0)176; RV32F-NEXT: sw zero, 4(a0)177; RV32F-NEXT: sw zero, 8(a0)178; RV32F-NEXT: sw zero, 12(a0)179; RV32F-NEXT: ret180;181; RV32D-LABEL: zero_v4f32:182; RV32D: # %bb.0: # %entry183; RV32D-NEXT: sw zero, 0(a0)184; RV32D-NEXT: sw zero, 4(a0)185; RV32D-NEXT: sw zero, 8(a0)186; RV32D-NEXT: sw zero, 12(a0)187; RV32D-NEXT: ret188;189; RV64F-LABEL: zero_v4f32:190; RV64F: # %bb.0: # %entry191; RV64F-NEXT: sw zero, 0(a0)192; RV64F-NEXT: sw zero, 4(a0)193; RV64F-NEXT: sw zero, 8(a0)194; RV64F-NEXT: sw zero, 12(a0)195; RV64F-NEXT: ret196;197; RV64D-LABEL: zero_v4f32:198; RV64D: # %bb.0: # %entry199; RV64D-NEXT: sw zero, 0(a0)200; RV64D-NEXT: sw zero, 4(a0)201; RV64D-NEXT: sw zero, 8(a0)202; RV64D-NEXT: sw zero, 12(a0)203; RV64D-NEXT: ret204entry:205 store <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, ptr %i, align 8206 ret void207}208 209define void @zero_v1f64(ptr %i) {210; RV32F-LABEL: zero_v1f64:211; RV32F: # %bb.0: # %entry212; RV32F-NEXT: lui a1, %hi(.LCPI7_0)213; RV32F-NEXT: addi a1, a1, %lo(.LCPI7_0)214; RV32F-NEXT: lw a2, 0(a1)215; RV32F-NEXT: lw a1, 4(a1)216; RV32F-NEXT: sw a2, 0(a0)217; RV32F-NEXT: sw a1, 4(a0)218; RV32F-NEXT: ret219;220; RV32D-LABEL: zero_v1f64:221; RV32D: # %bb.0: # %entry222; RV32D-NEXT: fcvt.d.w fa5, zero223; RV32D-NEXT: fsd fa5, 0(a0)224; RV32D-NEXT: ret225;226; RV64F-LABEL: zero_v1f64:227; RV64F: # %bb.0: # %entry228; RV64F-NEXT: sd zero, 0(a0)229; RV64F-NEXT: ret230;231; RV64D-LABEL: zero_v1f64:232; RV64D: # %bb.0: # %entry233; RV64D-NEXT: sd zero, 0(a0)234; RV64D-NEXT: ret235entry:236 store <1 x double> <double 0.0>, ptr %i, align 8237 ret void238}239 240define void @zero_v2f64(ptr %i) {241; RV32F-LABEL: zero_v2f64:242; RV32F: # %bb.0: # %entry243; RV32F-NEXT: lui a1, %hi(.LCPI8_0)244; RV32F-NEXT: addi a1, a1, %lo(.LCPI8_0)245; RV32F-NEXT: lw a2, 0(a1)246; RV32F-NEXT: lw a1, 4(a1)247; RV32F-NEXT: sw a2, 0(a0)248; RV32F-NEXT: sw a1, 4(a0)249; RV32F-NEXT: sw a2, 8(a0)250; RV32F-NEXT: sw a1, 12(a0)251; RV32F-NEXT: ret252;253; RV32D-LABEL: zero_v2f64:254; RV32D: # %bb.0: # %entry255; RV32D-NEXT: fcvt.d.w fa5, zero256; RV32D-NEXT: fsd fa5, 0(a0)257; RV32D-NEXT: fsd fa5, 8(a0)258; RV32D-NEXT: ret259;260; RV64F-LABEL: zero_v2f64:261; RV64F: # %bb.0: # %entry262; RV64F-NEXT: sd zero, 0(a0)263; RV64F-NEXT: sd zero, 8(a0)264; RV64F-NEXT: ret265;266; RV64D-LABEL: zero_v2f64:267; RV64D: # %bb.0: # %entry268; RV64D-NEXT: sd zero, 0(a0)269; RV64D-NEXT: sd zero, 8(a0)270; RV64D-NEXT: ret271entry:272 store <2 x double> <double 0.0, double 0.0>, ptr %i, align 8273 ret void274}275 276define void @zero_v4f64(ptr %i) {277; RV32F-LABEL: zero_v4f64:278; RV32F: # %bb.0: # %entry279; RV32F-NEXT: lui a1, %hi(.LCPI9_0)280; RV32F-NEXT: addi a1, a1, %lo(.LCPI9_0)281; RV32F-NEXT: lw a2, 0(a1)282; RV32F-NEXT: lw a1, 4(a1)283; RV32F-NEXT: sw a2, 0(a0)284; RV32F-NEXT: sw a1, 4(a0)285; RV32F-NEXT: sw a2, 8(a0)286; RV32F-NEXT: sw a1, 12(a0)287; RV32F-NEXT: sw a2, 16(a0)288; RV32F-NEXT: sw a1, 20(a0)289; RV32F-NEXT: sw a2, 24(a0)290; RV32F-NEXT: sw a1, 28(a0)291; RV32F-NEXT: ret292;293; RV32D-LABEL: zero_v4f64:294; RV32D: # %bb.0: # %entry295; RV32D-NEXT: fcvt.d.w fa5, zero296; RV32D-NEXT: fsd fa5, 0(a0)297; RV32D-NEXT: fsd fa5, 8(a0)298; RV32D-NEXT: fsd fa5, 16(a0)299; RV32D-NEXT: fsd fa5, 24(a0)300; RV32D-NEXT: ret301;302; RV64F-LABEL: zero_v4f64:303; RV64F: # %bb.0: # %entry304; RV64F-NEXT: sd zero, 0(a0)305; RV64F-NEXT: sd zero, 8(a0)306; RV64F-NEXT: sd zero, 16(a0)307; RV64F-NEXT: sd zero, 24(a0)308; RV64F-NEXT: ret309;310; RV64D-LABEL: zero_v4f64:311; RV64D: # %bb.0: # %entry312; RV64D-NEXT: sd zero, 0(a0)313; RV64D-NEXT: sd zero, 8(a0)314; RV64D-NEXT: sd zero, 16(a0)315; RV64D-NEXT: sd zero, 24(a0)316; RV64D-NEXT: ret317entry:318 store <4 x double> <double 0.0, double 0.0, double 0.0, double 0.0>, ptr %i, align 8319 ret void320}321