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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=riscv32 -global-isel | FileCheck %s --check-prefix=RV32I3; RUN: llc < %s -mtriple=riscv64 -global-isel | FileCheck %s --check-prefix=RV64I4 5define i8 @ucmp.8.8(i8 zeroext %x, i8 zeroext %y) nounwind {6; RV32I-LABEL: ucmp.8.8:7; RV32I: # %bb.0:8; RV32I-NEXT: sltu a2, a1, a09; RV32I-NEXT: sltu a0, a0, a110; RV32I-NEXT: sub a0, a2, a011; RV32I-NEXT: ret12;13; RV64I-LABEL: ucmp.8.8:14; RV64I: # %bb.0:15; RV64I-NEXT: sltu a2, a1, a016; RV64I-NEXT: sltu a0, a0, a117; RV64I-NEXT: sub a0, a2, a018; RV64I-NEXT: ret19 %1 = call i8 @llvm.ucmp(i8 %x, i8 %y)20 ret i8 %121}22 23define i8 @ucmp.8.16(i16 zeroext %x, i16 zeroext %y) nounwind {24; RV32I-LABEL: ucmp.8.16:25; RV32I: # %bb.0:26; RV32I-NEXT: sltu a2, a1, a027; RV32I-NEXT: sltu a0, a0, a128; RV32I-NEXT: sub a0, a2, a029; RV32I-NEXT: ret30;31; RV64I-LABEL: ucmp.8.16:32; RV64I: # %bb.0:33; RV64I-NEXT: sltu a2, a1, a034; RV64I-NEXT: sltu a0, a0, a135; RV64I-NEXT: sub a0, a2, a036; RV64I-NEXT: ret37 %1 = call i8 @llvm.ucmp(i16 %x, i16 %y)38 ret i8 %139}40 41define i8 @ucmp.8.32(i32 %x, i32 %y) nounwind {42; RV32I-LABEL: ucmp.8.32:43; RV32I: # %bb.0:44; RV32I-NEXT: sltu a2, a1, a045; RV32I-NEXT: sltu a0, a0, a146; RV32I-NEXT: sub a0, a2, a047; RV32I-NEXT: ret48;49; RV64I-LABEL: ucmp.8.32:50; RV64I: # %bb.0:51; RV64I-NEXT: sext.w a0, a052; RV64I-NEXT: sext.w a1, a153; RV64I-NEXT: sltu a2, a1, a054; RV64I-NEXT: sltu a0, a0, a155; RV64I-NEXT: sub a0, a2, a056; RV64I-NEXT: ret57 %1 = call i8 @llvm.ucmp(i32 %x, i32 %y)58 ret i8 %159}60 61define i8 @ucmp.8.64(i64 %x, i64 %y) nounwind {62; RV32I-LABEL: ucmp.8.64:63; RV32I: # %bb.0:64; RV32I-NEXT: beq a1, a3, .LBB3_265; RV32I-NEXT: # %bb.1:66; RV32I-NEXT: sltu a4, a3, a167; RV32I-NEXT: sltu a0, a1, a368; RV32I-NEXT: sub a0, a4, a069; RV32I-NEXT: ret70; RV32I-NEXT: .LBB3_2:71; RV32I-NEXT: sltu a4, a2, a072; RV32I-NEXT: sltu a0, a0, a273; RV32I-NEXT: sub a0, a4, a074; RV32I-NEXT: ret75;76; RV64I-LABEL: ucmp.8.64:77; RV64I: # %bb.0:78; RV64I-NEXT: sltu a2, a1, a079; RV64I-NEXT: sltu a0, a0, a180; RV64I-NEXT: sub a0, a2, a081; RV64I-NEXT: ret82 %1 = call i8 @llvm.ucmp(i64 %x, i64 %y)83 ret i8 %184}85 86define i32 @ucmp.32.32(i32 %x, i32 %y) nounwind {87; RV32I-LABEL: ucmp.32.32:88; RV32I: # %bb.0:89; RV32I-NEXT: sltu a2, a1, a090; RV32I-NEXT: sltu a0, a0, a191; RV32I-NEXT: sub a0, a2, a092; RV32I-NEXT: ret93;94; RV64I-LABEL: ucmp.32.32:95; RV64I: # %bb.0:96; RV64I-NEXT: sext.w a0, a097; RV64I-NEXT: sext.w a1, a198; RV64I-NEXT: sltu a2, a1, a099; RV64I-NEXT: sltu a0, a0, a1100; RV64I-NEXT: subw a0, a2, a0101; RV64I-NEXT: ret102 %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)103 ret i32 %1104}105 106define i32 @ucmp.32.32_sext(i32 signext %x, i32 signext %y) nounwind {107; RV32I-LABEL: ucmp.32.32_sext:108; RV32I: # %bb.0:109; RV32I-NEXT: sltu a2, a1, a0110; RV32I-NEXT: sltu a0, a0, a1111; RV32I-NEXT: sub a0, a2, a0112; RV32I-NEXT: ret113;114; RV64I-LABEL: ucmp.32.32_sext:115; RV64I: # %bb.0:116; RV64I-NEXT: sltu a2, a1, a0117; RV64I-NEXT: sltu a0, a0, a1118; RV64I-NEXT: subw a0, a2, a0119; RV64I-NEXT: ret120 %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)121 ret i32 %1122}123 124define i32 @ucmp.32.32_zext(i32 zeroext %x, i32 zeroext %y) nounwind {125; RV32I-LABEL: ucmp.32.32_zext:126; RV32I: # %bb.0:127; RV32I-NEXT: sltu a2, a1, a0128; RV32I-NEXT: sltu a0, a0, a1129; RV32I-NEXT: sub a0, a2, a0130; RV32I-NEXT: ret131;132; RV64I-LABEL: ucmp.32.32_zext:133; RV64I: # %bb.0:134; RV64I-NEXT: sext.w a0, a0135; RV64I-NEXT: sext.w a1, a1136; RV64I-NEXT: sltu a2, a1, a0137; RV64I-NEXT: sltu a0, a0, a1138; RV64I-NEXT: subw a0, a2, a0139; RV64I-NEXT: ret140 %1 = call i32 @llvm.ucmp(i32 %x, i32 %y)141 ret i32 %1142}143 144define i32 @ucmp.32.64(i64 %x, i64 %y) nounwind {145; RV32I-LABEL: ucmp.32.64:146; RV32I: # %bb.0:147; RV32I-NEXT: beq a1, a3, .LBB7_2148; RV32I-NEXT: # %bb.1:149; RV32I-NEXT: sltu a4, a3, a1150; RV32I-NEXT: sltu a0, a1, a3151; RV32I-NEXT: sub a0, a4, a0152; RV32I-NEXT: ret153; RV32I-NEXT: .LBB7_2:154; RV32I-NEXT: sltu a4, a2, a0155; RV32I-NEXT: sltu a0, a0, a2156; RV32I-NEXT: sub a0, a4, a0157; RV32I-NEXT: ret158;159; RV64I-LABEL: ucmp.32.64:160; RV64I: # %bb.0:161; RV64I-NEXT: sltu a2, a1, a0162; RV64I-NEXT: sltu a0, a0, a1163; RV64I-NEXT: subw a0, a2, a0164; RV64I-NEXT: ret165 %1 = call i32 @llvm.ucmp(i64 %x, i64 %y)166 ret i32 %1167}168 169define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {170; RV32I-LABEL: ucmp.64.64:171; RV32I: # %bb.0:172; RV32I-NEXT: beq a1, a3, .LBB8_2173; RV32I-NEXT: # %bb.1:174; RV32I-NEXT: sltu a4, a3, a1175; RV32I-NEXT: sltu a1, a1, a3176; RV32I-NEXT: j .LBB8_3177; RV32I-NEXT: .LBB8_2:178; RV32I-NEXT: sltu a4, a2, a0179; RV32I-NEXT: sltu a1, a0, a2180; RV32I-NEXT: .LBB8_3:181; RV32I-NEXT: sub a0, a4, a1182; RV32I-NEXT: sltu a1, a4, a1183; RV32I-NEXT: neg a1, a1184; RV32I-NEXT: ret185;186; RV64I-LABEL: ucmp.64.64:187; RV64I: # %bb.0:188; RV64I-NEXT: sltu a2, a1, a0189; RV64I-NEXT: sltu a0, a0, a1190; RV64I-NEXT: sub a0, a2, a0191; RV64I-NEXT: ret192 %1 = call i64 @llvm.ucmp(i64 %x, i64 %y)193 ret i64 %1194}195