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1; RUN: llc -mtriple=riscv32 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \2; RUN: grep -v "Verify generated machine code" | \3; RUN: FileCheck %s --check-prefixes=CHECK4; RUN: llc -mtriple=riscv64 -O0 -debug-pass=Structure < %s -o /dev/null 2>&1 | \5; RUN: grep -v "Verify generated machine code" | \6; RUN: FileCheck %s --check-prefixes=CHECK7 8; REQUIRES: asserts9 10; CHECK-LABEL: Pass Arguments:11; CHECK-NEXT: Target Library Information12; CHECK-NEXT: Target Pass Configuration13; CHECK-NEXT: Machine Module Information14; CHECK-NEXT: Target Transform Information15; CHECK-NEXT: Create Garbage Collector Module Metadata16; CHECK-NEXT: Assumption Cache Tracker17; CHECK-NEXT: Profile summary info18; CHECK-NEXT: Machine Branch Probability Analysis19; CHECK-NEXT: ModulePass Manager20; CHECK-NEXT: Pre-ISel Intrinsic Lowering21; CHECK-NEXT: FunctionPass Manager22; CHECK-NEXT: Expand large div/rem23; CHECK-NEXT: Expand fp24; CHECK-NEXT: Expand Atomic instructions25; CHECK-NEXT: RISC-V Zacas ABI fix 26; CHECK-NEXT: Module Verifier27; CHECK-NEXT: Lower Garbage Collection Instructions28; CHECK-NEXT: Shadow Stack GC Lowering29; CHECK-NEXT: Remove unreachable blocks from the CFG30; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)31; CHECK-NEXT: Scalarize Masked Memory Intrinsics32; CHECK-NEXT: Expand reduction intrinsics33; CHECK-NEXT: Exception handling preparation34; CHECK-NEXT: Prepare callbr35; CHECK-NEXT: Safe Stack instrumentation pass36; CHECK-NEXT: Insert stack protectors37; CHECK-NEXT: Module Verifier38; CHECK-NEXT: Assignment Tracking Analysis39; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection40; CHECK-NEXT: Finalize ISel and expand pseudo-instructions41; CHECK-NEXT: Local Stack Slot Allocation42; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass43; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass44; CHECK-NEXT: RISC-V Insert Write VXRM Pass45; CHECK-NEXT: RISC-V Landing Pad Setup46; CHECK-NEXT: RISC-V VMV0 Elimination47; CHECK-NEXT: Init Undef Pass48; CHECK-NEXT: Eliminate PHI nodes for register allocation49; CHECK-NEXT: Two-Address instruction pass50; CHECK-NEXT: Fast Register Allocator51; CHECK-NEXT: RISC-V Insert VSETVLI pass52; CHECK-NEXT: Fast Register Allocator53; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis54; CHECK-NEXT: Fixup Statepoint Caller Saved55; CHECK-NEXT: Lazy Machine Block Frequency Analysis56; CHECK-NEXT: Machine Optimization Remark Emitter57; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization58; CHECK-NEXT: Post-RA pseudo instruction expansion pass59; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass60; CHECK-NEXT: Insert KCFI indirect call checks61; CHECK-NEXT: Analyze Machine Code For Garbage Collection62; CHECK-NEXT: Insert fentry calls63; CHECK-NEXT: Insert XRay ops64; CHECK-NEXT: Implement the 'patchable-function' attribute65; CHECK-NEXT: RISC-V Indirect Branch Tracking66; CHECK-NEXT: Branch relaxation pass67; CHECK-NEXT: RISC-V Make Compressible68; CHECK-NEXT: Contiguously Lay Out Funclets69; CHECK-NEXT: Remove Loads Into Fake Uses70; CHECK-NEXT: StackMap Liveness Analysis71; CHECK-NEXT: Live DEBUG_VALUE analysis72; CHECK-NEXT: Machine Sanitizer Binary Metadata73; CHECK-NEXT: Insert CFI remember/restore state instructions74; CHECK-NEXT: Lazy Machine Block Frequency Analysis75; CHECK-NEXT: Machine Optimization Remark Emitter76; CHECK-NEXT: Stack Frame Layout Analysis77; CHECK-NEXT: RISC-V pseudo instruction expansion pass78; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass79; CHECK-NEXT: Unpack machine instruction bundles80; CHECK-NEXT: Lazy Machine Block Frequency Analysis81; CHECK-NEXT: Machine Optimization Remark Emitter82; CHECK-NEXT: RISC-V Assembly Printer83; CHECK-NEXT: Free MachineFunction84